US 3543269 A
Description (OCR text may contain errors)
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United States Patent US. Cl. 343-5 12 Claims ABSTRACT OF THE DISCLOSURE The invention comprises a method and apparatus for displaying a cyclic information signal and related indicia on a single gun cathode ray tube. For radar application, the video signal received responsively to a single transmitted pulse may be stored in a binary shift register having dual input sections, while the video signal from the preceding pulse is reproduced for analog display at a rate which is a multiple of the real time video reception rate, and the video time compressed display is followed by display of related indicia by the same presentation apparatus. For these purposes, the invention permits the use of a single gun cathode ray tube in a radar operating with minimal, or negligible, dead time between the end of the video signal reception period and the succeeding radar pulse transmission. In another embodiment, the cyclic information signal may be continuously fed for storage in binary form to shift registers arranged for rapid readout and presentation in cooperation with sweep voltages correlated with a reference phase of the cyclic signal derived from another register system, permitting indicia display between the successive information signal displays, without requiring that the display system operate in synchronism with the cyclic information signal.
BACKGROUND OF THE INVENTION The present invention comprises method and apparatus for displaying cyclic video information signals at an accelerated rate on a cathode ray tube with conjoint operation of indicia display generators between successive information displays. The invention may operate synchronously with respect to the cyclic information signal to dislay a full cycle thereof continuously in one sweep operation, or it may operate independently of the period of recurrence of the information signal. In the latter instance, asynchronous operation of the display system will 0 present successive portions of each information signal cycle under time acceleration and permit indicia display in the intervening periods between singal information dislay. While the primary application of the invention involves radar systems, it is generally applicable to the display of any type of cyclic information signal.
The use of radar systems for fire control surveillance frequently requires the juxtaposition of indicia or symbology with related targets for identification purposes. The similar flexible use of applied indicia in conjunction with presentation of a cyclic wave form is often desirable, as for instance during classroom instruction. The present invention provides visually continuous coordinated display of video and indicia data using single gun cathode ray tube presentation.
In one embodiment of the present invention, the complete cycle of the video information signal is stored at its real time rate of reception as binary signals in a shift register comprising a pair of dual input sections. Simultaneously therewith, the binary video singal from the preceding information signal cycle is read out, converted to an analog signal, and displayed on the indicator at a rate "ice which is a multiple of the real time rate of its reception. This video display is followed by generation and display of the appropriate indicia, all during the reception and storage of the next video cycle sequence.
In another form of the present invention, time segments of the video signal are displayed at an accelerated rate, and the indicia displayed during shift register storage of the next succeeding portion of the video signal. The latter embodiment operates asynchronously with regard to the information signal cycles and substantially reduces shift register storage capacity requirements of the system.
DESCRIPTION OF THE PRIOR ART Some prior art systems in the field of the present invention have used multiple gun cathode ray display means for simultaneous application of video and indicial information. Other systems have simultaneously applied video and indicial information by the same electron gun, resulting in degradation of the video display. In further examples of the prior art, indicial display has been effected by interruption of the video display, or radar systems have been required to provide prolonged dead time between the termination of video display and transmission of the subsequent radar pulse. The latter systems represent a serious design compromise, particularly in relation to high velocity targets. Other systems have proposed even more complex expedients involving the use of conversion between basically different rasters, such as conversion from radialplan position presentation to a television type presentation into which the indicia display is incorporated. These expedients have involved complicated display equipment, or necessarily tolerate significant loss of radar range, un desirable symbol flicker, or registration inaccuracies.
SUMMARY In the present invention, the video presentation is accomplished with time compression from a digital storage register, followed by indicia presentation, thus to indicate video and indicial data sequentially with high precision, all during storage of the succeeding video signal cycle, or portion thereof, in the digital memory. Consequently, high resolution display of both types of data is achieved with extremely simple presentation equipment particularly in radar systems designed for optimum operation with minimal, or negligible, dead time. The present invention is, moreover, applicable to existing radar equipment using single gun presentation by incorporating therewith a limited number of components in the combination herein described. Such systems may comprise any conventional types of presentation, including radial plan position pre sentation, type B presentation, or single linear scan presentation employing either beam. deflection or intensity modulation.
BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention are shown in the accompanying drawings, in which:
FIG. 1 comprises a block diagram of a system illustrating the present invention;
FIG. 2 diagrammatically represents representative Waveforms and timing periods in the operation of the system of the invention;
FIG. 3 diagrammatically represents a typical composite display;
FIG. 4 comprises a block diagram of a second embodiment of the invention; and
FIG. 5 diagrammatically represents certain time relations and waveforms of the system of FIG. 4.
DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in block diagram in FIG. 1, the system may comprise a conventional radar transmitter 1 and a radar receiver 2, utilizing, respectively, antennas 3 and 4. The
radar transmitter 1 recurrently transmits radio frequency pulses under control of radar trigger generator 5. The output of trigger generator 5 is shown in FIG. 2, at A, and is also applied to the control circuitry for the remainder of the system to initiate the signal handling operation responsive to each ranging pulse. Consequently, in the specific embodiment shown, the radar trigger generator need not necessarily have a highly stable repetition rate, although such is its preferable operation.
Trigger generator 5 also supplies a signal to sweep control gate 6 to initiate synchronized operation of low frequency clock 7 and high frequency clock 8 as the transmitter fires. The initiating signals to the clocks are supplied from decoder 10 operated with reference to input signals received from radar ranging counter 11 and display ranging period counter 12, both receiving high frequency clock pulse inputs via sweep control gate 6. Assuming that the ranging period under description is the first (11) shown at the left of FIG. 2, the output of the low frequency clock initiates and terminates as shown in FIG. 2C. The clock signal is operationally utilized throughout this period, but while the output of high frequency clock 8 is similarly timed, as shown at G, in FIG. 2, its output, as will appear below, is utilized only during a portion of this period in the signal processing. Its output, as received by counters 11 and 12, is however, employed throughout each cycle for timing control.
In response to the operation of transmitter 1, radar receiver 2 supplies a video output signal persisting through the desired ranging period. As will appear, in order to store this signal train in binary form, it is periodically sampled and converted from its analog voltage value to a digital number. The sampling frequency selected depends on the range resolution desired, and the number of samples taken further depends on the design range of the radar system. The sampling frequency is determined by the repetition rate of low frequency clock 7.
For this purpose, the output of clock 7 is fed through delay means 13 to video detector and hold circuit 14. Circuit 14 may take a variety of forms well known in the art, such as integrating circuit means recurrently cycled into operation at the beginning of each period defined by the output of the low frequency clock signal, and sampled at the end of each cycle thereof by separate threshold, or level, detectors. The output of circuit 14 will accordingly periodically appear at the end of each clock cycle to characterize the video signal during that sampling period. The integrator means is then reset to zero for the succeeding cycle.
Analog to digital converter 15 operates responsively to the highest threshold detector voltage value generated during each sampling period and supplies an output in digital form. While design requirements will determine the resolution with which the analog video signal is converted to its digital counterpart, it is convenient for most applications to employ a three digit binary number system which permits evaluation of the video voltage signal energy according to eight contiguous sub-ranges covering the normal range produced by the radar video signal wave train.
The output of analog to digital converter 15 is stored in, and transferred from, a parallel shift register system com prising dual input sections and 21 operating in connection with output section 22. The output signals from converter 15 are channeled, in alternative ranging cycles, alternately to input register sections 20 and 21, by control gates 23. Signal transfer between input register sections 20 and 21 and output register section 22 is controlled by selector gates 24.
As above noted, the video signal is sampled at a rate established by low frequency clock 7. The clock output is supplied to control gates 23 to apply the binary signal from converter 15 at the end of each sampling period to the input stage of the shift register system. Immediately thereafter, the detector circuits are reset by the delayed clock output for operation in the next subsequent sampling period through delay means 13.
In programming the register system, the radar video signal, as sampled throughout the ranging period, is stored in one of the two input register seections 20, 21, and the terminal section 22. In the next succeeding cycle, this entire binary number sequence is read out at a rapid rate responsively to transfer signals from high frequency clock 8. During this time compressed readout, the initial portion of the video wave train resulting from the next ranging operation is being stored in the other dual input register section at an input rate determined by the low frequency clock. The system is so designed that readout from the final register section 22 is completed before the second input register section has been filled, and the output register section 22 is then connected to the second input section and programmed to operate in combination by the low frequency clock therewith to store the sampled converted video wave train as its reception progresses.
As above noted, the number of stages in the tandem register system will be selected in accordance with the sampling rate and the ranging period for the video signal. The dual input register sections each has the same number of stages, and this number taken together with the number of stages of selection 22 comprises the total storage capacity. The compressed ratio of readout to input times determines the ratio of the number of stages in the input sections to the number of stages in the final section of the register system. In the system shown in FIG. 1, the time compression ratio is 1:4, so that the input sections each comprise one-third as many stages as output section 22. While two complete and separate register sections could be employed, the preferred embodiment provides more efiicient utilization of the binary signal handling equipment.
The shift registers 20-22 may comprise large-scale integrated circuits using standard bipolar semiconductors, or metal oxide silicon (MOS) semiconductor dynamic shift registers. The former olfer higher speed operation, while the latter may be more economical in cost. In some applications, subdivided MOS registers may be used in a multiplexing arrangement. Clock control is applied by the gating system to each stage in each register for signal transfer.
Control gates 23, as noted above, are programmed under the low frequency clock output to transfer the digital signal from converter 15 alternatively to input register section 20* or input register section 21. The desired transmission channel programming is effected under the necessary signals generated by gate control logic 311. The input signal to gate control logic 30 is supplied from decoder 10 and comprises, in the specific arrangement of FIG. 1, sequential pulses shown in FIG. 2 at B. These pulse signals subdivide the ranging period in four equal portions in accordance with the time compression ratio of 1:4 on which the system of FIG. 1 is designed. Accordingly, during the persistence of the low frequency clocking pulses, as shown in FIG. 2 at C, the digitally converted output of this ranging operation is fed through control gates 23 to input register section 20. Simultaneously, the shift pulse control logic 31 supplies transfer pulses from the low frequency clock 7 to input register section 20, as shown at FIG. 2, at D. Decoder network 10, responsively to the outputs of counters 11 and 12, further supplies the necessary inputs to shift pulse conrtol logic network 31 for programming transfer in output register section 22. When register section 20 is filled, moreover, selector gates 24 are programmed by another output signal from gate control logic 30 to transfer the digitalized video sequence from input register section 20 to the final register sec tion 22. Simultaneously, the shift pulse control logic 31 supplies low frequency clock transfer pulses to final register section 22, as shown in FIG. 2, at F, so that its operation is sequenced in synchronism with that of input section 20 to progressively store the complete video sequence on the current ranging operation.
On this ranging cycle, video signal storage is terminated by appropriate outputs from decoder 10 under control of ranging counter 11. At this point, the entire video sequence is digitally stored in register sections 20 and 22. (Radar trigger generator is about to initiate the succeeding cycle, which can follow with a very short, or negligible, radar dead time.
At the end of the ranging period, under control of the output signals from decoder 10, operation of clocks 7 and 8 is terminated during the radar dead time. On generation of the next succeeding radar trigger signal, the latter reinitiates synchronized operation of the two clocks via decoder 10 and counters 11 and 12.
In this alternate cycle, the video signal is again sampled at the low frequency clock rate and stored at the low frequency clock rate in input register section 21 initially, exactly as described for input section for the preceding cycle above (see FIG. 2E). The digital counterpart of the previous video sequence is read out of the register memory system at a time compressed rate.
The high frequency clock output is again supplied to counters 11 and 12 for timing purposes, as above described. The shift pulse control logic 31, on this ranging cycle, immediately supplies transfer pulses from high frequency clock 8 to both register sections 20* (FIG. 2H) and 22 (FIG. 21). The stored sequence of the digital counterpart of the previous video sequence is then converted to a suitable analog signal by digital to analog converter and applied through video amplifier 36 to display system 37. As noted above, display 37 preferably comprises a single gun cathode ray tube which operates under suitable sweep circuitry, to be described below. Depending on the presentation desired, the video sequence supplied from converter 35 may be used for beam deflection or beam current modulation. In the specific system of FIG. 1, beam intensity modulation has been illustrated. The readout rate in the specific system, as shown in FIG. 2, is four times as fast as the real time rate at which the video signal was stored.
As readout is initiated, decoder 10 supplies a trigger signal in synchronism with t at A. FIG. 2, to the radar presentation sweep generator 40, whose output appears at K, FIG. 2. The radar sweep generator output is applied as a deflection signal for the cathode ray tube display 37 to cause presentation of the radar signal along the desired time base locus. Assuming that three predominant targets appear in the video sequence between the time t' and 1' at M, FIG. 2, these would be presented as shown at FIG. 3, at a, b, and c. At t' the video input to display 37 from converter 35 terminates. Simultaneously therewith, decoder 10 supplies a trigger signal to the indicia position generator 41 whose output is also supplied as a deflection control to display 37. For the purpose of this description, the indicia position generator will be considered to generate a sweep as shown at FIG. 2L, although this generator would preferably be a random position generator under the control of inputs from a computer or other indicia store. As shown at L, FIG. 2, this sweep output has the same amplitude as the radar display sweep K, but may be of a different time period. Consequently, the indicia sweep display period affords time for the operation of quite complex symbology generator operation, should that be desired, as might be necessary for PPI presentation systems. Relatively simple indicia generation is illustrated, however, for the purposes of conciseness, in the system of FIG. 2.
For the latter purpose, the progressively increasing output voltage L of FIG. 2 is simultaneously applied to three level selectors 42, 43, and 44, provided with manual controls 46, 47, and 48. Each is therefore operative to develop an output trigger signal when voltage L attains a selected value, which may be at any time in its entire range. The level selector outputs are individually applied to the respective indicia generators 50, 51, and 52. In the illustrated system, these generators are shown as supplying a single, a double, and a triple pulse output at M, FIG. 2. Their outputs are applied to the cathode ray tube display system 37 for deflection modulation of the cathode ray beam orthogonally to the time base deflection effected by the sweep generators. FIG. 3 shows the composite display of the video signal and the related symbology, wherein the level selector controls 46-48 have been set to apply the selective symbology indications to the right of each of the respective targets a, b, and c. On relaxation of indicia sweep generator 41, as shown at L, FIG. 2, the display system remains quiescent until the next operation of the radar trigger generator.
As will be understood, during the presentation of the video sequence and the symbol display just described, the system was storing the digitalized video sequence as received in register sections 21 and 22. This was effected under operation of low frequency clock signals as applied to control gates 23, and the gate control logic signal applied thereto from 30 to direct the sampled converted video sequence to input register section 21, also being clocked for transfer at the low frequency clock rate via shift pulse control logic 31 (FIG. 21E). At the end of the radar display sweep (FIG. 2K), gate control logic 30 shifts selector gates 24 to feed the stored digital sequence from register section 21 to register section 22, which was emptied of its stored signals during the last display sweep under control of the high frequency clock transfer signal from shift pulse control logic 31. Logic 31 thereupon initiated supply of low frequency clock transfer signals from clock 7 to register section 22 (FIG. 2F). Consequently, the counterpart digital storage of the video sequence received on the succeeding ranging period (n+1) progressed uniformly from register section 21 to section 22 for the complete ranging period during which display of the preceding video sequence, and the desired symbology, was simultaneously displayed. Therefore, at the end of the ranging period, the system becomes temporarily quiescent with the digital counterpart of the video sequence stored in register sections 21 and 22 pending the next radar transmission under control of trigger generator 5.
For the purposes of explanation, the operation of the video and symbology display components was not de scribed in connection with the first period (n) shown in FIG. 2. It is now apparent, however, that during the readout period, the high frequency clock was applying transfer pulses via the shift pulse control logic 31 to register sections 21 and 22 during the first part of this period (:FIG. 2I, I), while the cathode ray display 37 successively received the radar signal synchronized with the radar sweep (FIG. 2K), and immediately thereafter the output of the indicia sweep generator (FIG. 2L), and the outputs of the indicia symbology generators 50-52. In the recurrent operation of the overall system, the system effects visually continuous, correlated display of video and indicia information.
The display system of FIG. 4, while analogous in many respects to that of FIG. 1, differs from the latter in that it is continuously operative to store and display cyclic input information signals in conjunction with identifying indicia. Thus, it is essentally asynchronous with respect to the input signal and can accommodate input signals over a wide range of recurrence rates. This system automatically responds to a reference phase datum sensed with regard to the cyclic information signal input to produce a coherent cycle to cycle information signal display.
The system of FIG. 4 includes numerous components whose counterparts appear in the system of FIG. 1, and in these instances has been added to the reference numeral used in FIG. 3. In other instances, while related component structure is frequently contemplated, individual differences may exist. In these cases, dilferent numerals reflect this relation.
As in the case of FIG. 1, the exemplary information signal source is again taken as a radar system including receiver 102, transmitter 101, and the associated trigger circuit 105. Trigger 105 supplies the display system reference phase data with regard to the cyclic information signal supplied by the radar receiver 102.
The output signal from the receiver is continuously fed to the display system, which continually stores a digital version of this information signal, including, for a radar source, the output of radar receiver 102 during the dead radar time intervals. With other information input signals, obviously the information input would be similarly converted to digital form and stored in the continuous manner to be described. Similarly, phase reference data would be derived from the signal characteristics from different sources than radar in a conventional manner to supply phase data equivalent to that derived from trigger generator 105.
The system of FIG. 4 is basically characterized as continuously operating under control of free running clocks 156 and 157, whose output signals are utilized analogously to those of the control clocks 7 and 8 of FIG. 1. As above discussed, the low frequency clock output establishes the rate at which the input information signal is sampled, fed to the storage registers, and transferred therein. The high frequency clock, continuously running at a multiple rate and synchronized phase with respect to the low frequency clock, determines the readout rate for the counters, as described above. Synchronization is obtained by decoder 181 which includes the necessary circuitry to function as the master control for the system. Thus, decoder 181 also supplies correlated control signals to logic circuits 161 and 162.
The system of FIG. 4 employs a different arrangement of parallel shift registers for time compressed readout operation. For this purpose, two parallel shift register sections 158 and 159 are employed for information storage. Section 158 provides the predominant storage capacity, and section 159 a fraction thereof. Thus, in a four to one time compression system, register section 159 would provide x bits storage, while register section 158 would provide 4x bits. The ratio of storage capacities of the sections correspond to the frequency ratio of the low and high frequency clocks.
This register configuration can be used with the system of FIG. 1, and vice versa.
In the operation of the information signal conversion and storage, the low frequency clock signal quantizes the same in the manner described above by the detector and hold circuit 114, feeding the analog digital converter 115, from which the binary signal is applied to control gates 160. The control gates are programmed to the gate control logic network 161 and clock 156 to feed the signal alternately to register sections 158 and 159. The shift pulse control logic network 162 operates during information signal storage responsively to the output of low frequency clock 156, to advance the binary information in the registers. Under operation of the gate control 160, the binary counterpart of the information signal is first introduced to register section 158 of the predominant storage capacity. As this register section reaches its capacity limit, control gate 160 shifts the binary input to register section 159, and simultaneously therewith the shift pulse control logic 162 reads out the information signal segment rapidly from register section 158 through selector gate 163 to the digital to analog converter 122, whence it is amplified at 136 and applied to the cathode ray display indicator 137 in the manner above described.
As the binary information read out is completed from register section 158, register section 159 is just filled and at this point the shift pulse control logic 162 and the gate control logic 161 causes a rapid readout of register section 159 through selector gates 163 for continuing the display.
At the same time, control gate 160 is shifted by control gate logic 161 to feed the converted information signal to register section 158, for its next cycle of operation. In this manner, signals received from an information source, such as radar receiver 102, are continuously converted to binary counterpart form and stored in register sections 158 and 159. Readout of the register sections is at a rapid rate which is a multiple of the rate of storage. The time periods intervening between successive readouts are available for indicia display. As noted above, moreover, the rate at which the information storage shift registers are programmed is independent of the rate of recurrence of the information signal.
The continuous sequence of operation of register sections 158 and 159 are shown in FIG. 5. At 5A, the storage periods during which register section 158 is receiving information is shown. In line B, readout periods for register section 158 are shown, which are coextensive with the storage periods of register section 159 shown at C. Readout periods for section 159 are shown at D.
Information is accordingly applied to the cathode ray display means 137 during the interval shown at 5E. It should be noted that the successive time segments of the information signal supplied from radar receiver 102 represented in the time sectors at SE is entirely arbitrarily related to the recurrence rate of the radar information signal source. In other words, the information contained in any single time sector shown at 5E may consist of a fraction of one radar ranging signal cycle, and may include a portion of the radar dead time.
Responsive to the phase reference information, supplied by trigger circuit 105, with respect to the cyclic information signal, the display system of the present embodiment generates sweep voltages for display 137 to position the information in that display cycle at the correct position on the indicator. The manner in which the display sweep generator is programmed will now be described.
Infonmation display sweep generation in the system of FIG. 4 employs a pair of shift registers 168 and 169 which are analogous to registers 158 and 159 and respective storage capacities, but preferably of single digit configuration. These registers continually store information for utilization by the information display sweep generated circuitry which is read out simultaneously with information display as shown at FIG. 5E. For this purpose, the shift pulse control logic network 162 applies a similar sequence of shift pulses to register sections 168 and 169 as was discussed in connection with the information storage register sections. The input signals for register sections 168 and 169 are similarly programmed by control gates 170 by gate control logic network 161 to operate in a manner analogous with that of control gates 160. Similarly, gate control logic network 161 programs selector gates 171 to deliver a continuous output signal sequence during the sequential readout operations of register section 168 followed by register section 169. The information display sweep generator control channel includes a sweep timing and bit insertion generator 175. This generator operates to generate zero or one binary output signals at the basic frequency determined by low frequency clock 156. Normally, it supplies a series of zeros which are stored through control gates 170 in shifted register sections 168 and 169. Responsive to input phase information, obtained in the system of FIG. 4 from trigger generator 105, the bit insertion generator is programmed to supply a consecutive series of ones for a selected ranging period determined by its included sweep timing means. Thus, when a cycle of the information signal data is initiated from the output of radar receiver 102 for storage as a digital counterpart in register sections 15 8 and 159, simultaneously the sweep generating and insertion gen= erator 175 initiates storage of ones in shift register sections 168 and 169. Since the series of ones from the bit insertion generator is applied to the input of register sections 168 and 169 beginning in synchronized relation with radar signal whose storage is then initiated in register section 158 and continued in section 159, the readout time relationships are also in the desired synchronism.
Selector gates 171 apply the readout signals from register sections 168 and 169 to detector 178. So long as zeros are supplied from the shift registers, detector 178 remains quiescent. When the ones signal appear, detector, 178 applies these quantized signals to the display sweep generator 179, which successively integrates the series of signals to provide a sweep voltage for displaying the information signal on indicator 137. The operation of the information display sweep generator 179 is therefore initiated at whatever point it may be required in any information display time sector shown at B, and continues to the end of that sector. Sweep generator 179 then retains the terminal sweep voltage lgenerated until information display is again available in the next successive interval shown at FIG. 513. During the intervening time segments available for indicia display, however, the output of sweep generator 179 is effectively disconnected from the display indicator 137 by decoupling network 180.
Under operation of the sweep timing component of the bit insertion generator 175, the resultant number of ones in sequence is applied to geneator 179 during an arbitrary number of information display sectors shown in FIG. 5B, depending on the design of the equipment. The sweep timer of 175 is preferably adjustable to ac commodate a variety of information signal conditions. At the end of the ones sequence, detector 178 senses the termination of the one outputs and the transition to zero outputs, and discharges the integrator of sweep generator 179 for resumption of operation at the initiation of the next successive series of ones which starts the next information display sweep voltage generation.
Application of indicia to display 137 is effected in the system of FIG. 4 analogously to the method of the previous embodiment. For this purpose, sweep generator 141 of FIG. 4 feeds a plurality of level detectors, selectively activating indicia generators for display at the indicator. During operation of indicia generator network 141, decoupler network 180 effectively decouples the output of information display sweep generator 179 from display 137. The information channel may be blanked by selectors gates 163, while the indicator is operated responsively to the necessary voltages from the indicia display channel.
The operation of indicia display generator 141 occurs in the sequential time segments shown at FIIG. SF. The sweep generator 141 is triggered into operation by decoder 181.
As mentioned in conjunction with the previous embodiment, the indicia sweep generator is used in this description in the interests of clarity and simplicity and in actual practice this device might well be replaced by an indicia position generator controlled by a computer or indicia store.
The correlated outputs in time sequence of information display sweep generator 179 and indicia sweep generator 141 are shown at FIG. 56. In the first readout period, information display sweep generation has begun at an intermediate point and proceeds to an arbitrary level. At the termination of this readout period, the sweep voltage is eflectively decouped from the display 137, and indicia generator sweep 141 initiates operation from a zero level under control of decoder 181. Its output voltage proceeds to increase linearly to a predetermined value during the indicia display period, which corresponds to the maximum level attainable by information display sweep generator 179 under control of the sweep timing generator of 175.
At the beginning of the next information display period, blanking network 180 reapplies the arbitrary voltage attained by sweep generator 179 at the end of the preceding information display period, which voltage then linearly increases as the consecutive series of ones signals is continued in readout from register sections 168 and 169. Generator 179 then holds the second level it has attained during the next indicia display operation of generator 141. The third information display period, as shown in FIG 5G, for example, may include termination of the display sweep. At this point, detector 178 discharges the integration means to sweep generator 179 pending initiation of a new display sweep. After an effective radar dead time, the subsequent information display sweep initiates in the same information display time sector. Thus, the system of FIG. 4 is especially adapted to display adjustably positionable indicia in conjunction with any cyclic video information signal having a recurrence period equal to or greater than the sweep timing period established by bit insertion generator 17 5 Since the sweep timing periods are easily adjustable, as are the effective sweep amplitudes of the sweep generators, it is obvious that the asynchronous system of FIG. 4 is highly adaptable to the coherent indication of a wide variety of signals, or of signals of changing frequency. Specifically, it is of great utility in connection with radars of different pulse repetition rate, variable radar ranges, or variable dead times.
While it will be understood that the systems shown in FIGS. 1 and 4 represent exemplary embodiments of the invention, it will be understood that both the apparatus thereof and the described method are subject to manifold variations within the scope of the inventive concept. For example, while the embodiments set forth at length hereinabove consider only systems wherein readout is performed at some higher rate than the read-in, it is obvious that the system could perform well where the readout takes place at some lower rate than the read-in. In other words, the readout may be at any multiple, either higher or lower, than the read--in. Consequently, the bounds of the invention are to be determined with reference to the scope of the appended claims.
1. A display system for presenting sensor information in conjunction with related indicia comprising:
means for receiving the output of a sensor, and for converting the received sensor data from analog form to plural digit binary form;
storage means fed by receiving and converting means operative to store the sensor data in the plural digit binary form at the rate of reception;
means for periodically reading the stored information out of the storage means at a rate which is a multiple of the rate of reception;
means operative to convert the plural digit binary data readout into analog form;
presentation means for displaying such analog data during a fraction of the length of time originally used to receive the data; and
indicia means operative with the presentation means during at least a portion of the remaining fraction of time originally used to receive the data, to indicate related indicia in conjunction with the data display.
2. The system of claim 1 wherein the presentation means comprises a single gun cathode ray tube operatively connected with the indicia means, and the system further comprises a radar sensor.
3. The system of claim 1 wherein the storage means comprises a pair of input shift register sections and a single output shift register section selectively connecable therewith.
4. The system of claim 3 further including clocking means for applying high frequency transfer pulses to one input register section and low frequency transfer pulses to the other input register section during the said fraction of the data receiving period.
5. The system of claim 4 wherein the clocking means further comprises means operative to apply high frequency transfer pulses to the output register section during the said fraction of the data receiving period and to apply 11 low frequency transfer pulses thereto to operate the same in the remainder of the data receiving period.
6. The system of claim 5 wherein the indicia means comprises means for generating a plurality of distinctive indicia at selected locations relative to the video display.
7. The system of claim 1 wherein the storage means comprises a pair of shift register sections selectively connectable with the receiving and converting means.
8. The system of claim 7 further including clocking means for applying high frequency transfer pulses to one register section and low frequency transfer pulses to the other register section during the said fraction of the data receiving period.
9. The system of claim 1 further including indicia sweep generation means comprising a pair of shift register sections.
10. The system of claim 9 further including clocking means for applying high frequency transfer pulses to one register section and low frequency clocking pulses to the other register section during said fraction of the data receiving period.
11. The system of claim 10 wherein the indicia sweep generation means further comprises phase detection means responsive to cyclic data from the sensor.
12. The method of presenting cyclic information in conjunction with related indicia comprising:
receiving a cyclic information signal,
converting the information signal to plural digit binary data as it is received,
storing the binary data at the rate of reception,
converting and displaying the stored binary data as an analog signal during a display period which is a fraction of the period of its reception,
indicating in conjunction with the information display, during a period not exceeding in duration the remaining portion of the period of reception, related indicia, and
sequentially repeating the recited steps to effect visually continuous correlated display of information and indicia.
References Cited UNITED STATES PATENTS 3,119,992 1/1964 Fluegel 235-454 X 3,404,309 10/1968 Massell et a1. 3l5--18 3,422,435 1/ 1969 Cragon et al.
RODNEY D. BENNETT, Primary Examiner M. F. HUBLER, Assistant Examiner US. Cl. X.R.