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Publication numberUS3557796 A
Publication typeGrant
Publication dateJan 26, 1971
Filing dateMar 10, 1969
Priority dateMar 10, 1969
Also published asDE2006076A1, DE2006076C2
Publication numberUS 3557796 A, US 3557796A, US-A-3557796, US3557796 A, US3557796A
InventorsDavies Gomer L, Keller John W Jr, Terry Reese S Jr
Original AssigneeCordis Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Digital counter driven pacer
US 3557796 A
Images(3)
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Description  (OCR text may contain errors)

United States Patent 1 1 3,557,796

{72] lmcntors John W. Keller,.lr.; [56] References Cited Reese S. Terry, Jr., Miami; Gomer L. UNITED STATES PATENTS 3,156,235 11/1964 Jaeger l28/2.O5 31 A No. 805,714 3,384,075 5/1968 Mitchell 128/206 ml 10,1969 3,460,542 8/1969 Gemmer 128/421 [45] Patented Jan. 26, I971 [73] Assignee Cordis Corporation Primary Examiner-William E Kamm Miami, Fla. Attorney-Kenway, Jenney and Hildreth a corporation of Florida ABSTRACT: The cardiac pacer disclosed herein employs a digital counter driven by a relatively high frequency oscillator to time intervals which simulate various cardiac functions. When allowed to c cle re titivel the counter rovides a [54] DIGITAL COUNTER QRWEN PACER relatively slow, fixed rate i n ode ot operation. Ho vever, the 12 Claims 3 Drawmg counter may be reset under certain conditions by ventricular [52) US. Cl 1, 128/419 signals to provide a demand mode of operation and by atrial [51] Int. Cl 1 v A6ln 1/36 signals under certain other conditions to provide a so-called [50] Field of Search 1 v v 1 A l l .l 128/205, synchronized mode of operation. Noise rejection circuitry is 2.06, 4 1 9424, 4 l 9P( Digest) also disclosed.

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vSHEET 3 0F 3 3 CLOCK NINE STAGE OSCILLATOR B'NARY ICQUNTER R (:7 ca 0909 IL A r J b D R Q u R Q I 5 FF '6 r w 6 5 R oll l? INVENTORS DAVIES GOMER L ATTORNEYS DIGITAL COUNTER DRIVEN PACER BACKGROUND OF THE INVENTION This invention relates to cardiac pacers and more particularly to such a pacer employing digital circuitry.

in the normal heart, electrical signals are generated and appear in the atrium at a rate of approximately 60 to 120 times per minute, depending on such factors as body size and amount of physical exertion. Approximately O.l second after such a signal has appeared in the atrium, it is transferred to the ventricle of the heart, which reacts to the stimulation by contracting. This contraction forces blood from the ventricle into the arterial system and thence to the entire body. The delay between the appearance of an electrical signal in the atrium and its appearance in the ventricle is called the A-V delay. Following the contraction of the ventricle, there is an insensitive period lasting about 0.4 second, during which time the heart is unresponsive to electrical pulses. This time is referred to as the refractory delay period.

A common type of heart failure is irregularity in the generation of atrial potentials. In some cases, these potentials appear at only a low rate; in others, they cease entirely for extended periods though at other times the signals may be generated with perfect regularity. It is in persons suffering from this kind of cardiac disorder that a standby or so-called demand mode pacer is used. This device is designed to apply stimulating pulses to the ventricle, by means of an electrode implanted therein, only when the heart fails to generate pulses spontaneously. When natural pulses regularly appear, the pacer provides no stimulation; when they appear irregularly, the pacer adjusts its timing to integrate its artificial pulses with the natural ones. This type of pacer is often provided with circuitry which simulates the refractory delay period of the heart. The reason for including such delay circuitry is that a spontaneous electrical signal which appears a short time after delivery of an artificial pulse is ineffective to pump blood, either because the natural refractory period of the heart caused the heart to ignore the spontaneous pulse or because the ventricle has not had time following the previous beat to be refilled with blood. A simulated refractory period causes the pacer likewise to ignore these ineffective beats. The device's timing continues just as if the beats had never occurred.

Another form of heart disease is the so-call ed A-V block in which the patients heart undergoes normal or near-normal atrial contraction but the atrial signal is not transferred to the ventricle. With such a patient, it is desirable to use a so-called synchronous pacer which detects atrial signals and supplies to the ventricle a stimulating pulse about 0.1 second later, a period which constitutes a simulated A-V delay. In the absence of detected atrial signals, the pacer supplies ventricular pulses at a fixed rate. The synchronous pacer, like the demand pacer, is often provided with refractory delay simulation.

A drawback of pacers presently in use is their relatively large size. While this does not affect the ease of installation in any but the rarest patients, it is easier to hermetically seal the pacer package if it is of smaller volume. Such sealing is desirable because it eliminates the possibility that body fluids will seep into the device and damage it. Such hermetic sealing employing metallic members can also be employed to shield the pacer from electromagnetic interference.

Another problem presented by currently-used pacers is their finite battery life. Recent improvements have extended battery life to the neighborhood of 2 years, but increasing this time still constitutes an important improvement by reducing the frequency of battery replacements which require surgery.

Among the several objects of the present invention may be noted the provision of a cardiac pacer which is highly reliable and stable; which provides very accurate timing; which is protected from dangerous operation caused by ambient electrical noise; which has very low power consumption and thus yields long battery life; which is relatively compact; which will operate in a demand mode providing either an inhibit demand or synchronous demand operation; which will operate in a straight synchronous mode; which can provide a fixed rate operation; and which is relatively inexpensive. Other objects and features will be in part apparent and in part pointed out hereinafter.

SUMMARY OF THE INVENTION Briefly, a cardiac pacer according to the present invention times various events and delays by means of a digital counter which is driven by an oscillator operating at a frequency which is a relatively large multiple of a normal heartbeat rate. A cardiac stimulating pulse is generated at a predetermined point in the count. Thus, if the counter cycles repetitively, the heart is stimulated at a predetermined fixed rate. To provide demand mode operation, the counter is reset in response to spontaneous cardiac signals thereby to prevent stimulation when the heart is functioning normally. To provide synchronous mode operation, the counter is reset to a point preceding the stimulation count by an amount which simulates a normal A-V delay. a

The use of digital count down circuitry permits both the various delays and the durations of the stimulating pulses to be accurately timed. Further, by counting down from a relatively high frequency, an oscillator having a relatively short duty cycle may be used so as to reduce battery drain. Further, the use of a relatively short oscillator period permits timing components, e.g. capacitors, of relatively small size to be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block logic diagram of a cardiac pacer of this invention;

FIG. 2 is a block logic diagram of another embodiment of the pacer incorporating noise detection circuitry; and

FIG. 3 is a block logic diagram of still another embodiment.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, the apparatus illustrated there is adapted for use as either a demand or synchronous mode cardiac pacer, separate output terminals, 6 and 9 respectively, being provided for the two modes. Depending on the mode of operation desired, an electrode which is implanted in a location suitable for stimulating ventricular contraction is connected to one or the other of these output terminals. A single input terminal, designated 10, is employed for both modes, the electrode connected to this input terminal being placed in contact with the ventrical for demand mode operation and in contact with the atrium for synchronous mode operation. In demand mode operation, the terminals 6 and 10 may in fact both be connected to the same lead.

Timing of the different events occurring in the operation of this apparatus is provided by a digital counter 3. The counter is driven by an oscillator 1 which establishes the time base. As illustrated, counter 3 comprises a nine stage binary divider and the oscillator 1 runs at a frequency which is relatively high with respect to the contemplated range of heartbeat rates or frequencies. Since the counter 3 requires only a very short triggering pulse, the duty cycle of oscillator l is preferably relatively short to reduce battery drain.

As is conventional, counter 3 provides a two-state output signal for each stage of binary division, these signals being designated C1-C9. The counter also provides signals which are the binary complements of these signals, these complementary signals being designated a e? In the er ri; bodiments illustrated herein, only the C1, C7, C8, C9 and C9 signals are utilized and thus only these signals are designated on the drawings but, as will be apparent to those skilled in the digital circuitry arts, other combinations of output signals may be used if different event timings are desired. Positive logic is assumed.

As is also conventional, the counter 3 run cyclically, that is, the states of the binary output signals pass through a sequence which repeats after all the possible combinations have been utilized. With the nine stage binary counter illustrated, the number of possible states is 2 r 512. Further, the counter may at will be reset to a predetermined starting point by the application of a reset signal to a reset terminal, designated R. The starting point of the counter is considered herein to be the zero count and the various possible states or counts are con' sidered to be zero through 51 l. At zero count, the output signals C1C9 are low and the output signals GT-m are positive r high.

The C9 output signal from the counter 3 is applied to the clock input terminal, designated C, of a so-called DType flipflop 16 and the C1 signal is applied to the reset terminal R of this flip-flop. D-type flip-flops are available commercially in integrated circuit form from several manufacturers and their operation is generally as follows. The device responds to a positive-going voltage transition on the clock input terminal, designated C, by making the logic level output on an output terminal, designated Q, identical to the logic level present at an input terminal designated D, at the time of the positivegoing transition at the C terminal. Thereafter the Q output signal remains the same, ignoring changes in the D input 'signal, until another positive-going transition is applied at the clock input C. The device may also be reset by the application .of a high or positive signal to a reset terminal designated R.

The reset function overrides all others; as long as a high level is present at the R terminal, the output signal at Q is low re gardless of changes at the D or C terminals. A signal which is the binary complement of the signal present at terminal Q is provided at a terminal designated Cardiac signals applied to the input terminal 10 are amplified and shaped by means of an amplifier 11 so as to be squared into waveforms suitable for use with digital circuitry, as is understood by those skilled in the art. The square signals thereby obtained are applied to the clock terminal C of a second D-type flip-flop 17. The C9 signal is applied to the D input of this flipflop and the output signal from the oscillator 1 is applied to the reset terminal R. The Q output signal from flip-flop 11 is applied to the reset terminal R of the counter 3 while the Q output signal from this flip-flop is applied to the D input terminal of the first flip-flop 16.

The Q output signal from the flip-flop 16 is applied to the input terminal of an amplifier 21 which responds to a positive input signal by applying to the output terminal 6 a voltage level which is suitable for cardiac stimulation.

The portions of the apparatus thus far described are those employed in providing operation in the demand mode and that operation is substantially as follows. Assuming initially that no cardiac signals are applied to the input terminal-10 and that flipflop 17 is in its reset condition so that the respective 6 output signal is high, the counter 3 will run indefinitely in its cyclic mode. Thus, when the count changes from 51 1 tot), the C 9 output signal will experienceapositive-going transition and the positive output signal present at the D input terminal of flip-flop 16 will be transferred to its Q output terminal. On the next count, however, the flip-flop 16 will be reset by the C1 signal as the C1 signal goes positive on count 1. It can thus. be seen that, with no detected cardiac signals, the pacer will generate a stimulating pulse having a duration of one oscillator cycle for every 512 oscillator cycles. Assuming that the oscillator l operates at 590 c.p.s., the apparatus will thus deliver 1.7 millisecond pulses at the rate of approximately 70 pulses per minute which is an appropriate timing for nonsynchronous or demand mode cardiac stimulation.

During the counting from zero to the intermediate count of 255, the C9 output signal is low and thus, even if cardiac signals are received, the flip-flop 17 will not change state. This insensitive period simulates the refractory delay of the heart and prevents any'intcraction between the output and input circuits of the pacer. From count 256 through count 511, however, the C9 signal is high and thus a cardiac signal received during this latter interval will cause the flip-flop 17 to change states and the resulting high signal applied tothe terminal R of the counter 3 will cause the counter to be reset to its zero count. Simultaneously with the resetting of the counter 3, the Q signal from flip-flop 17 goes low so that, even though the resetting of the counter produces a positive-going transition in the C9 signal, no change of state is produced in the flip-flop 16 and thus no output signal is generated. On the next count after the resetting of counter 3, the flip-flop 17 is reset by the oscillator output signal. Received cardiac signals are typically of sufiicient duration to span more than one cycle of the oscillator so that the flip-flop 17 will change state at least once even if the cardiac signal is initiated during a period when the oscillator output signal is high.

From the foregoing, it can be seen that, if the patient's heart is beating normally at a rate which is more than the free running rate of the pacer, i.e. about 70 beats per minute, and not more than twice that rate, i.e. about beats per minute, the counter 3 will be reset to its zero count by each natural heartbeat before a count of 5] l is reached. Thus, the patients heart will not be stimulated at all if it is beating spontaneously within this 2-to-l range of rates. However, if no spontaneous heartbeat is detected between count 256 and count 5l 1, the I pacer will then stimulate the patients heart at the end of the full count period, that is, after a period which corresponds to the 70 pulse per second free running rate. In other words, the difference between the starting point count and the end of the counting sequence establishes a maximum interval between heartbeats. Accordingly, if the spontaneous heart signals disappear intermittently, the pacer will integrate its operation with the normal heartbeat.

The generation of a synchronous pacing signal is controlled by means including a third D-type flip-flop 18. The C8 and C9 signals are combined in a NOR gatel27 to provide a signal which is high from count 0 throughcount 127. The resultant signal is applied to the D input terminal of flip-flop 18. The C7 signal is applied to the clock input terminal C of this flip-flop and the C1 signal is applied to its reset terminal R. The output signal provided at the Q terminal of flip-flop 18 is amplified by an amplifier 33 to provide at output terminal 9 a signal level suitable for cardiac stimulation.

The C7 signal experiences a positive-going transition at counts 64, 192, 320 and 448 but only the transition at count 64 can produce a change in state of the flip-flop 18 since the D input is low at the other three transition points. Accordingly, it can be seen that flip-flop 18 will be put into its so-called set state each time the counter 3 reaches a count of 64. Further, the flip-flop 18 will be reset on the next count, i.e. count 65, by the C1 signal. Thus, each time the counter reaches a count of 64, a cardiac stimulating pulse having a duration of one oscillator cycle will be provided at the output terminal 9.

When the apparatus illustrated in FIG. 1 is to be utilized in the synchronous mode, the input terminal 10 is connected to an electrode which is implanted so as to detect atrial signals.

The resetting of counter 3 is controlled in response to detected signals as described previously. Thus, the counter is reset toits zero count if an atrial signal is detected from count 256 through count 511. A stimulating pulse is then generated at output terminal 9 when count 64 is reached. The, delay provided by the interval between the resetting and the 64 count is about 108 milliseconds whichsatisfactorily simulates the normal A-V delay. Thus the heart is stimulated with timing appropriate for synchronous pacer operation.

From the time thatthe counter 3 is reset until count 256 is reached, the input circuit is insensitive to detected cardiac signals just as it was in .the demand mode of operation described previously. Thus, the interval from count 64 to count 256 provides a simulated refractory period during which the apparatus will not respond to input signals. Accordingly, interaction between the input and output circuits is prevented, as is the overly rapid stimulation of the heart due to premature detected signals.

If no atrial signals at all are detected, the counter 3 will run cyclically as described previously and stimulating pulses will be generated at a fixed rate, one pulse being generated each time the counter 3 passes the 64 count. Accordingly, if there is failure of the heart to generate atrial signals or if the input lead should break, the generation of stimulating pulses will not fail altogether but will lapse into the relatively slow free-running rate.

As noted previously, electrical noise present in certain environments can interfere with cardiac pacer operation by introducing false input signals which improperly modify the operation of the pacer. The embodiment illustrated in FIG. 2 includes circuitry for identifying interfering electrical noise and preventing it from causing a dangerous mode of operation. The embodiment of FIG. 2 is essentially the same as the apparatus of FIG. 1 except for the addition of those components which condition the effect of input signals. The amplitier 1] also drives a counter 35 which, as illustrated, comprises a two stage binary divider. Counter 35 provides, at an output terminal designated Q35, a signal which has a positive-going transition after four input signals have been counted. The signal from gate 27 is applied to a reset terminal R on counter 35 for resetting counter 35.to its zero count during counts 0 through 128 of counter 3.

The output signal from counter 35 is applied to the clock input terminal C of a fourth D-Type flip-flop 38. A Logic High Signal is applied to the D input terminal of flipflop 38 and the Q output signal from flip-flop 16 is applied to the reset ter minal R of flip-flop 3 The Q output signal from flip-flop 38 is combined with the Q 9 signal from counter 3 in a NOR gate 44 and the resultant signal is applied to the D input terminal of the flip-flop 17 in place of the straight C9 signal which was employed in the embodiment of FIG. 1.

Assuming that the flip-flop 38 is in its reset condition and that the counter 3 has just reached a count of 128 so that the counter 35 has just been reset and the signal applied to the D input of flip-flop 38 is high, the operation of this noise detection circuitry is as follows. Detected input signals advance the counter 35. If more than four input signals are received before the counter 3 reaches a count of 256, the flipflop 38 will be caused to change states, that is, to be put int-.5 its so-called set condition. In this set condition, the flip-flop 38 applies a high signal to the NOR gate 44. Thus, the NOR gate will provide a low sign al to the D input of flip-flop 17 regardless of the state of the 9gsignal. Accordingly, detected input signals which are passed by the amplifier 11 to the clock input C of flip-flop 17 cannot cause that flip-flop to change states and thereby reset counter 3 as described previously. If the counter 3 is not reset, the apparatus then provides stimulating pulses at the relatively slow free running rate in the same manner as if no input signals were received. If fewer than four input signals are received between the count of 128 and the count of 256, the flip-flop 38 does not change states and the flip-flop 17 becomes responsive to input signals received after counter 3 reaches a count of 256 as described previously.

In summary, it can be seen that this noise detection circuitry operates by counting received signals for a predetermined period which precedes the normal sensitive period and by providing a fixed rate or free-running mode of operation if more than a predetermined number of input signals are detected during this period. In other words, the detection of input signals at a relatively high repetition rate is taken as an indication that interfering electrical noise is present and the pacer then ignores all detected signals for the remainder of the fixed rate cycle. While genuine cardiac signals may be ignored as a result of this mode of operation, the reversion to fixed rate operation is deemed preferable to the random rate of stimulation which might otherwise occur in the case of synchronous mode operation or the complete cessation of stimulation which might otherwise occur in the case of demand mode operation. This noise detection circuitry thus provides an advantageous protective feature in either mode of operation.

The standby demand mode operation provided by the circuits of FIGS. 1 and 2 is of the so-called inhibit type, that is, no output pulses are produced if normal heart signals are detected. The embodiment illustrated in FIG. 3, which is basically similar to the FIG. 1 embodiment, is arranged to provide so-called synchronous demand operation. A NAND g a t e 45 combines the Q output signal from flip-flop 16 with the goutput signal from the reset flip-flop 17. The NAND gate then drives the output amplifier 21.

The NAND gate 45 reinverts the inverted or complemented output signal from flip-flop 16 so that, when no input signal is received, this circuit operates as the FIG. I circuit to provide stimulation at a fixed rate. When a ventrical signal is detected, causing the counter 3 to be reset as befgre, an output pulse is also generated immediately due to the signal from flip-flop 17. However, since the ventrical is already starting to contract, the stimulus from the pacer is effectively disregarded. This type of operation avoids the possible conflicts of rhythm that may be present with a fixed-rate pacer, for example, when A-V mode conduction is restored. If desired, switching means can be incorporated to permit both inhibit demand and synchronous demand modes.

A form of synchronous demand operation can also be provided using the circuit of FIG. 1 without change by connecting the output terminal 9 to the input terminal 10 and to a ventrical lead. With this arrangement a pulse is generated a short interval after a normal ventricle signal is detected but this pulse is again ineffective since it occurs within the refractory period. If no input pulses are detected the apparatus lapses into a fixed rate mode of operation as in the other arrangements discussed.

It should be understood that certain variations on the preferred embodiments of these pacers are within the spirit of the invention. The binary dividers, for example, could be replaced by other binary logic devices such as ring counters, shift registers, or the like. Similarly, the NOR gates could be replaced by other gates. If desired, the stimulating pulse duration could be determined by a one-shot multivibrator. These changes could be made with only relatively minor alterations in the circuitry as well as changes in the logic.

An advantage of the use of digital circuitry for providing the various timing functions is that the various components, e.g., the counters, gates and flip-flops, can be constructed in integrated circuit form using presently available devices. Further, by custom designing the integrated circuitry using presently available fabrication techiques, the entire pacer can be constructed on a single semiconductor substrate thereby further reducing size, eliminating hand-wired circuit interconnections and facilitating hermetic sealing. Further, such integrated circuits have relatively low power consumptions.

In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained.

As various changes could be made in the above constructions without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

We claim:

1. Cardiac pacer apparatus comprising: an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heart beat rate; a cyclically operating digital counter means for counting the pulsations of said pulsating signal; and means controlled by said counter for generating a cardiac stimulating potential when said counter reaches a predetermined count.

2. Apparatus as set forth inclaim 1 wherein said means for generating said cardiac stimulating potential includes means for initiating the generation of said potential at the start of one cycle of said pulsating signal and for terminating the generation of said potential at the start of the next cycle of said pulsating signal.

3. Apparatus as set forth in claim ll further comprising: means for detecting cardiac signals generated during a heartbeat; and means responsive to such detected cardiac signals for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected maximum interval between successive heartbeats whereby a stimulating potential is generated only if said preselected maximum interval elapses between heartbeats.

4. Apparatus as set forth in claim 3 including means controlled by said counter for inhibiting resetting of said counter when the count held thereby is between said starting point count and a count which is intermediate said starting point count and said predetermined count, the difference between said starting point count and the intermediate count corresponding to a preselected refractory delay period.

5. Apparatus as set forth in claim 4 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said intermediate count and said predetermined count if more than a predetermined number of detected signals are counted by said second counter during the interval between a count which is intermediate said starting point count and said intermediate count whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

6. Apparatus as set forth in claim 1 further comprising means for detecting atrial signals; and means responsive to such detected atrial signals for setting said counter to a start ing point count, which precedes said predetermined count by a number corresponding to a preselected A\/ delay whereby stimulating potentials are generated in synchronously timed relationship to said atrial signals.

7. Apparatus as set forth in claim 6 including means con trolled by said counter for inhibiting resetting of said counter when the count held thereby is between said predetermined count and a subsequent count, the difference between said predetermined count and said subsequent count corresponding to a predetermined refractory delay period.

8. Apparatus as set forth in claim 7 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said subsequent count and said starting point count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said predetermined count and said subsequent count; and said subsequent count, whereby rapidly repeated electrical noise signals reaching said detecting means are inefiective to prevent generation of a stimulating potential at said predetermined count.

9. Cardiac pacer apparatus comprising:

an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heart beat rate;

a cyclically operating digital counter means for counting the pulsations of said pulsating signal;

means for initiating the generation of a cardiac stimulating potential starting at a predetermined count and for terminating the generation of said potential at a subsequent count;

means for detecting cardiac signals generated during a heartbeat;

means for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected maximum interval between successive heartbeats in response to cardiac signals which are detected after a count which is inter mediate said starting point count and said predetermined count. the difference between said starting point count and the intermediate count corresponding to a preselected refractory delay period.

it). Apparatus as set forth in claim 9 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said intermediate count and said predetermined count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said starting point count and said intermediate count; and the first said intermediate count, whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

ll. Cardiac pacer apparatus comprising:

an oscillator providing a pulsating signal at a preselected frequency, which preselected frequency is a relatively large multiple of a normal heartbeat rate;

a cyclically operating digital counter means for counting the pulsations of said pulsating signal;

means for initiating the generation of a cardiac stimulating potential starting at a predetermined count and for terminating the generation of said potential at a subsequent count;

means for detecting atrial signals;

means for setting said counter to a starting point count which precedes said predetermined count by a number corresponding to a preselected A\/ delay in response to atrial signals which are detected after a subsequent count which is after said predetermined count by a number corresponding to a preselected refractory delay period.

12. Apparatus as set forth in claim 7 further comprising:

a second digital counter for counting signals detected by said detecting means;

means controlled by said second digital counter for inhibiting resetting of the first said counter between said subsequent count and said starting point count if more than a predetermined number of detected signals are counted by said second counter during the interval between: a count which is intermediate said predetermined count and said subsequent count; and said subsequent count, whereby rapidly repeated electrical noise signals reaching said detecting means are ineffective to prevent generation of a stimulating potential at said predetermined count.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3156235 *Oct 3, 1960Nov 10, 1964Erich JaegerHeart monitoring device
US3384075 *Oct 1, 1965May 21, 1968Nasa UsaDigital cardiotachometer system
US3460542 *Feb 2, 1967Aug 12, 1969Hellige & Co Gmbh FInstrument for electrically stimulating the activity of the heart
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3688776 *Oct 13, 1970Sep 5, 1972Devices LtdDemand cardiac pacer with fast rate for indicating interference
US3709229 *Feb 9, 1971Jan 9, 1973American Optical CorpFree-running atrial and demand ventricular pacer
US3833005 *Jul 26, 1971Sep 3, 1974Medtronic IncCompared count digitally controlled pacemaker
US3870050 *Nov 7, 1973Mar 11, 1975Greatbatch WDemand pacer
US3943938 *Feb 27, 1974Mar 16, 1976Paul WexlerAnal sphincter device and barium enema plug
US3949758 *Aug 1, 1974Apr 13, 1976Medtronic, Inc.Automatic threshold following cardiac pacer
US4010759 *Aug 29, 1975Mar 8, 1977Vitatron Medical B.V.Insulated, corrosion resistant medical electronic devices and method for producing same
US4038991 *Mar 15, 1976Aug 2, 1977Arco Medical Products CompanyCardiac pacer with rate limiting means
US4049003 *Feb 2, 1976Sep 20, 1977Arco Medical Products CompanyDigital cardiac pacer
US4049004 *Mar 3, 1976Sep 20, 1977Arco Medical Products CompanyImplantable digital cardiac pacer having externally selectible operating parameters and "one shot" digital pulse generator for use therein
US4088140 *Jun 18, 1976May 9, 1978Medtronic, Inc.Demand anti-arrhythmia pacemaker
US4095603 *Dec 17, 1976Jun 20, 1978Cordis CorporationCardiac pacer employing discrete frequency changes
US4120307 *Oct 26, 1976Oct 17, 1978Medtronic, Inc.Cardiac pacemaker
US4132233 *Jun 13, 1977Jan 2, 1979Medtronic, Inc.Digital cardiac pacer
US4170999 *Jun 19, 1978Oct 16, 1979Biotronik Mess- Und Therapiegerate Gmbh & Co.Demand pacer having reduced recovery time
US4173230 *Jun 19, 1978Nov 6, 1979Biotronik Mess- Und Therapiegerate Gmbh & Co.Noise elimination and refractory period control in demand pacers
US4222385 *Sep 7, 1978Sep 16, 1980National Research Development CorporationElectronic heart implant
US4233985 *Nov 6, 1978Nov 18, 1980Medtronic Inc.Multi-mode programmable digital cardiac pacemaker
US4250883 *Nov 6, 1978Feb 17, 1981Medtronic, Inc.Digital cardiac pacemaker with refractory, reversion and sense reset means
US4275738 *Nov 6, 1978Jun 30, 1981Medtronic, Inc.Digital cardiac pacemaker clocking means
US4284082 *Dec 12, 1979Aug 18, 1981Medtronic B.V.KerkradeVentricular synchronized atrial pacemaker and method of operation
US4304238 *Aug 2, 1979Dec 8, 1981Cardiac Pacemakers, Inc.Programmable demand pacer
US4318411 *Sep 9, 1980Mar 9, 1982Siemens AktiengesellschaftHeart pacemaker
US4363325 *Jan 19, 1981Dec 14, 1982Medtronic, Inc.Mode adaptive pacer
US4388927 *Dec 13, 1979Jun 21, 1983American Hospital Supply CorporationProgrammable digital cardiac pacer
US4393874 *Apr 26, 1982Jul 19, 1983Telectronics Pty. Ltd.Bradycardia event counting and reporting pacer
US4401119 *Feb 17, 1981Aug 30, 1983Medtronic, Inc.Prolongation of timing intervals in response to ectopic heart beats in atrial and ventricular pacemakers
US4419996 *Mar 12, 1981Dec 13, 1983Cordis CorporationCardiac pacer apparatus
US4421116 *Mar 10, 1982Dec 20, 1983Medtronic, Inc.Heart pacemaker with separate A-V intervals for atrial synchronous and atrial-ventricular sequential pacing modes
US4446533 *May 19, 1980May 1, 1984National Research Development CorporationStored program digital data processor
US4466440 *Nov 12, 1981Aug 21, 1984Telectronics Pty. Ltd.Heart pacer time-domain processing of internal physiological signals
US4561444 *Jun 11, 1984Dec 31, 1985Cordis CorporationImplantable cardiac pacer having dual frequency programming and bipolar/linipolar lead programmability
US4771780 *Jan 15, 1987Sep 20, 1988Siemens-Pacesetter, Inc.Rate-responsive pacemaker having digital motion sensor
US4958632 *Mar 5, 1980Sep 25, 1990Medtronic, Inc.Adaptable, digital computer controlled cardiac pacemaker
US5010893 *Mar 24, 1988Apr 30, 1991Siemens-Pacesetter, Inc.Motion sensor for implanted medical device
US5265601 *May 1, 1992Nov 30, 1993Medtronic, Inc.Pacemaker
US5318593 *Nov 18, 1991Jun 7, 1994Medtronic, Inc.Multi-mode adaptable implantable pacemaker
US5370668 *Jun 22, 1993Dec 6, 1994Medtronic, Inc.Fault-tolerant elective replacement indication for implantable medical device
US5387228 *Jun 22, 1993Feb 7, 1995Medtronic, Inc.Cardiac pacemaker with programmable output pulse amplitude and method
US5402070 *Jul 15, 1994Mar 28, 1995Medtronic, Inc.Fault-tolerant elective replacement indication for implantable medical device
US5861008 *Feb 9, 1998Jan 19, 1999Pacesetter AbHeart stimulating device with stimulation energy responsive to detected noise
US8321023Jan 27, 2009Nov 27, 2012Cardiac Pacemakers, Inc.Baroreflex modulation to gradually decrease blood pressure
US8442640Jan 4, 2010May 14, 2013Cardiac Pacemakers, Inc.Neural stimulation modulation based on monitored cardiovascular parameter
US8461821May 20, 2010Jun 11, 2013Seiko Epson CorporationFrequency measuring apparatus
US8473076Sep 6, 2011Jun 25, 2013Cardiac Pacemakers, Inc.Lead for stimulating the baroreceptors in the pulmonary artery
US8508213May 18, 2010Aug 13, 2013Seiko Epson CorporationFrequency measurement device
US8571655 *Jan 26, 2010Oct 29, 2013Cardiac Pacemakers, Inc.Multi-site ventricular pacing therapy with parasympathetic stimulation
US8593131Sep 24, 2010Nov 26, 2013Seiko Epson CorporationSignal generation circuit, frequency measurement device including the signal generation circuit, and signal generation method
US8626282Nov 15, 2012Jan 7, 2014Cardiac Pacemakers, Inc.Baroreflex modulation to gradually change a physiological parameter
US8626301Jun 3, 2013Jan 7, 2014Cardiac Pacemakers, Inc.Automatic baroreflex modulation based on cardiac activity
US8643440Jul 13, 2010Feb 4, 2014Seiko Epson CorporationElectric circuit, sensor system equipped with the electric circuit, and sensor device equipped with the electric circuit
US8660648Nov 15, 2012Feb 25, 2014Cardiac Pacemakers, Inc.Implantable and rechargeable neural stimulator
US8664933May 20, 2010Mar 4, 2014Seiko Epson CorporationFrequency measuring apparatus
US8718961Oct 1, 2010May 6, 2014Seiko Epson CorporationFrequency measurement method, frequency measurement device and apparatus equipped with frequency measurement device
US20090251129 *Apr 3, 2009Oct 8, 2009Seiko Epson CorporationFrequency measurement device and measurement method
US20100125307 *Jan 26, 2010May 20, 2010Pastore Joseph MMulti-site ventricular pacing therapy with parasympathetic stimulation
DE2220781A1 *Apr 27, 1972Nov 30, 1972Cordis CorpHerzschrittmacher mit einstellbaren Betriebsparametern
DE2236434A1 *Jul 25, 1972Feb 8, 1973Medtronic IncElektromedizinisches reizstromgeraet
DE2738871A1 *Aug 29, 1977Mar 30, 1978Arco Med Prod CoHerzschrittmacher
DE2825626A1 *Jun 12, 1978Dec 21, 1978Medtronic IncDigitaler herzschrittmacher
DE2944597A1 *Nov 5, 1979May 22, 1980Medtronic IncProgrammierbarer herzschrittmacherimpulsgenerator
DE2944615A1 *Nov 5, 1979May 14, 1980Medtronic IncProgrammierbarer herzschrittmacherimpulsgenerator
DE2944616A1 *Nov 5, 1979May 14, 1980Medtronic IncImpulsgenerator fuer medizinische geraete
DE2944617A1 *Nov 5, 1979May 14, 1980Medtronic IncFuer bedarfs- und asynchronbetrieb programmierbarer herzschrittmacher
DE2944636A1 *Nov 5, 1979May 14, 1980Medtronic IncImpulsgenerator fuer medizinische geraete
DE2944637A1 *Nov 5, 1979May 14, 1980Medtronic IncProgrammierbares medizinisches geraet
EP0000988A1 *Aug 3, 1978Mar 7, 1979BIOTRONIK Mess- und Therapiegeräte GmbH & Co Ingenieurbüro BerlinDemand cardiac stimulating apparatus
EP0011938A2 *Nov 5, 1979Jun 11, 1980Medtronic, Inc.Programmable cardiac pacemaker pulse generator
EP0011939A2 *Nov 5, 1979Jun 11, 1980Medtronic, Inc.Digital cardiac pacemaker pulse generator
EP0011942A2 *Nov 5, 1979Jun 11, 1980Medtronic, Inc.Programmable cardiac pacemaker
EP0031229A2 *Dec 12, 1980Jul 1, 1981American Hospital Supply CorporationImprovements in cardiac pacer
EP0039269A1 *Apr 14, 1981Nov 4, 1981Medtronic, Inc.Pacemaker atrial refractory control for R-wave rejection
EP0058606A1 *Feb 10, 1982Aug 25, 1982Medtronic, Inc.Atrial and ventricular pacemaker
EP0857493A2 *Jan 15, 1998Aug 12, 1998Pacesetter ABHeart stimulating device with variable stimulation energy
WO1981001659A1 *Dec 10, 1980Jun 25, 1981American Hospital Supply CorpProgrammable digital cardiac pacer
WO2001034088A2Nov 13, 2000May 17, 2001Leo RubinCardiac device for electrical and chemical regulation, and vasoactive intestinal peptide for treatment of cardiopulmonary disorders
WO2002045798A2Nov 30, 2001Jun 13, 2002Resuscitek IncA medical device to restore functions of a fibrillating heart by cardiac therapies remotely directed by a physician via two-way communication
Classifications
U.S. Classification607/9
International ClassificationA61N1/365, A61N1/368
Cooperative ClassificationA61N1/365, A61N1/368
European ClassificationA61N1/368, A61N1/365
Legal Events
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Dec 5, 1988ASAssignment
Owner name: TELECTRONICS N.V., NETHERLANDS ANTILLES
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Owner name: TNC MEDICAL DEVICES PTE. LTD.
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Owner name: TELECTRONICS, N.V., DE RUYTERKADE 58A, CURACAO, NE
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