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Publication numberUS3560998 A
Publication typeGrant
Publication dateFeb 2, 1971
Filing dateOct 16, 1968
Priority dateOct 16, 1968
Also published asDE1952203A1, DE1952203B2
Publication numberUS 3560998 A, US 3560998A, US-A-3560998, US3560998 A, US3560998A
InventorsWalton Richard S
Original AssigneeHamilton Watch Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronically controlled timepiece using low power mos transistor circuitry
US 3560998 A
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

, Feb. 2, 1971 ELECTRONICALLY bONTROLLED TIMEPIECE USING LOW POWER MOS TRANSISTOR CIRCUITRY R S. WALTON Filed Oct. 16, 1968 DISPLAY FREQ. FREQ.

ACTUATING STANDARD CONVERTER MEANS 12 14 Ms l6 v 2 21 1 A HDI 2A 1A T P i P 5 (I) Am A w 0 I 46 44 3a 50 54 F H6 3- W 5 N 64 -'l N 24 34 9 d) -L F '0 l- 2 3 4 HG 2 7|\ 721 I4 74 76\ A F H F2 n A A HG 4 STAGE STAGE STAGE STAGE To SH P 2 M N A INVENTOR RICHARD S; WALTON ATTORNEYS United States Patent 3,560,998 ELECTRONICALLY CONTROLLED TIME- PIECE USING LOW POWER MOS TRAN- SISTOR CIRCUITRY Richard S. Walton, Lancaster, Pa., assignor to Hamilton Watch Company, Lancaster, Pa., a corporation of Pennsylvania Filed Oct. 16, 1968, Scr. No. 768,076 Int. Cl. G04c 3/00 US. Cl. 58-23 14 Claims ABSTRACT OF THE DISCLOSURE There is disclosed herein an electronically controlled timepiece suitable for use as a wrist watch employing an electronic oscillator operating at a frequency substantially in excess of the desired timekeeping rate, frequency reduction circuitry formed of a series of transistor stages operative in response to changes in voltage rather than current or power level changes to produce timing signal of the required frequency, actuating means responsive to the timing signal and a time display operated by the actuating means.

The present invention relates to electronic timekeeping devices and more particularly to an electronically regulated timekeeping device employing a master frequency standard of relatively high frequency and an electronic frequency converter to provide lower frequency drive signals at the desired timekeeping rate through suitable actuating means to a timekeeping display; The concepts disclosed herein are particularly adapted for use in electronic wrist watches or the like where compact construction and low power dissipation are essential.

Battery powered wrist watches and other small portable timekeeping devices of various types are well known and are commercially available. One such device which has proven to be quite successful commercially is shown and described in assignees United States Reissue Patent No. Re. 26,187, reissued Apr. 4, 1967 to John A. Van Horn et al., for Electric Watch. Electric watches of this type employ a balance wheel and a hairspring driven by the interaction of a current carrying coil and a magnetic field produced by small permanent magnets. Other types of mechanically regulated battery operated wrist watches are also known.

Considerable effort has also been directed toward the development of high accuracy wrist watches which do not employ electro-mechanical oscillators as the master speed reference. One approach which has been considered and has been subjected to substantial investigation is the use of completely electronic circuitry to generate a master drive signal for the time display. For example, it has been proposed to provide a low frequency oscillator or pulse generator operating at the desired timekeeping rate for direct drive of the time display through an electromechanical energy converter. However, difficulties have been encountered in implementing this including the difiiculty of providing a suitable stable low frequency oscillator of realistic size and power dissipation for use in a wrist watch.

Alternatively, there has been considered the use of a high frequency oscillator as a frequency standard in con junction with frequency conversion circuitry to produce a drive signal at the timekeeping rate. Unfortunatelv, there has not heretofore been available an oscillator-frequency converter combination having not only the required frequency stability, but also sufliciently low power dissipation and small size to be practical for use in a battery powered wrist watch.

The present invention overcomes the aforementioned difficulties in providing a battery operated wrist watch employing a purely electronic frequency standard. The construction employed includes a relatively high frequency oscillator and a low power integrated circuit fre quency divider coupled with a time display and suitable time display actuator. The circuitry includes an ultra low power integrated circuit, free-running multivibrator, and frequency divider constructed of a series of stages of integrated transistor circuitry so arranged that current flow through the circuit takes place only during circuit state transitions and not during the stable periods between transitions. The required circuitry can be constructed of relatively inexpensive components thereby making the new electronically controlled wrist watch commercially competitive with conventional spring driven and electric watches.

The circuit is characterized, as previously mentioned, by small size and ultra low power consumption. The primary frequency source is of a sufficiently high frequency to avoid the problems heretofore encountered with low frequency, direct drive of the timekeeping display yet not so high as to require an excessive number of frequency divider stages. Utilization of even a relatively large number of divider stages without excessive power consumption is achieved by a circuit arrangement in which circuit state transitions in response to operation of the primary frequency source are responsive to signal voltage transitions rather than current or power level changes.

The foregoing is achieved in the present invention by provision of a frequency divider constructed of a series of stages of transistor integrated circuitry, including transistors of opposite conductivity types, arranged in a complementary configuration, with a transistor of one conductivity type serving as the load circuit for a transistor of another conductivity type. Preferably, the free-running multivibration primary frequency source is also constructed in this manner.

A preferred embodiment is comprised of a plurality of metal oxide semiconductor (MOS) transistor integrated circuit stages arrayed in a complementary P- and N-channel configuration both for the primary frequency source and the divider. A suitable number of divider stages is employed to convert the primary frequency to a 1 Hz drive signal for the time display.

Accordingly, it is an object of this invention to provide an improved electronically regulated timekeeping device.

It is another object of this invention to provide an improved electronically regulated timekeeping device characterized by high accuracy, small size, and low power dissipation.

It is a further object of this invention to provide an electronically regulated timepiece as described above constructed of relatively inexpensive components yet retain- 1 ing the required accuracy and compactness to produce a commercially satisfactory product.

It is also an object of this invention to provide an electronically regulated timepiece including an electronic primary frequency source of relatively high frequency and a frequency divider, the circuitry of the frequency source and the frequency divider being so arranged that current flow through the circuit takes place only during circuit state transitions and not during the stable periods between transitions.

It is a further object of this invention to provide such an electronically regulated timepiece in which the circuit state transitions in the frequency divider circuit stages are initiated in response to change in voltage level rather than power or current level.

It is another object of this invention to provide such an electronically regulated timekeeping device comprised of a series of stages of transistor integrated circuitry including transistors of opposite conductivity types arranged in a complementary configuration with a transistor of one conductivity type serving as the load circuit for a transitor of another conductivity type.

It is an additional object of this invention to provide an electronically regulated timekeeping device including an integrated circuit high frequency oscillator and frequency divider formed of a plurality of metal oxide semiconductor transistor stages to produce timekeeping pulses, a time display, and an actuating means responsive to the timekeeping pulses for operating the time display.

It is also an object of this invention to provide an electronically regulated timekeeping device employing an oscillator-frequency converter combination including a plurality of integrated circuit metal oxide semiconductor transistor stages, each stage being constructed of an array of metal oxide semiconductor transistors in complementary N- and P-channel configuration.

It is an additional object of this invention to provide an electronic timekeeping device employing an electronic frequency divider characterized by extremely low power dissipation.

It is yet a further object of this invention to provide an electronic timekeeping device having an integrated circuit frequency divider as described above including a plurality of metal oxide semiconductor transistor stages, each stage including a plurality of transistors arranged so that the load circuit for a given transistor includes another transistor of opposite conductivity type.

The exact nature of the present invention, as well as other objects and advantages thereof, will become more apparent from consideration of the following detailed description and the accompanying drawing in which:

FIG. 1 is an overall block diagram of the electronically controlled timekeeping device in accordance with this invention;

FIG. 2 is a circuit diagram of a suitable embodiment of the frequency standard shown in FIG. 1;

FIG. 3 is a waveform diagram pertinent to the operation of the circuits, described herein;

.FIG. 4 is a block diagram showing the construction of the frequency converter shown in FIG. 1; and

FIG. 5 is a block diagram of a practical embodiment of a frequency divider circuit suitable for use in the frequency converter of FIGS. 1 and 4.

Referring now to FIG. 1, there is shown a block diagram of an electronically regulated timekeeping device in accordance with this invention. The device, generally denoted at 10, includes a frequency standard 12, frequency converter 14, a time display 16, and a display actuating means 18 coupling time display 16 to frequency converter 14. Frequency standard 12 and frequency converter 14 are constructed of a plurality of stages of transistor integrated circuitry to achieve compactness and a low order of power consumption. To achieve ultra-low power consumption, however, it has been found necessary to construct the circuitry in such a manner that current flows only during circuit state transistions and not during the stable periods between transitions.

This is best accomplished by employment of a circuit stage configuration including transistors of complementary conductivity types, with a transistor of one conductivity type serving in the load circuit for a transistor of opposite conductivity type. The circuits should employ transistors which switch in response to changes in voltage level rather than current or power levels, and are preferably formed of metal oxide semiconductor (MOS) transistor integrated circuits such as described more fully hereinafter.

Time display 16 may take several suitable forms such as the conventional watch face and cooperating second, minute, and hour hands shown. In that case, display actuating means 18 is preferably a suitable miniaturized elcctro-mechanical energy converter responsive to the periodic drive signal provided by frequency converter 14.

Frequency standard 12 provides a primary or master signal at a frequency substantially in excess of that employed in the actual operation of time display 16 and actuating means 18. Accordingly, frequency converter 14 is provided to reduce the frequency of the master signal. This produces the drive signal which operates the display actuating means 18. In a practical embodiment, a standard frequency of at least about 5 kHz., and a drive signal rate of 1 Hz. for direct drive of the second hand are preferred together with a conventional gear train mechanism to operate the minute and hour hands.

The construction of a suitable frequency standard oscillator 12 is illustrated in FIG. 2. The circuit embodies the concepts specified above, viz., complementary construction with transistors of opposite conductivity type serving mutually in load circuits for each other, and current flow only during circuit state transitions and not during the steady state periods between transitions.

In the preferred embodiment having elements responsive to changes in voltage rather than current or power levels, the circuit comprises two pairs of metal oxide semiconductor (MOS) transistors denoted 20 and 22. Tran sistor pair 20 includes a P-channel transistor 23 and an N-channel transistor 24. A source terminal 28 of P-channel transistor 23 is coupled to a positive power supply at 30 while source terminal 32 of N-channel transistor 24 is connected to ground 34. Drain terminals 36 and 38 of P-channel transistor 23 and N-channel transistor 24, respectively, are coupled together at 40. Also, gate terminals 42 and 44 of P-channel transistor 23 and N- channel transistors 24, respectively, are coupled together at 46.

Transistor pair 22 is similarly constructed and includes a P-channel transistor 48 and an N-channel transistor 50. A source terminal 52 of P-channel transistor 48 is coupled to positive power supply at 30 while a source terminal 58 of N-channel transistor 50 is connected to ground 34. Drain terminals 54 and 56 of P-channel transistor 48 and N-channel transistor 50, respectively, are coupled together at 60. Also, gate terminals 62 and 64 of P-channel transistor 48 and N-channel transistor 50, respectively, are coupled together at 66.

As is known, MOS transistors are ordinarily provided with substrate terminals. While these have been omitted here, in the interest of clarity, it should be understood that for P-channel transistors 23 and 48, substrate connections are made tothe positive power supply at 30' while for N-channel transistors 24 and 50, substrate connections are made to ground.

Common drain terminal 40 of transistor pair 20 is directly coupled to common gate terminal 66 of transistor pair 22. Also, common drain terminal 60 of transistor pair 22 is coupled through a feedback capacitor 68 to common gate terminal 46 of transistor pair 20. A further feedback path is provided by a resistor which is connected from the common junction points 40 and 66 to common gate terminal 46.

As may be appreciated, free-running multivibrator operation is achieved by the feedback paths and direct coupling described, 'with the frequency of oscillation being determined by the values selected for capacitor 68 and resistor 7 0.

Two frequency standard outputs, hereinafter denoted as F and F are provided. Output F is taken from common drain terminal 60 of transistor pair 22, while-output F0is taken at common drain terminal 40* of transistor pair 2 In operation, frequency standard oscillator 12 provides square wave outputs F and F at a frequency determined by capacitor 68 and resistor 70. The output F is at approximately the power supply voltage when output If is at ground. Conversely, the output F is at approximately the power supply voltage when output F is at ground.

The operation may best be understood by first considering transistor pairs 20 and 22 separately. For transistor pair 20, if the voltage at common gate terminal 46 is sufficiently above a certain minimum threshold volt age, P-channel transistor 23v will be in its non-conductive (OFF) state and N-channel transistor 24 will be in its highly conducting (ON) state. Under those conditions, common drain terminal 40 will essentially be shorted to ground through ON transistor 24 and the signal output 'F will be a low voltage. This will be referred to hereinafter as the zero state. On the other hand, if the volt age appearing at common gate terminal 46 is sufliciently below the threshold, the conductive states are reversed with N-channel transistor 24 being OFF and P-channel transistor 23 being ON. Under these conditions, common drain terminal 40 is shorted to the power supply terminal 30 through ON transistor 23 and the output F is at a high voltage. This will be denoted as the ONE state. Operation of transistor pair 22 is identical to that of transistor pair 20.

As previously explained, transistor pairs 20 and 22 are interconnected. Thus, the input at common gate terminal 66 is the same as the output at common drain terminal 40. If the output F is ONE, the input to common gate terminal 66 is high and N-channel transistor 50 is ON. Common drain 60 is then shorted to ground and output F is ZERO. Conversely, if the voltage at common drain terminal 40 is low, P-channel transistor 48 is ON and output F will be ONE.

To understand the mechanism of transition between ONE and ZERO states, assume that the common drain terminal 40 is at a high voltage, i.e., F is ONE. Com-mon drain terminal 60 is then at a low voltage, i.e., F is ZERO. Under these conditions, a charging path for capacitor 68 exists from power supply terminal 32 through transistor 23, resistor 70, capacitor 68, and transistor 50 to ground :whereby a positive voltage across the capacitor in the direction shown is established.

Since the positive side of capacitor 60 is coupled to common gate terminal 46 of transistor pair 20', the voltage there rises with the voltage across the capacitor, ultimately reaching a level exceeding the threshold voltage for N-channel transistor 24. This causes an inversion of the conductivity states of transistors 23 and 24, and output F switches from ONE to ZERO. Since common drain terminal 40 (output F) is directly coupled to common gate terminal 66 in transistor pair 20, the voltage there falls below the threshold voltage of N- channel transistor 50. This causes an inversion of conductivity states of transistors 48' and 50, and output F switches from ZERO to ONE.

Since the voltage across capacitor 68 cannot change instantaneously, the rapid voltage rise of output F is transmitted back to common gate terminal 46 of transistor pair 20. The latter, previously at a slightly above the threshold voltage, is now driven to a large positive value. This insures that the common drain output 40 (F) will remain at ZERO.

With conductivity states of the circuit reversed, capacitor 68 discharges to ground through resistor 70 and N-channel transistor 24. After capacitor 68 has been discharged, it begins to charge again but in the sense opposite to that indicated in FIG. 2, through a charging path from power supply terminal 32 through P-channel transistor 48, capacitor 68, resistor 70, and N-channel transistor 24 to ground.

The charging process continues until the voltage at common gate terminal 46 falls to the threshold voltage for N-channel transistor 24, whereupon the conductivity states of transistors 23 and 24 again switch. Common drain terminal 40 of transistor pair 20 and common gate terminal 66 of transistor pair 22 both rise toward the power supply voltage as transistor 23 begins to conduct. This changes output F from ZERO to ONE. Also, this causes the conductivity states of transistors 48 and 50 to reverse, which changes output F from ZERO to ONE.

Since the voltage across capacitor 68 cannot change instantaneously, the output F at common drain terminal 60 is coupled directly to common gate terminal 46 maintaining transistor 23 OFF and transistor 24 ON. At this time, the same charging path for capacitor 68 as existed orginally now exists again and the previously described process is continuously repeated. The resulting squarewave outputs F and F are shown in FIGS. 3a and 3b.

The above-described circuit possesses several distinct advantages for use in the electronic watch of this invention. However, it should be appreciated that other oscillator circuits, capable of providing highly stable operation, low power consumption, small size, etc. may be substituted.

The required frequency conversion between the frequency standard signals and the low frequency drive signal may best be accomplished by utilization of a multistate binary frequency divider illustrated schematically in FIG. 4. Frequency converter 14 includes a plurality of series connected stages, four of which are shown. Each stage is provided with a pair of input terminals and a pair of output terminals. The inputs to first stage 71 are provided by the F and F outputs of frequency standard oscillator 12. correspondingly, the input to second stage 72 is provided by the outputs of first stage 71, denoted F and F This is continued for all remaining stages whereby the output of the m stage 74 provides inputs P and F to the n stage 76. Stage 76 provides an output F which constitutes the drive signal for display actuating means 18.

Each of the stages in frequency converter 14 serves to divide the input to that particular stage by 2. Thus, a succession of n stages provides division by 2. If the frequency of output signal F is to be 1 Hz., frequency f of the standard signal must be a power of 2 and the number of stages n must be chosen in accordance with the relationship: n=l0g F. For example, frequency standard oscillator 12 must operate at 4096 Hz. with a frequency converter 14 having 12 stages (11:12) to achieve a drive frequency of 1 Hz.

To achieve suitably low power dissipation levels to render such a multistage counter arrangement practical for use in a battery powered wrist watch, it has been found preferable to employ integrated circuits of a particular type as now described in detail. The particular circuitry which has been employed here is of the type described in connection with FIG. 2 above employing pairs of complementary voltage-level sensitive transistors so arranged that transistors of opposite conductivtiy type serve mutually in load circuits for each other. Again, the circuit configuration is preferably such that current flow occurs only during state transitions. To achieve compactness and low power consumption, integrated circuit construction should be employed here as in FIG. 2.

The construction and operation of a suitable embodiment employing complementary MOS circuitry will now be described in connection with FIGS. 3 and 5.

As illustrated in FIG. 5, the circuit is constructed of a series of MOS transistor pairs, some of which serve signal transmission or gating functions and others of which serve frequency conversion or logic functions. These will be denoted as transmission pairs and logic pairs respectively.

Specifically, the circuit comprises a first transmission pair 78 including a P-channel transistor 80 and an N-channel transistor 82 connected source-to-source at 84 and drain-to-drain at 86. Gate 88 of P-channel transistor 80 is connected to the F input while gate 90 of N-channel transistor 82 is connected to the F input. As will be understood, the F and F inputs constitute the high frequency inputs which are divided by a factor of 2 in each stage of frequency converter 14 shown in FIG. 4.

A second transmission pair 92 includes a P-channel transistor 94 and an N-channel transistor 96, coupled source-to-source at 98 and drain-to-drain at 100. Gate 102 of N-channel transistor 96 is connected to the F input while gate 104 of P-channel transistor 94 is connected to F input. Common source terminal 98 of transmission pair 92 is connected to common drain terminal 86 of transmission pair 7 8.

A first logic pair 106 is formed of a P-channel transistor 108 and an N-channel transistor 110, connected at a common gate terminal 112 and at common drain terminal 114. Common gate terminal 112 is connected to output 86 of transmission pair 7 8. A source terminal 116 of P-channel transistor 108 is connected to the power supply at 118 while a source terminal 120 of N-channel transistor 110 is connected to ground at 122.

A second logic pair 124 is formed of a P-channel transistor 126 and an N-channel transistor 128 connected at a common gate terminal 130 to common drain terminal 114 of logic pair 116 and also by a feedback path 132 at common drain terminal 134 to output terminal 100 of transmission pair 92. A source terminal 136 of P-channel transistor 126 is connected to power supply at 118 while a source terminal 138 of N-channel transistor 128 is connected to ground at 122.

The circuit of FIG. also includes a second identical grouping of two transmission pairs 140 and 142 and logic pairs 144 and 146. Transmission pair 140 includes a P-channel transistor 148 and an N-channel transistor 150 connected source-to-source at 152 and drain-to-drain at 154. Gate terminal 156 of P-channel transistor 148 is connected to input F while gate terminal 158 of N-channel transistor 150 is connected to input F.

Transmission pair 142 includes a P-channel transistor 160 and an N-channel transistor 162 connected sourceto-source at 164 and drain-to-drain at 166. Gate 168 of P-channel transistor 160 is connected to input F while gate 170 of N-channel transistor 162 is connected to input F.

Logic pair 144 includes a P-channel transistor :172 and N-channel transistor 174 having a common gate connection 176 and a common drain connection 178. Logic pair 146 includes a P-channel transistor 180 and an N-channel transistor 182 having a common gate terminal 184 and a common drain terminal 186. Terminals 188 and 190 of P-channel transistors 172 and 180 are connected to power supply at 118 while source terminals 192 and 194 of N-channel transistors 174 and 182 are connected to ground at 122. A circuit output F is provided at common drain terminal 178 of logic pair 144 while a second circuit output F is provided at common drain terminal 186 of logic pair 146.

Common drain terminal 186 also provides a feedback connection 196 to terminal 164 of transmission gate 142 and a second feedback connection 198 coupled to terminal 84 of transmission gate 78. As in case of primary frequency source 12 described above, the substrate terminals for the various MOS transistors are not shown in the interest of clarity but it should be understood that in all cases, the substrates of P-channel transistors are coupled to the power supply and the substrates of N-channel transistors are coupled to ground.

To understand the operation of the above-described circuit, it should be recalled that for P-chaii'nel depletion mode operation, a source to drain conductive path exists for low gate voltages. Increasing gate voltage reduces the conductivity, ultimately turning the transistor off when sufficient gate voltage is attained. Conversely, for N-channel enhancement operation, a conductive path does not exist for small gate voltages but rather is established when the gate voltage exceeds a minimum positive gating threshold.

By way of example, for transmission pair 78, a ONE input state for F and a ZERO input state for F (high and low voltages respectively) will maintain both transistors 80 and 82 in a non-conductive (OFF) state. Conversely, in transmission pair 140, both transistors 148 and 150 will be in the conductive (ON) state.

As to logic pair 106, a positive voltage at common gate terminal 112 exceeding the gating threshold will turn N-channel 110 ON and P-channel transistor 108 OFF. This establishes common drain output terminal 114 at ground potential through conducting transistor 110. Conversely, a low voltage at common gate terminal 112 will turn P-channel transistor 108 ON and turn N-channel transistor OFF, which establishes common drain terminal 114 at essentially the power supply potential through conducting transistor 108.

Description of the actual operation of the circuit illustrated in FIG. 5 is most conveniently given in terms of the operating states of the transmission pairs and logic pairs rather than in terms of the voltages associated with the individual transistors themselves. Thus, a transmission pair will be referred to as ON when both of the component transistors are conducting and OFF when both of the component transistors are non-conducting. Likewise, the output of a logic pair will be denoted as ON-E When its common drain terminal voltage is high, i.e., when the input at the common gate terminal fails to exceed the gating threshold, thereby rendering the P-channel transistor conductive and the N-channel transistor non-conductive. Conversely, the output of a logic pair will be denoted as ZERO when the voltage at the common drain terminal is low, i.e., when the input at the common gate terminal exceeds the gating threshold thereby rendering the P-channel transistor non-conductive and the N-channel transistor conductive.

With the foregoing in mind, and with reference to FIGS. 3a3d, and 5, assume that input states F and T switch to ZERO and ONE, respectively at time Transmission pairs 78 and 142 go ON and transmission pairs 92 and 140 go OFF. Assume also that the output of logic pair 144 is high, this makes output state F =ONE. (The alternative assumption of the output of logic pair 144 being low is also valid; this simply results in a one-half cycle shift in circuit operation as will be apparent from the description.) As a result, the input to logic pair 146 is ONE, and output state F is ZERO, as illustrated in FIGS. 30 and 3d.

Common gate terminal 112 of logic pair 106 is directly connected to ground at 122 through the N-channel transistor 182 in logic pair 146, feedback path 198, and ON transmission pair 78. Consequently, P-channel transistor 108 is ON, and logic pair 106 is in the ONE state. The resulting high voltage at common gate terminal of logic pair 124 maintains the N-channel transistor 128 ON, and the common output 134 is low.

At time t the input states F and F change to ONE and ZERO, respectively. Transmission pair 78 goes OFF and transmission pair 92 goes ON. The output of logic pair 106 is maintained in the ONE state since common gate terminal 112 is now coupled to ground through transmission pair 92, feedback path 132, and conducting N- channel transistor 128 in logic pair 124. (The latter is maintained conducting by the continued high output at common drain 114 of logic pair 106.)

The input transition at time 1 also turns transmission pair ON. This transfers the ONE state output of logic pair 106 to common gate terminal 176 of logic pair 144. Output 178 then switches to the ZERO state and circuit output state F goes to ZERO as shown in FIG. 30. This in turn switches logic pair 146 to the ONE state, and circuit output state F goes to ONE, as illustrated in FIG. 3d.

At time t the input states F and F again change to ZERO and ONE respectively. This turns transmission pair 78 ON, and couples the ONE output of logic pair 146 to the input of logic pair 106 through feedback path 198. This establishes output 114 in the ZERO state which in turn establishes output 134 of logic pair 124 in the ONE state.

The input transition at time t also causes transmission pair 140 to be turned OFF and 142 to be turned ON thereby connecting common gate terminal 176 of logic pair 144 through feedback path 196 to the output of logic pair 146. Since the latter is in the ONE state, this maintains the output of logic pair 144 in the ZERO state. This, in turn, maintains the circuit output F at ZERO, as shown in FIG. 30.

correspondingly, the low level at drain terminal 178 is connected to common gate 184 of logic pair 146. This maintains P-channel transistor 180 conductive with common drain 186 still connected to the power supply. This keeps circuit output state T at ONE as shown in FIG. 3%

During the next input transition at time t F and F switch to ONE and ZERO, respectively, as shown in FIGS. 3a and 3b. This turns transmission pair 78 OFF and transmission pair 92 ON so that common gate terminal 112 of logic pair 106 is connected through feedback path 132 to output 134 of logic pair 124. The latter is already in the ON state, since common drain terminal 114 was low during time t -t due to the connection of gate terminal 112 through transmission pair 78 and feedback path 198 to drain terminal 186. Accordingly, there is no change in the output states of either logic pair 106 or 124.

The input transition at time t also causes transmission pair 140 to be turned ON and transmission pair 142 to be turned OFF. This causes common gate terminal 176 of logic pair 144 to be connected to the output of logic pair 106. The low signal level at gate 176 causes logic pair 144 to switch states since the output 178 of logic pair 144 Was low during time t t due to connection of gate 176 through ON transmission pair 142 and feedback path 196 to drain 186 of logic pair 146. As a result, circuit output F switches from ZERO to ONE as shown in FIG. 3c. Likewise, logic pair 206 switches states and circuit output F goes from ONE to ZERO as shown in FIG. 3d.

During the next input transition at time L F and F return to ZERO and ONE, respectively as shown in FIGS. 3a and 3b. The circuit has returned to the initially described conditions and the sequence of operations described above is repeated. Comparing FIGS. 3a and 3c, and FIGS. 3b and 3d, it may be seen that outputs F and F provided complementary signal transitions in response to transitions of the inputs F and I at a frequency exactly one-half the input frequency.

To achieve the desired degree of frequency division, it is merely necessary to combine a series of stages as described in FIG. 5 into a chain as shown in FIG. 4. Even a moderately large number of stages will be small enough for use in a wrist Watch and will consume a realistically small amount of power.

In the foregoing, there has been described an electronically regulated timekeeping device characterized by sufficiently small size and low power dissipation to be practical for use in a device of wrist watch size. While the preferred embodiment and certain especially significant operating conditions have been set forth in detail, it should be understood that various modfications will be apparent to those skilled in the art in light of the foregoing description. These would include, for example, substitution of other circuit designs for the frequency standard oscillator described in connection with FIG. 2, as well as substitution of alternative time display means for the watch face and hands illustrated. One such modification contemplated could be an optical display providing an illuminated time indication. In this case, display actuating means 18 would be suitable integrated circuit switching means providing selective actuation of the display elements in response to the drive signal output of frequency converter 14. Variation of transistor types for the latter circuit, consistent with the requirements set forth herein may also be possible.

Thus, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiment is therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the 10 appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

What is claimed and desired to be secured by United States Letters Patent is:

1. An electronically regulated timekeeping device of sufficiently small size and power consumption for use as a wrist watch including an electronic signal source to generate a master frequency signal; a time display; means for actuating said time display in response to said master frequency signal; and frequency conversion means coupling said electronic signal source to said actuating means for substantially reducing the frequency of said master signal, said frequency conversion means comprising: a plurality of stages of transistor integrated circuitry, each stage including a plurality of transmission pairs, each transmission pair comprising a P-channel MOS transistor and an N-channel MOS transistor coupled together in a sourceto-source and drain-to-drain configuration, the gate terminals of said transistors being coupled to said electronic signal source; and a plurality of logic pairs, each logic pair comprising a P-channel MOS transistor and an N-channel MOS transistor coupled together in a gate-to-gate and and drain-to-drain configuration, the source terminal of the P-channel transistor being adapted to be connected to a positive power supply terminal and the source terminal of the N-channel transistor being adapted to be connected to a negative power supply terminal; and means coupling the drain and gate terminals of said logic pairs together through the source-to-drain conductive path formed in each of said transmission pairs.

2. An electronically regulated timekeeping device as defined in claim 1 wherein said electronic signal source comprises means for generating a first binary signal and a second binary signal complementary to said first binary signal; and means providing said first and second binary signals separately to said frequency conversion means; wherein the gate terminal of one transistor in each of said transmission pairs is coupled to said first binary signal, and the gate terminal of the other transistor in each of said transmission pairs is coupled to the second binary signal.

3. An electronically regulated timekeeping device as defined in claim 2 wherein: each stage of said frequency conversion means comprises two substages, each including two transmission pairs and two logic pairs; the drain terminal of the first logic pair in each of said substages bein coupled to the gate terminal of the second logic pair in each of said substages; the first transmission pair in each of said substages providing a feedback connection from the drain terminal of the second logic pair to the gate terminal of the first logic pair in the respective stage; the second transmission pair in the first substage providing a feed-back connection from the drain terminal of the second logic pair in the second substage to the gate terminal of the first logic pair in the first substage; the second transmission pair in the second substage providing a direct connection from the drain terminal of the first logic pair in the first substage to the gate terminal of the first logic pair in the second substage; a first stage output being provided at the drain terminal of the first logic pair in the second substage, and a second stage output, complementary to said first output, being provided at the drain terminal of the second logic pair in the second substage.

4. An electronically regulated timekeeping device as defined in claim 3 wherein the gate terminals of the N- channel transistors in the first transmission pair of said first substage and the second transmission pair of the second substage, and the gate terminals of the P-channel transistors in the second transmission pair of the first substage and the first transmission pair of the second substage are connected to the first binary output of said electronic signal source; the gate terminals of the P-channel transistors in the first transmission pair of the first sub- 11 stage and the second transmission pair of the second substage, and the gate terminals of the N-channel transistors in the second transmission pair of the first substage and the first transmission pair of the second substage being connected to the output of the electronic signal source.

5. An electronically regulated timekeeping device as defined in claim 4 including a plurality of stages; the gate terminals of the transmission pairs in a subsequent stage being connected to the first and second complementary stage outputs of the preceding stage.

6. An electronically regulated timekeeping device of sufficiently small size and power consumption for use as a wristwatch including: an electronic signal source to generate a master frequency signal; a time display; means for actuating said time display in response to said master frequency signal; and frequency conversion means coupling said electronic signal source to said actuating means for substantially reducing the frequency of said master signal, said frequency conversion means comprising: a plurality of stages of transistor integrated circuitry, each stage including a plurality of logic means and a plurality of signal transmission means coupling said logic means together, said logic means and said signal transmission means having control inputs and signal paths, with the conductivity states of said signal paths being switchable in response to changes in the signal at said control inputs, substantial current flow in said signal paths occuring only during transition between conductivity states, the logic means and signal transmission means in each of said stages of transistor integrated circuitry being comprised of first transistors of a predetermined conductivity type, and second transistors of opposite conductivity type, coupled together with transistors of one conductivity type serving in a load circuit for transistors of the opposite conductivity type.

7. An electronically regulated timekeeping device of sufiiciently small size and power consumption for use as a a wristwatch including: an electronic signal source to generate a master frequency signal; a time display; means for actuating said time display in response to said master frequency signal; and frequency conversion means coupling said electronic signal source to said actuating means for substantially reducing the frequency of said master signal, said frequency conversion means comprising: a plurality of stages of transistor integrated circuitry, each stage including a plurality of logic means and a plurality of signal transmission means coupling said logic means together, said logic means and said signal transmission means having control inputs and signal paths, with the conductivity states of said signal paths being switchable in response to changes in the signal at said control inputs, substantial current flow in said signal paths occurring only during transition between conductivity states, each stage of said frequency conversion means including a plurality of logic pairs, each logic pair comprising a P- channel MOS transistorand an N-channel MOS transistor coupled together in a gate-to-gate and drain-to-drain configuration; and MOS transistor signal transmission means coupling the drain and gate terminals of said logic pairs together.

8. An electronically regulated timekeeping device of sufficiently small size and power consumption for use as a wristwatch including: an electronic signal source to generate a master frequency signal; a time display; means for actuating said time display in response to said master frequency signal; and frequency conversion means coupling said electronic signal source to said actuating means for substantially reducing the frequency of said master signal, said frequency conversion means comprising: a plurality of stages of transistor integrated circuitry, each stage including a plurality of logic means and a plurality of signal transmission means coupling said logic means together, said logic means and said signal transmission means having control inputs and signal paths, with the conductivity states of said signal paths being switchable in response to changes in the signal at said control inputs,

substantial current flow in said signal paths occurring only during transition between conductivity states, each transistor being provided with two terminals defining a signal path through said transistor and a third terminal providing a control input for said transistor; pairs of said transistors being arranged as said logic means, each of said logic means comprising two transistors of opposite conductivity types having a series connection of said signal paths and a parallel connection of said control input terminals; said signal transmission means selectively coupling the signal paths and the control input terminals of said logic means together as a function of the output of said electronic signal source, and as a function of previously existing conductivity states in said circuit.

9. An electronically regulated timekeeping device of sufficiently small size and power consumption for use as a wristwatch including: an electronic signal source to generate a master frequency signal; a time display; means for actuating said time display in response to said master frequency signal; and frequency conversion means coupling said electronic signal source to said actuating means for substantially reducing the frequency of said master signal, said frequency conversion means comprising a plurality of stages of transistor integrated circuitry forming a binary divider chain, each stage comprising at least one pair of complementary MOS transistors including a P-channel MOS and a N-channel MOS transistor, with the conductivity states of said MOS transistors being switchable in response to changes in the signal at the input of the stage whereby substantial current flow through said transistors occurs only during transition between conductivity states.

10. An electronically regulated timekeeping device as defined in claim 9 wherein said transistors comprise logic pairs coupled together in gate-to-gate and drain-to-drain configuration.

11. An electronically regulated timekeeping device as defined in claim 7 wherein said electronic signal source provides a pulse waveform defining time periods; and wherein the signal transmission means cooperate with the logic pairs and respond to changes in the signal level of the pulse waveform to establish conductivity states of said transistors during a given period as a function of the pulse waveform during that period and as a function of the conductivity states of said transistors during the previous time period.

12. An electronically regulated timekeeping device as defined in claim 8 wherein each signal transmission means comprises a pair of transistors of opposite conductivity type having a parallel connection of said signal paths and connection of said control input terminals to the output of said electronic signal source.

13. An electronically regulated timekeeping device as defined in claim 8 wherein said electronic signal source provides a pulse waveform defining time periods; and wherein the signal transmission means cooperate with the logic means and respond to changes signal level of the pulse waveform to establish conductivity states for the transistors in said logic means during a given time period as a function of the conductivity states of said transistors during the previous time period.

14. An electronically regulated timekeeping device as defined in claim 13 wherein said signal transmission means respond to changes in the voltage of said pulse waveform rather than changes in current or power in said waveform.

References Cited FOREIGN PATENTS 791,946 8/1968 Canada 5823 U.S. Cl. X.R. 33ll7, 144

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
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US3760580 *Feb 2, 1972Sep 25, 1973Suwa Seikosha KkBinary divider circuit for electronic watch
US3839856 *Jan 24, 1972Oct 8, 1974Time ComputerSolid state watch with calendar display
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US3930169 *Sep 27, 1973Dec 30, 1975Motorola IncCmos odd multiple repetition rate divider circuit
US3938318 *Jun 8, 1973Feb 17, 1976Texas Instruments IncorporatedWrist watches
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US4214173 *Mar 3, 1978Jul 22, 1980Standard Microsystems Corp.Synchronous binary counter utilizing a pipeline toggle signal propagation technique
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Classifications
U.S. Classification368/87, 331/75, 331/113.00R, 331/17, 968/902, 377/121, 331/144
International ClassificationG04G3/02, G04G3/00
Cooperative ClassificationG04G3/02
European ClassificationG04G3/02