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Publication numberUS3571757 A
Publication typeGrant
Publication dateMar 23, 1971
Filing dateMay 24, 1968
Priority dateMay 27, 1967
Also published asDE1762313A1, DE1762313B2, DE1762313C3
Publication numberUS 3571757 A, US 3571757A, US-A-3571757, US3571757 A, US3571757A
InventorsKiyasu Zeniti, Miki Tetsuya
Original AssigneeFujitsu Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Cascaded coder for a pulse modulation system
US 3571757 A
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Description  (OCR text may contain errors)

United States Patent Inventors Zeniti Kiyasu;

Tetsuya Miki, Sendai-shi, Japan Appl. No. 731,781 Filed May 24, 1968 Patented Mar. 23, 1971 Assignee Fiyitsu Limited Kawasaki, Japan Priority May 27, 1967, Aug. 21, 1967 Japan Tokugansho, 42-33842 and 4253653 CASCADED CODER FOR A PULSE MODULATION SYSTEM 9 Claims, 27 Drawing Figs.

11.8. C1 332/9, 325/38, 328/55, 328/151, 340/347, 340/348 Int. Cl 1103k 7/10, l-l03k 5/159, H03k 13/74 Field of Search 332/1, 99

(T), 11, 11 (D), 15, 10,22,;328/51,55, 151; 340/348, 360, 354, 347 (A-D); 325/38, 38.1

[56] References Cited UNITED STATES PATENTS 2,770,777 11/1956 Feisse1..... 332/1 3,035,258 5/1962 Chasek 340/347 3,134,971 5/1964 Sem-Sandberg.... 340/347 3,403,226 9/1968 Wintringham 332/11X 3,419,819 12/1968 Murakamiet al... 332/9 Primary Examiner-Alfred L. Brody Attorneys-Curt M. Avery, Arthur E. Wilfond, Herbert L.

Lerner and Daniel J. Tick PATENTEDKAR23I97I 357L757 sum 70F 9 FIGJIA AMPLITUDE F/GJ/B AMPL Tl/DE F/GJ/C fksaue/vcrf EASEADETB CQDEEQ FOR A PULSE MQDULATHGN SYTEM DESCRIPTION OF THE INVENTION The present invention relates to a cascaded coder. More particularly, our invention relates to a cascaded coder for a pulse modulation system. The coder is utilized in analog-todigital conversion or the like in a pulse code modulation system of FCM system or in a telemetering system.

Known coders of the aforementioned type include the successive feedback comparison type coder, the counter type coder, the pulse code tube type coder, and the cascaded coder. Of these types, those best suited for high speed coding are the pulse code tube type coder and the cascaded coder. The pulse code tube type coder, however, utilizes an electron beam in an electron tube and has disadvantages or defects which require a hot cathode for termionic radiation. The pulse code tube type coder thus requires a high voltage power source of accelerating electrons. Furthermore, the life of such a coder is'short. For these reasons, only the cascaded coder may provide high speed coding by utilizing integrated circuits.

A cascaded coder comprises a plurality of pulse-modulating circuits, each of which is a unit circuit or stage. The number of unit circuits utilized may vary and is equal to the number of bits in the code. Each unit circuit comprises input and output characteristics and provides a binary code output. The unit circuits are connected in cascade with each other. A disadvantage or defect of the cascade type coder is that high speed coding becomes more difficult with an increase in the number of coding bits.

The principal object of the present invention is to provide a new and improved cascaded coder.

An object of our invention is to provide a cascaded coder which overcomes the disadvantages of the coders of known type.

An object of the present invention is to provide a high speed order.

An object of the present invention is to provide a high speed cascaded coder.

An object of the present invention is to provide a high speed cascaded coder which does not decrease in speed as the number of coding bits increases.

in accordance with the present invention, the cascaded coder provides high speed coding due to an increase in the density of a pulse amplitude modulated or PAM pulse supplied to the input of the coder. The increase in the value of the unit circuit until the regulation or required value is reached requires a considerable period of time due to the frequency characteristics of the components utilized in said unit circuits. The period of time increases in a next-succeeding unit circuit, since each unit circuit or stage is adversely affected by the next-preceding unit or stage. For this reason, in a conventional cascaded coder, the operating time of each unit circuit or stage must be made equal to the operating time of the last unit circuit, so that a considerable period of time is required for coding. p

In order to overcome the aforementioned disadvantage, the cascaded coder of our invention includes a pulse-shaping circuit connected between each adjacent pair of unit circuits. Each pulse-shaping circuit comprises a sampling circuit. An input supplies an input signal to the sampling circuit. A holding circuit is connected to the sampling circuit and an output is connected to the holding circuit. This prevents the waveform supplied to a unit circuit from being adversely affected by the next-preceding unit circuit. This permits the operating time of each of the stages to be equal to the operating time of the first stage and thereby provides high speed coder operation.

The speed of the coding operation may be further increased by variation of the amplifying characteristic or amplification factor of the amplifier included in each unit circuit and by sampling at the instant at which the regulated or required value is reached. The regulated or required value is reached sooner by such variation of the amplification factor or amplifying characteristic. The sampling is further facilitated by providing an even, smooth or level characteristic after the output of the unit circuit provides the regulated value at an earlier instant.

In accordance with the present invention, a cascaded coder for a pulse modulation system comprises a plurality of pulsemodulating circuits and a plurality of pulse-shaping circuits, as hereinbefore described, each comprising the aforedescribed circuit. Each of the pulse-modulating circuits may comprise a comparator and a delay. An input supplies an input signal to the comparator and to the delay. An adder is connected to the delay. A switch operated by the comparator interconnects a bias voltage source to the adder for applying bias voltage to the adder in accordance with a result provided by the comparator. An amplifier is connected to the adder. Each of the pulse-modulating circuits may comprise a comparator and a rectifier. An input supplies an input signal to the comparator and to the rectifier. An adder is connected to the rectifier. A bias voltage source is connected to the adder. An amplifier is connected to the adder.

Each of the pulse-modulating circuits includes a delay for an input signal, an adder connected to the delay for adding a signal to the input signal and an amplifier connected to the adder. The amplifier has a transient response characteristic which provides the required value in a short period of time thereby providing a level response characteristic. The amplifier may have a low frequency amplification factor which is larger than the required amplification factor, or a high frequency amplification factor which is the turnover value of the amplification factor.

Each of the pulse-modulating circuits includes an amplifier having an input. An initial pulse plus a delayed and attenuated initial pulse are applied to the input of the amplifier. The amplifier comprises a circuit for attaining the required level in a brief period of time relative to the combined pulses and providing a level response characteristic.

in order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings, wherein:

FlG. l is a block diagram of a known type of cascaded coder of a normal binary system;

F KG. 2 is a block diagram of a known type of cascaded coder of a reflected binary system;

FIG. 3 is a block diagram of an embodiment of the cascaded coder of the present invention;

FIG. 4 is a circuit diagram of a pulse-shaping circuit which may be utilized in the coder of H6. 3;

FlGS. 5A, 5B, 5C and 5D are graphical presentations of the waveforms appearing in the coder of FlG. 3;

FIG. 6 is a graphical presentation of an amplifying characteristic of an amplifier;

FIGS. 7A, 7B, 7C and 7D are graphical presentations illustrating the variations of the voltage or current characteristic of an amplifier;

FIG. 8 is a circuit diagram of the equivalent circuit of an amplifier;

FIG. 9 is a modification of the circuit of F IG. 3;

FIG. lid is a modification of the circuit of F l6. 9;

FIGS. MA, MB and MC are graphical presentations of the frequency characteristic of the circuit of F l6. 10;

FIG. 12A is a graphical presentation of part of a PAM input waveform:

FIG. T23 is a graphical presentation of part of a response output waveform;

Flt lIiA is a graphical presentation of an input pulse supplied to an amplifier;

FlG. 13B is a graphical presentation of the response waveform of the amplifier;

FlGS. 114A, 14.8 and MC are graphical presentations of the response waveforms; and

FlG. 15 is a block diagram of an embodiment of an amplifier circuit of the present invention which provides the ad- 3 vantages ofFlGS. 11A to 11C, 12A, 1213, 13A, 13B and 14A to 14C.

In FlG l, a first unit circuit or stage 11, a second unit circuit or stage 12, a third unit circuit or stage 13, a fourth unit circuit or stage 14 are cascade-connected to each other in known manner with the unit circuit 12 following the unit circuit 11, the unit circuit 13 following the unit circuit 12, etc. Each unit circuit is the same as the others, so that only the first unit circuit 11 will be described.

A PAM input signal is supplied to the first unit circuit 11 via an input terminal 15. The input signal is supplied to an analogue delay line 16 via a lead 17 and to a comparator 18 via the lead 17 and a lead 19. The delay line 16 provides the required delay time. An adder 21 is connected to the delay line 16 via a lead 22. A bias power source 23, which provides a voltage E1, is connected to the adder 21 via a switch 24 connected in a lead 25. The comparator 18 is mechanically or otherwise suitably coupled to the switch 24. An amplifier 26 is connected to the adder 21 and provides an output signal at an output terminal 28. The output signal at the output terminal 28 is supplied to the delay line 29 and the comparator 31 via leads 32 and 33. The delay line 29 and the comparator 31 are part of the unit circuit 12. The unit circuit 12 is indentical with unit circuit 11 and functions in the same manner.

Any suitable number of unit circuits may be utilized,

although four unit circuits ll, 12, 13 and 14, are shown in FIG. 1. A PCM output pulse or signal is provided at an output terminal 34 of the unit circuit 11. The output terminal 34 is connected to the comparator 18 via a lead 35. A PCM output pulse or signal is provided at an output terminal 36 of the unit circuit 12. The output terminal 36 is connected to the comparator 31 via a lead 37. The PCM output pulse or signal is provided by the unit circuit 13 at an output terminal 38 and the PCM output signal of the unit circuit 14 is provided at an output terminal 39.

The PAM pulse or signal fed to the input terminal of the unit circuit 11 has a polarity or sign which is detected by the comparator 18. If the sign is positive, a PCM pulse is provided at the output terminal 34. The comparator 18 functions to close the switch 24, so that a negative bias voltage E1 is appliedto the adder 21 where it is added to the PAM pulse provided by the delay line 16 after a suitable delay in time. If the polarity of the PAM pulse is negative,-the switch 24 remains open. The amplitude of the PAM pulse to which either the reference voltage of the reverse polarity has been applied or has not been applied, as described, is doubled by amplification in the amplifier 26. The amplified PAM pulse provided by the amplifier 26 is supplied to the delay line 29 and the comparator 31 of the next succeeding unit circuit 12 via the output terminal 28 and the leads 32 and 33. Theunit circuit 12 then functions in the same manner as the unit circuit 11 and provides a signal to the next succeeding unit circuit 13. The number of unit circuits utilized in the coder of FIG. 1 is equal to the number of bits in the code utilized.

FIG. 2 shows a coder of a reflected binary system. In FIG. 2, a PAM input pulse or signal is supplied via an input terminal 41 and a lead 42 to a rectifier 43. The input signal is supplied to a comparator 44 via the lead 42 and a lead 45. The rectifier 43 functions to provide uniform polarities to the analogue pulses. An adder 46 is connected to the rectifier 43 via lead 47. A source of bias voltage E1 is connected to the adder 46 via a lead 48. An amplifier 49 is connected to the adder 46 via a lead 51. An output terminal 52 is connected to the amplifier 49. The amplification provided by the amplifier 49 is 2. A PCM output signal or pulse is provided at an output terminal 53 which is connected to the comparator 44 via a lead 54.

The polarity or sign of the PAM input signal supplied to the input terminal 41 is detected bythe comparator 44. If the polarity of the PAM input signal is positive, a PCM output pulse or signal is provided at the output terminal 53. The PAM input signals are also supplied to the rectifier 43 and are rectified so that they all have a negative polarity or sign, for example. The PAM input pulse is added in the adder 46 to the bias voltage El, which is of positive polarity and which has a magnitude equal to one-half the maximum amplitude level in the adder 46..lf the polarities of the PAM input pulses are all made positive by the rectifier 43, the bias voltage E1 is a negative voltage.

In illustration of the foregoing description, if the PAM input pulse is between +8 volts and -8 volts, the bias voltage E1 is +4 volts. The amplitude of the analogue pulse, which is the sum of the PAM input pulse and the bias voltage E1, is doubled in amplitude by the amplifier 49 and is supplied to the rectifier 55 and the comparator 56 of the next-succeeding unit circuit via the output terminal 52 and leads 57 and 58. The polarity of the signal supplied to the second unit circuit via the output terminal 52 is detected by the comparator 56 thereof. If the polarity is positive, a PCM output signal or pulse is provided at an output terminal 59 connected to the comparator 56 by a lead 61. The PCM output pulse or signal is a binary 1. If the polarity is negative, a binary 0 is provided at the output terminal 59. The analogue pulse, as in the first unit circuit or stage, is transferred through the rectifier 55 and thence through an adder and an amplifier and is then supplied to the next-succeeding, or third, unit circuit. Reflected binary coding is thereby accomplished. in a conventional cascaded coder of the aforedescribed type, the frequency band of the amplifier of each unit circuit is finite, so that response to the input pulse is incomplete. For this reason, the increasing or rising characteristic of the output pulse of the unit circuit deteriorates. Furthermore, a unit circuit includes a rectifier in a reflected binary coder, and the voltage is shifted in a normal binary coder, so that the unit circuit provides a complicated response to an input, the rising or increasing characteristic of which is deteriorated, as aforementioned. The input signal waveform in a later stage is afiected by the preceding stages, so that a longer period of time is required than in each of the preceding stages in order to attain the even part of the pulse waveform to theattainment of the level part of the pulse, including an allowable error, is defined as the setting time, the holding time required of the input holding pulse must be longer than the longest of the setting times of the'stages. This has caused a decrease of the speed of operation of a known coder.

in a cascaded coder, in general, when the allowable error of coding is regulated and the characteristics of the unit circuits are all made equal to each other, the setting time becomes the longest in the later stage. Thus, for example, if the allowable error is 5 percent of the final quantization stage and the period I of time required for the rising or increasing of the amplifier of a unit circuit is 3 nanoseconds, in a reflected binary coder involving a 9-bit code, the setting time of the first stage is 16 nanoseconds and the setting time of the ninth stage is 33 nanoseconds. The holding time of the input pulse must then be longer than 33 nanoseconds.

The disadvantage of the decreasedspeed of operation of a known coder is overcome, in accordance with out invention, by connecting pulse shaping circuits between the unit circuits of the coder. FIG. 3 shows a cascaded coder of the present invention which performs coding in a 9-bit code. In FIG. 3, the first unit circuit 71, the second unit 72 and the ninth unit circuit 73 are illustrated. The third, fourth, fifth, sixth, seventh and eighth unit circuits are not shown in order to maintain the clarity of illustration. Each of the unit circuits is identical with the aforedescribed unit circuits of FIGS. 1 or 2. The unit circuit 71 has an analogue pulse input terminal 74 and an analogue pulse output terminal 75. The unit circuit 72 has an analogue pulse input terminal 76 and an analogue pulse output terminal 77. The unit circuit 73 has an analogue pulse input terminal 78. The unit circuit 71 has a PCM pulse output terminal 79. The unit circuit 72 has a PCM pulse output terminal 81. The unit circuit 73 has a PCM pulse output terminal 82.

In accordance with the present invention, a pulse-shaping circuit 83 is connected between the output terminal 75 of the unit circuit 71 and the input terminal 76 of the unit circuit 72. A pulse-shaping circuit 84 is connected between the output terminal 77 of the unit circuit 72 and the input terminal of the next-succeeding, or third, unit circuit (not shown in FIG. 3). A pulse-shaping circuit 55 is connected between the output terminal of the eighth unit circuit (not shown in FIG. 3) and the input terminal 7% of the ninth unit circuit 73. Each pulse-shaping circuit 33, $4, $5, and so one, samples the pulse voltage when the output pulse of the next-preceding stage becomes stable within the allow able error, and holds said pulse voltage. The pulse-shaping circuit then transfers the held pulse voltage to the input terminal of the next-succeeding unit circuit or stage.

A circuit diagram of an embodiment of a pulse-shaping circuit which may be utilized as the pulse-shaping circuit 83, 84, 85, or the like, bl-ShOWl'l in FlG. 4. in F IG. 4, a balanced gate circuit as comprises a plurality of diodes d7, 38, 89 and 93, connected in tlie manner of a full-wave rectifier. An input signal is supplied via an input terminal 92, which which is connected to the circuit lid via a lead 93. A voltage holding or storing capacitor 9 is connected in parallel with the circuit 86 via a lead 95 and a lead 96. The circuit 86 is connected to an amplifier 917 via the lead 95. An output terminal E li is connected to the amplifier :7 via a lead 99. The amplifier 97 has a high input impedance. The voltage storing capacitor 94 and the amplifier 97 comprise a holding circuit 101.

A loop comprising a resistor Hi2 and the secondary winding 1103 of a transformer Md connected in series with each other and leads we and lllld, is connected to the outputs of the circuit 36. A capacitor M7 is connected in shunt across the resistor W2 and the RC circuit M2, 1107 functions to provide a reversed bias of the diodes of the gate circuit 86 when there is no timing or clock pulse. The transformer MP4, has a primary winding 1% and functions to convert a clock or timing pulse supplied via input terminals M199 and ill connected to said primary winding, into a suitable signal for driving the gate circuit $6 in a state of equilibrium. The gate circuit 86, the loop connected to its outputs, and the transformer Mid comprise a sampling circuit M2.

input terminals llS, lid and ll of the pulse-shaping circuits d3, lid and 85 respectively, of F IG. 3, are utilized for the supply of clock or timing pulses. The clock pulses are utilized to perform the sampling and pulse holding or storing operations. An analogue delay circuit l M is connected between the PCM output terminals 79 and 81 of the unit circuits 71 and 72 via leads M7 and 118. An analogue delay circuit 119 is connected between the PCM output terminal 81 of the unit circuit 72 and the FCM output terminal of the next-succeeding third unit circuit (not shown in FIG. 3) via leads 12E and 1122. An analogue delay circuit U3 is connected between the PCM output terminal of the eighth unit circuit (not shown in FIG. 3), and the PCM output terminal of the unit circuit 73 via leads i2 and E25. The analogue delay circuits 116, M9, 123, and the like, function to provide a required time delay to the PCM output signals of the unit circuits or stages in transmitting the PCM signals in series. The PCM output signals are provided at a PCM output terminal 126.

The unit circuit 71 functions to detect the polarity or sign of the PAM input pulse or signal supplied to the input terminal 74. This is accomplished in the manner described with reference to FIG. 2. The PCM output signal, which is the first bit of the code output, is provided at the PCM output terminal 75 Simultaneously, the input pulse is full-wave rectified and a suitable bias is added to said input pulse. The resultant pulse is then phase-inverted and amplified by an amplification of 2 to provide the output signal at the output terminal 75. Generally, the PAM input pulse is a substantially ideal square pulse. However, due to the fact that the frequency characteristic of the unit circuit is finite, and due to the fact that the full-wave rectifier is a nonlinear circuit, there is distortion or deterioration in the rising or increasing and falling or decreasing parts or the output pulse waveform during operations by the unit circuit. Consequently, the output pulse is not a square pulse. These distortions increase quantized noises in the next-succeeding stages, so that, in order to minimize the adverse effect created thereby, the output pulse is supplied to the pulse-shaping circuit 33 via the output terminal '75.

The pulse-shaping circuit S3 functions to shape the pulse provided at the output terminal 75 into a substantially ideal rectangular pulse by a sampling operation. When the magnitude of the voltage or current of the output pulse of the unit circuit '71., provided at the output terminal 75, has sufficiently approached an ideal level, such voltage or current is sampled and is then held or stored for a required period of time. The instant of sampling in the sampling circuit M2 (FlG. i) is determined by the clock pulse supplied to the input terminals W9 and ill. The shaped pulse is supplied to the next-succeeding unit circuit 72 (FIG. 3), which functions in the same manner as the unit circuit 71. The operation is then repeated in each succeeding pulse-shaping circuit and unit circuit.

The pulse or signal is finally supplied to the unit circuit 73 where the ninth bit of die code is provided, so that 9-bit coding is thereby completed. During the operation of the cascaded coder of HG. 3, from the supply of the PAM input pulse to the input terminal 74, until the provision of the pulse at the input terminal 753 0? the ninth unit circuit 73), the delay of the pulse in each stage or unit circuit is the sum of the time delay provided by such stage or unit circuit and the period of time from the instant of increase or rise of the pulse in the pulse shaping circuit to the instant of sampling. Thus, if the time delay of the delay circuits llld, ill, B23, and the like, is selected to be slightly less than the delay time of the pulse in each of the stages or unit circuits, a code output may be provided at the output terminal 126 which is a series of PCM signals arranged in time from the digit of highest degree to the digit of lowest degree.

FlGS. 5A to 5D disclose the waveforms appearing in the cascaded coder of FlG. 3, said cascaded coder comprising, for example, a reflected binary coder. FlG. 5A illustrates the waveform of the input pulses supplied at the input terminals 74, 76, 78, and so on, of MG. 3. The unit circuit ofa reflected binary system provides full-wave rectification, adds a bias voltage to the input signal and doubles the amplitude of the signal by amplification. Thus, when the input signal has the waveform shown in F lG. 5A, the output signal provided by the unit circuit is that shown in FlG. 5B. in each of FlGS. 5A to 5D, the ordinate represents the amplitude. The maximum amplitude is :Vm. in each of H615. 5A to 5D, the broken line abscissa indicates zero voltage and each of the curves illustrated in solid lines indicates the actual response waveform provided relative to the frequency characteristic of the amplifier.

FIG. 5C shows sampling pulses provided by sampling the instant at which the waveforms illustrated in H6. 53 have satisfactorily settled within the allowable error range. FIG. 5D illustrates the pulses provided by holding or storing the pulses of FIG. 5C for a determined pulse length. The pulses of FIG. 5D are supplied to the next-succeeding unit circuit or stage. Each unit circuit then functions in the manner indicated by FlGS. 5A to 5D.

A comparison of the phase of the curve of FIG. 5A and that of the curve of FIG. 5D indicates that a phase delay which is almost equal to the pulse length is provided by the pulse-shaping circuit. Thus, the bit pulses provided by the unit circuits 71, 72, 73, and so on, of FIG. 3, have similar phase delays and, therefore, delay components or delay circuits 116, i119, i235, and so one, are connected between the unit circuits so that the phase delays of the bit pulses maybe corrected and the PCM outputs of said unit circuits may be provided at the correct time intervals.

As hereinbefore described, in accordance with out invention, the setting time of each unit circuit or stage is always shorter than it would be if there were no pulse-shaping circuit. it is therefore unnecessary that the pulse width of the input pulse supplied to the coder be longer than the sum of setting time of the first stage and a time period required for the sampling of the input signal. The sampling may be accomplished in a very period of time. Higher speed coding may be provided in a cascaded coder by providing shorter pulse lengths. The cascaded coder of the present invention may thus function at higher speeds than known coders in which unit circuits, as illustrated in FIGS. 1 and 2, are merely directly connected to each other in cascade.

Higher speeds of coding may be provided by the coder of the present invention when a greater number of bits in involved, rather than a smaller number of bits. Furthermore, the pulse-shaping circuits of our invention may be connected either between every adjacent pair of unit circuits, between every other adjacent pair of unit circuits, or between selected adjacent pairs of unit circuits. The principle of the present invention may be applied to multinary coders, as well as to binary coders. If the sampling by the pulse shaping circuits is ideal in a reflected binary coder of nine bits, the speed of coding may be almost doubled by the present invention.

The speed of coding may be even further increased, in accordance with out invention. In a cascaded coder, utilizing sampling circuits connected between adjacent unit circuits, as in the present invention, the input voltage or current supplied to a specific unit circuit or stage is determined only by the magnitude of the output voltage or current from the nextpreceding unit circuit or stage at the instant of sampling. Coding may therefore be accomplished only if the magnitude at the instant of sampling is sufficiently close to the ideal mag nitude at the instant of sampling is sufficiently close to the ideal magnitude at the instant of sampling is sufficiently close to the ideal magnitude or value even if the magnitudes at other instants are shifted from the ideal magnitude. Therefore, when the frequency band of the amplifier is constant, higher speed coding may be provided by causing the pulse response waveform of the amplifier to reach the ideal magnitude sooner or earlier. The coding speed is not related to the waveform after the ideal value or magnitude has been reached. In accordance with the present invention, therefore, high speed coding is provided by providing a transient response characteristic of the amplifier which permits the response waveform of the amplifier to reach the ideal level sooner in each unit circuit of the cascaded coder.

The characteristic of an amplifier in a unit circuit or stage of the cascaded coder may be slightly varied by circuits connected to the two sides of such amplifier. The transient response characteristic of the amplifier, however, is regulated principally by the structure of the amplifier. Various types of amplifying components, such as semiconductor amplifiers, transistors, vacuum tubes, and the like, may be utilized as the amplifier. However, the gain or amplification factor decreases at high frequencies. In other words, there is a limitation of the frequency bandwidths imposed upon the amplifying component. The increasing or rising of the characteristic thus requires a finite period of time in amplifying the sampled pulse.

It may be assumed, for illustrative purposes, that the amplification factor or degree of amplification of a transistor amplifier at high frequencies is caused by alpha cutoff. The amplification factor may also be caused by other factors, but the following principle applies in all cases. The degree of amplification or the amplification factor may be expressed as wherein k is a positive real constant having a selected value of about 2, f is the alpha cutoff frequency, and S is the operator or the frequency parameter.

The response characteristic of the output of the amplifier is illustrated in FIG. 6. In .FIG. 6, a step function S(t) is applied during the time period to the input of the amplifier. The unit step function is S(t) and the height or distance of the step is a.

As indicated by Equation (1) and by the curve of FIG. 6, the transient response of the amplifier relative to the step function An infinite period of time is .thus required to theoretically approach the stationary level, magnitude or value. Actually,

however, the stationary level, magnitude or value. Actually, however, the stationary level may be approached within a finite period of time as an approximate level and may be utilized practically. For this purpose, a first order lag system of known type may be utilized as an example. In such a case, k equals the number 2 in Equation (1).

The period of time tt required for the level of response of the step to reach a level shifted from the ideal level by l percent may be expressed as wherein, as is evident from Equation (l),fo is the frequency at which the gain of the amplifier is decreased by 3 db. If the frequency f0 is megahertz or megacycles per second, tr is equal to 0.735Xl0 in accordance with Equation (3). This indicates that a time period of 7.35 nanoseconds is required. As illustrated by the foregoing example, a transistor having an alpha cutoff frequency of 1000 megahertz or megacycles per second is required in order to provide an amplifier having a delay of 0.735 nanosecond, within an allowed error range of 1 percent. A time delay is therefore provided, and a coding speed limitation is accordingly imposed.

In accordance with our invention, the limitation to the coding speed is removed, and said speed is accordingly increased. In accordance with one embodiment of our invention, the amplification degree k at low frequencies is given a magnitude which is slightly greater than 2. A suitable amplification degree k is thus, for example, equal to 2.02. The ideal level may then be substantially reached by utilization of the value of tr of Equation (3). The approximate value of 1 percent may be reached within a period of time of If f0 is 100 megahertz or megacycles per second, n=6.2 l0 so that the required period of time is 6.2 nanoseconds. The speed of coding may thus be increased by about 20 percent relative to known coders. If the value of k is still greater than 2, the speed of coding may be still further increased. Generally, the product of the gain and the frequency bandwidth is almost constant in an amplifier. Thus, if

K=27rfok (5) Equation (2) may then be expressed as K k 1. 6 T t Then Iffo=l00 megahertz, k=2 and F001 in Equation (8), t2 is 1.6 nanoseconds.

In another embodiment of our invention, the transient response characteristic relative to the unit step of the amplifier is expressed by the waveforms of FIGS. 7A to 7D. In each of FIGS. 7A to 7D, the abscissa represents time, as in FIGS. 5A to 5D. The ordinate of each of FIGS. 7A to 7D indicates voltage or current. The crossover of the ordinate and abscissa axes in each of FIGS. 7A to 7D is the point of zero voltage or current or zero time. In each of FIGS. 7A to 7D, the broken lines indicate the ideal waveforms provided when the input unit step voltage or current to the amplifier is ideally amplified, and the slot line curves indicate the output response waveforms provided by the present invention.

As is well known, the curve of FIG. 7A illustrates the waveform of the characteristic provided by peaking of the amplifier, and the curve of FIG. 7B is similar to that of FIG. 7A, with the exception that in FIG. 7B, the slope of the waveform at the point of intersection with the ideal level is zero or close to zero. In FIG. 7A, the voltage or current is an exponentially attenuated periodic oscillation, so that time slots t3 to :4, :4 to :5, 25 to 16, and so on, are equal to each other. The time slot from the increasing or rising point of the unit step to the first point of intersection with the ideal level, that is, the time slot of zero to t3, is, however, generally different from the remaining time slots.

FIG. 8 is the equivalent circuit of the amplifier utilized in the aforedescribed first order lag system. In FIG. 8, a current source 131 is indicated when the signal is ideally amplified. A load resistor 132 is connected across the current source 131. The load resistor 132 is the load of the amplifier. A stray capacitance 133 of the load is indicated as being in shunt with the load resistor 132. An output signal voltage is provided at an output terminal 134.

In FIG. 9, which is a modification of FIG. 8, a current source 131', a load resistor 132, a stray capacitance 133 and an output terminal 134 are connected in the same manner as the corresponding components of FIG. 8. In FIG. 9, however, a peaking inductance 135 is connected in series with the load resistor 132'. The series connection of the load resistor 132' and the peaking inductance 135 is connected across the current source 131'; the stray capacitance 133' being shunted across said series connection.

The response waveform provided at the output terminal 134 of FIG. 9, when a unit step is provided as the current source 131, is shown in FIG. 7A. It should be noted, however, that, as is well known, the values of the components of FIG. 9 must be related to each other he the relation in order for the aforedescribed oscillatory characteristic to appear. In the foregoing relationship, L135 is the inductance of the peaking inductance 135, R132 is the resistance of the load resistor 132', and C133 is the capacitance of the stray capacitance 133'.

The gain or amplification degree or factor of the circuit of FIG. 9 at high frequencies is grater than that of the circuit of FIG. 8. Furthermore, the circuits of FIGS. 8 and 9 are identical, except for the addition of the peaking inductance 135 to thei'circuit of FIG. 9. An oscillatory response characteristic as shown in FIG. 7A is thus provided, and as is well known, the increasing or rising of the characteristic may always be improved. It may be assumed that the resistance value of the load resistor 132 is 1 kilohm and that the capacitance value of the stray capacitance 133 is 10 micromicrofarads, in FIG. 8, the time constant being 1- nanoseconds. When a known amplifier of a first order lag system is utilized in the unit circuits, the precision or accuracy required for reflected binary coding of nine bits may be provided at the sample point spaced from the increasing or rising point of the unit step wave by 90 or 100 nanoseconds. On the other hand, when the inducting valve of the peaking inductance 135 of FIG. 9 is 5 microhenries, the time slots from the increasing points of the unit step waves corresponding to 13 and 14 of FIG. 7A are 16.9 nanoseconds and 47.7 nanoseconds, respectively. This means that the necessary accuracy may be achieved considerably sooner than in a first order lag system and coding of higher speed may be realized. It is therefore necessary to sample the response wave at the instant corresponding to t3 or [4 of FIG. 7A.

In the aforedescribed embodiments of the present invention, it is practically impossible to accomplish sampling with pulses having an infinitesimal pulse length, and without jitter. It is thus inevitable that a small error arise even if the response waveform approximates the ideal level. In high speed coding, in general, the pulse length of the sampling pulse and the jitter thus cannot be neglected. For this reason, quantized noise increases. This may be avoided by providing a response waveform which is tangent with the ideal level at the point of intersection with said ideal level, as shown in FIGS. 78 and 7C. The response waveform of FIG. 7B and that of FIG. 7C differ from the waveform of FIG. 7A only in amplitude, so

that, as indicated by said FIG., the period of time required for the response maybe shortened and the increase of the quantized noise due to jitter may be avoided. In FIG. 7B, the point of intersection of the response waveform and the ideal level occurs at t7. In FIG. 7C, such point of intersection occurs at t8. In FIG. 7D, the time slots extend from t9, to I10, t10 to 211, and tll to I12.

A response characteristic as shown in FIG. 7D may be provided by the use of additional circuitry. The transfer function of the equivalent circuit of the amplifier for providing the response characteristic of FIG. 7D must utilize a plurality of complex poles, as indicated in FIG. 10, which is a modification of the circuit of FIG. 9. A load resistor 132" is connected in series with a peaking inductance across a current source 131" in the same manner as in FIG. 9. A stray capacitance 133" is connected across the series connection of the load resistor 132" and the peaking inductance 135 in the same manner as in FIG. 9. In FIG. 10, however, a second load resistor 141 is connected in series with a second peaking inductance 142 and a second stray capacitance 143. A third load resistor 144 is connected in shunt across the stray capacitance 143. The series connection of the second load resistance 141, the second peaking inductance 142 and the second stray capacitance 143 is connected in parallel with the series connection of the load resistor 132" and the peaking inductance 135', as well as with the stray capacitance 133".

The characteristic feature of the amplifier circuit for realizing a response characteristic of the aforedescribed type may be determined from the frequency characteristic of the amplitude. FIGS. 11A, 11B and 11C disclose the frequency characteristic of the circuit of FIG. 10 and therefore illustrate the aforementioned point. In FIGS. 11A to 11C, the abscissa represents the frequency f and the ordinate represents the amplitude. It is necessary that peaks be provided at frequencies f0, 3fo, Sfo and so on, or at frequencies f0 2f0, 3f0, and so on, in the frequency characteristic in order that oscillatory response characteristics be provided.

FIGS. 12A and 12B illustrate the relation between the pulse width length of the PAM pulse required when the response characteristic of this type is achieved. FIG. 12A illustrates part of the PAM input waveform and FIG. 12B illustrates part of a response output waveform. In FIGS. 12A and 123, the abscissa represents time and the ordinate represents voltage or current. In FIG. 12A, a rectangular PAM pulse is the sum of the step waves indicated by broken lines in FIG. 12B. The response waveform, relative to the PAM pulse may thus be indicated as the sum of the response waves indicated by the slot line curves of FIG. 128 relative to the step waves of FIG. 128.

In FIG. 12B, 113, r14, r15, r16, r17, t18 indicate the points of intersection of the response wave of the amplifier of FIGS.

8, 9 or 10 with the ideal level. At the points M3 to :18, the preceding response waves are equal to the ideal level, so that the actual response wave, which is the sum thereof, is also equal to the ideal level, and the object may be achieved by performing sampling at such points. The sample points in FIG. 12A are r19, r20, :21, and so on. These sample points correspond to the point t4 of FIG. 7A, which is the second point of intersection with the ideal level. In this case, a single fundamental period of the oscillation of the response wave is required as the pulse length of the PAM input pulse. If the first point of intersection of the ideal level is selected as the sample point, however, the pulse length of the PAM input pulse may be one-half period. Approximately 63 nanoseconds is required as the pulse length of the PAM pulse in the example illustrated by FIGS. 12A and 12B. Approximately 32 nanoseconds is lll required when the first point of intersection is selected as the sample point. The speed of coding when the first point of intersection is selected as the sample point, is about three times as high as that of an amplifier of the first order lag system.

As aforedescribed, in accordance with our invention, coding of very high speed may be attained by properly designing the amplifiers. In order to provide high speed in the aforedescribed embodiment, however, the amplifier must be so designed that level parts or peaks are formed in the waveform, as shown in FIGS. 11A, 11B and 11C. A slight error is inevitably produced if the only operation is to increase the degree of amplification of the amplifier. Such an error may be eliminated in accordance with other embodiments of the present invention, as hereinafter described. Thus, the amplification degree k at low frequencies may be made slightly larger than the required amplification degree K. Furthermore, the input pulse may be applied as the resultant or combination of the original pulse and a pulse provided by attenuating and delaying the original pulse. This is illustrated in FIGS. 13A and In each of FIGS. 13A to 13B, the abscissa represents time and the ordinate represents voltage or current. In FIG. 13A, the curve of FIG. 13A is the input pulse of an amplifier. The pulse is actually a rectangular wave, but a step pulse is shown in FIG. 13A in order to facilitate the explanation of the principle of the invention. The positive step pulse arising at the origin of zero time and voltage or current is the original pulse and has an amplitude A. A negative pulse having an amplitude B, arising at a time r22 may be provided by attenuating the original pulse, inverting the phase and delaying said pulse by a period of time from zero to r22.

FIG. 13B iiTJsYFiis' the response waveform of the amplifier.

When the pulse of FIG. 13A is ideally amplified at zero time, the waveform represented by the broken line of FIG. 13B is provided, and the response waveform is shown by the slot line curve. Since the degree of amplification or gain, is greater than K, the ideal response waveform indicated by the broken line of FIG. 13B initially is greater than KA. The ideal response waveform is, however, decreased by KB at the time r22 due to the response of the negative pulse applied to the input terminal. The operation is adjusted so that the required amplitude KA is provided at precisely the time t22. On the other hand, the actual response of the amplifier is KA exactly at the time t22 where it is settled and becomes smooth or level.

7B A -2 ;ft 2 2 and AK may be expressed as B, I 1 B K 13 Then the first term of Equation (1 1) becomes KA and the second tenn thereof becomes zero. In other words, in accordance with Equations (12) and (13) the response waveform becomes level or smooth at an amplitude of KA after the time I22, as shown in FIG. 13B.

Whenfo is 100 megahertz, K is 2 and AKis 0.2, B is equal to A and I22 equals 3.68X second. This is equal to about half the actual values, with an allowable error of 1 percent when the aforedescribed operation is not followed. The time 222 may be shortened even more by increasing AK. Furthermore, since the response may be made completely level or smooth after the ideal level has been reached, there is no adverse effect of the jitter of the sampling pulse.

A similar effect may be provided by another embodiment of the present invention. In accordance with such embodiment, peaking is effected by connecting an inductance to the load of the amplifier. Furthermore, as in the aforedescribed embodiment, the input pulse is applied as the resultant or combination of the initial pulse and a pulse provided by attenuating and delaying the initial pulse. The output voltage of a transistor amplifier which includes an inductance connected in series with a load resistance may be calculated by using the equivalent circuit of FIG. 9. In FIG. 9, the resistor 132' is the load resistance, the capacitor 133' is the stray capacitance such as, for example, the collector capacity of the transistor and the stray capacity of the circuit, and the inductor is the beginning inductance, as hereinbefore described.

FIGS. 14A, 14B and 14C illustrate the response waveforms. In each of FIGS. 14A to 14C, the abscissa represents time and the ordinate represents voltage or current. FIG. 14A, which is equivalent to FIG. 7A, illustrates the response waveform provided at the output terminal 134 of FIG. 9 when a unit step is provided at the current source 131 of FIG. 9. As hereinbefore described, the values of the components of FIG. 9 must come within the relation in order to provide the aforedescribed oscillatory characteristic. The circuit of FIG. 9 may provide increased gain at high frequencies compared to a circuit without a peaking inductance, where no peaking is effected. Therefore, an oscillatory response of the type illustrated in FIG. 14A may be provided and, as known, the increase or rise may always be improved.

When a circuit of the aforedescribed type is utilized as the amplifier, and the initial pulse has an amplitude A at zero time, as shown in FIG. 14B, and a pulse having an amplitude B arises at a point delayed from zero time by a time interval zero to t22, is combined with the initial pulse to provide the input pulse, the response waveform reaches the ideal level at the time :22. The response waveform reaches the ideal level at the time r22 under a specific condition, as shown in FIG. 14C. After the time :22, the oscillation component is removed from the response waveform and said response waveform is level or smooth. This may be explained theoretically by expressing the amplification degree k of the amplifier at low frequencies as k+K=AK, as in the aforementioned embodiment. Again, K is the required amplification degree.

The response in the time period from zero to 122 which may be provided only in relation to the pulse amplitude A is A (K+A) [1+e" (Csin bt-cos bt)] (14) The response to the pulse of amplitude B applied at the time t22 is B(K+AK) [l +e""' (C sin b[tr22lcos b[t-z22l)] wherein +Be [cos bt22 (C sin bt-cos bt) sin bt22 (C cos bt-lsin bt)}] (16).

Since bt22 =1:- (17) B A+B 19) These values may be utilized in Equation 16). Equation 16) is then equal to KA, thereby indicating that the response is level or smooth at the ideal level after the time r22. This embodiment thus provides the same results as the foregoing embodiment by providing a response characteristic which is such that the ideal level may be reached sooner and by eliminating the influence of sampling jitter.

FIG. 15 is an amplifier circuit of our invention which provides the advantages of FIGS. 11A to 11C, 12A, 12B, 13A, 13B and 14A to 14C, as aforedescribed. In FIG. 15 an amplifier 151 has an input terminal 152 connected to its input via a lead 153 and an output terminal 154 connected to its output by a lead 155. A delay line 156 is connected to the input terminal 152 via the lead 153 and a lead 157. The delay line 156 provides a suitable delay time. The delay line 156 is connected to ground via a terminating resistor 158. The lead 153 adjacent the input of the amplifier 151 is connected to ground via a matched resistor 159.

In the first discussed embodiment of the present invention, a known type amplifier of a first order lag system is utilized as the amplifier 151 and the input pulse is applied to such amplifier and to the delay line 156 simultaneously. The input pulse supplied to the delay line 156 is reflected by the terminating resistor 158 and is returned to the input terminal 152. At such time, the input terminal 152 is matched to the characteristic impedance of the delay line by the matched resistor 159. Therefore, the pulse is not reflected again and a pulse, delayed by the period of time required for passing through the delay line and then returning through said delay line, is applied to the amplifier 151. The amplitude of the pulse reflected at the terminating resistor 158 of the delay line 156 may be varied by variation of the resistance value of said terminating resistor. However, as is known, the relation between the resistance value of the terminating resistor 158 and the amplitude of the pulse, as shown in FIG. 13A, is

12 R158 R159 A R158+R159 (20) wherein R158 is the resistor value of the terminating resistance 158 and R159 is the resistor value of the matched resistance 159 or the characteristic impedance of the delay line 156.

RM may be varied from -lto by providing a resistance value of the terminating resistor 158 within a range from 0 to the characteristic impedance of the delay line. The circuit of FIG. 15 may thus be readily provided. When an axial cable is utilized as the delay line 156, a delay time of about nanoseconds is provided by a 1 meter length of said cable, so that the required length to said delay line is determined by the required delay time. The length of the delay line may be onehalf the length of a delay line in a known embodiment. A delay 'line 156 comprising an axial cable having a length of approximately 185 centimeters provides a time :22 which is equal to 3.68X109 second, as hereinbefore mentioned.

When the amplifier circuit of FIG. is to be utilized as the next embodiment of the present invention, the amplifier 151 must comprise an amplifier which provides peaks. The resistance value of the terminating resistance 155 must be greater than the matched resistor 159 or the characteristic impedance of the delay line 156, since the pulse reflected by the delay line is an attenuated positive pulse. In other respects, the first and second embodiments may be the same, provided that the amplification degree of the amplifier 151 in each embodiment must be determined to provide a response which is level or smooth after a determined point.

As hereinbefore described, our invention permits the ideal level to be reached considerably sooner than in amplifiers and provides a response which is level or smooth after reaching the ideal level. This is accomplished by a suitable design of the amplifiers in the unit circuits of the cascaded coder to provide the desired response characteristic and by delaying and com- LII bining pulses under suitable conditions at the input of the amplifier. The cascaded coder of the present invention thus functions with improved precision or accuracy and high speed.

Although an alternating binary system has been described, the present invention may be readily utilized in a normal binary system, a reflected binary system, and a multinary system having an arbitrary base. F urtherrnore, although pulse-shaping circuits are illustrated as being connected between each pair of adjacent unit circuits (FIG. 3), said pulse-shaping circuits need not be included between each pair of adjacent unit circuits. The attenuated and delayed pulse which is combined with the initial input signal pulse may be provided from another pulse source.

While the invention has been described by means of specific examples and in specific embodiments, we do not wish to be limited thereto, for obvious modifications will occur to those skilled in the art without departing from the spirit and scope of thsisyqmi n- We claim:

1. A cascaded coder for a pulse modulation system, said coder comprising:

a plurality of pulse converting circuits;

input means for supplying analogue input pulses to the first of said pulse converting circuits; plurality of analogue delay circuits each connected in parallel between corresponding adjacent ones of said pulse converting circuits;

a plurality of pulse-shaping circuits each coupled between adjacent corresponding ones of said pulse-converting circuits, each of said pulse-shaping circuits comprising a sampling circuit, an input for supplying an input signal to said sampling circuit, a holding circuit connected to said sampling circuit and an output connected to said holding circuit; and

output means for deriving PCM output signals from the last of said pulse converting circuits.

2. A cascaded coder as claimed in claim 1, wherein each of said pulse converting circuits comprises comparator means, delay means, input means for supplying an input signal to said comparator means and said delay means, adder means connected to said delay means, bias voltage means, switch means operated by said comparator means interconnecting said bias voltage means to said adder means for applying bias voltage to said adder means in accordance with a result provided by said comparator means and amplifier means connected to said adder means.

3. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits comprises comparator means, rectifier means, input means for supplying an input signal to said comparator means and said rectifier means, adder means connected to said rectifier means, bias voltage means connected to said adder means and amplifier means connected to said adder means.

4. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes amplifier means having a transient response characteristic which provides the required value in a short period of time.

5. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes amplifier means having a transient response characteristic which provides the required value in a short period of time, said amplifier means having a low frequency amplification factor which is larger than the required amplification factor.

6. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes amplifier means having a transient response characteristic which provides the required value in a short period'of-time, said amplifier means having a high frequency amplification factor which is the turnover value of the amplification factor.

7. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes delay means for an input signal, adder means connected to said delay means for adding a signal to the input signal and amplifier means connected to said adder means, said amplifier means having a transient response characteristic which provides the required value in a short period of time relative to the added signals thereby providing a level response characteristic.

8. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes amplifier means having an input, delay means and attenuating means connected to said input and means for applying to the input of said amplifier an initial pulse plus a delayed and attenuated initial pulse.

9. A cascaded coder as claimed in claim 1, wherein each of said pulse-converting circuits includes delay means for an input signal, adder means connected to said delay means for adding a signal to the input signal and amplifier means connected to said a'dder means, said amplifier means having a transient response characteristic which provides the required value in a short period of time relative to the added signals thereby providing a level response characteristic and said amplifier means comprising circuit means for attaining the required level in a brief period of time relative to the combined pulses and providing a level response characteristic.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3 571 757 Dated March 23 I 9 Z Inventor(s) Zeniti yasu et a1 It is certified that error appears ii! the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In heading to printed specification Assignee should read Fujitsu Limited Signed and sealed this 21;.th day of August 1971.

(SEAL) Attest:

EWARD M.F'LETGHER,J'R. WILLIAM E. scHUrLER, Attesting Officer Commissioner of Patents

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Referenced by
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US6560283 *Jul 20, 1998May 6, 2003British Broadcasting CorporationRe-encoding decoded signals
US7375664 *Jun 7, 2006May 20, 2008Texas Instruments IncorporatedSystems and methods for providing anti-aliasing in a sample-and-hold circuit