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Publication numberUS3579207 A
Publication typeGrant
Publication dateMay 18, 1971
Filing dateNov 14, 1967
Priority dateNov 14, 1967
Publication numberUS 3579207 A, US 3579207A, US-A-3579207, US3579207 A, US3579207A
InventorsBartlett Peter G, Meschi Joseph E
Original AssigneeGulf & Western Industries
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Load sequencer controller
US 3579207 A
Abstract  available in
Images(3)
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Claims  available in
Description  (OCR text may contain errors)

United States Patent [72] Inventors Peter G. Bartlett 340/40 Bettendorf, Iowa; 3,375,494 3/1968 Piening etal. 340/40 Joseph Mesch" Lyons Primary Examiner-Terrell W. Fears [211 App]. No. 682,814 A M Tlb d Bod 221 Filed Nov. 14, 1967 omey 1 my Y [45] Patented May 18, 1971 [73] Ass'gnee i lndusmes ABSTRACT: A load sequencer controller is disclosed herein W or which serves to sequentially allocate and time a plurality of load intervals. The controller includes a plurality of interval 54 I LOAD SEQUENCER CONTROLLER time storage memories, each corresponding with an associated 31 Claims, 4 Drawing Figs load interval to be timed. Each of the memories includes a pluwhy of electrically alterable and interrogatable bistable U.S. 173.2, memory means serve to store information. The 340/ 35 weighted binary content of each memory is a decimal number [5]] [lit-Cl Gllc 11/22 representative of a desired time duration for an agsgcialed 0f load intervaL An interrogation circuit serves to sequentially 173.2, (AM), 174 (CM), 35, 37, 40 41 apply interrogation signals to the memories so that when any (lnqulred),92/29 92/35, 92/50, 92/12, 146-2, one memory is interrogated the output of that memory pro- 3091, 343 vides a pattern of binary signals. An actuating circuit receives pulses from a source of equi-time-spaced pulses and serves to [56] References and actuate the interrogation circuit each time the decimal UNITED STATES PATENTS number of the received pulses is equal to the decimal weight 3,300,775 1/ I967 Dowling 340/41X of the pattern of binary signals of the memory last inter- 3,302,170 1/1967 Jensen et al. 340/40x rogated.

/C BINARY RES ETj S C O U N T E R 30 6 32 a i-b r-c d l- A BINARY 80 g N +60 S HAPER COM PARATOR I RI I l i i I i l FFI FF2IFl"-'3 FF4 RESET 3 n T I Is 5 INTERVAL TIME 9 E, E STORAGE CERAMIC A MEMORY MATRIX A2 1 A A4 INTERVAL J Oio I 2 TIME 0 o 'l I SEQUENCER wR ITE I TW CIRC TM3J INTERROGATOR U T o o I I 3,305,828 2/1967 Auer,.lr.etal.

PATENIEU MAY is [an SHEET 2 OF 3 M W mam B. Y HWJIS RE m} MM 56. mt H 7 03) 56 BE; U% M PJ 5 5E3 m?) 56 NEE; m 6E 56 NE; {N3 .56 mEEs m; b6 BE;

ATTORNEYS LOAD SEQUENCER CONTROLLER This invention relates to the art of electrical controls and, more particularly, to electrical controls for sequentially allocating and timing a plurality of load intervals.

The invention is particularly applicable to the art of traffic control and will be described with particular reference thereto; although, it is to be appreciated that the invention has broader applications, such as in process control or other control arts, wherein means are required to sequentially allocate and time a plurality of load intervals.

In the past, load intervals have been sequentially allocated and timed with the use of an electromechanical step switch mechanism, using break away cams to control the load sequencing program. Such electromechanical mechanisms are inherently slow in operation, and any program change requires the breaking away of a new set of cams. The reliability and flexibility of such an electromechanical mechanism is limited due to the use of mechanical moving parts.

In more recent years, electronic trafi'rc controllers have included ring counter and ring timer circuits for sequentially allocating various traffic intervals in a cyclical fashion. Such circuits, however, have usually incorporated RC timers for timing the durations of the various traffic intervals. These timers are analog and, hence, the timings may become inaccurate due to variations in values of the circuit components upon temperature changes of the surrounding environments. Also, these circuits are not readily adjustable to provide for interval program changes or interval timing changes.

The present invention is directed toward a load sequence controller which sequentially allocates and times a plurality of load intervals without the use of electromechanical mechanisms and the like, and wherein readily adjustment may be made of the interval timing and/or interval program.

In accordance with one aspect of the present invention, the apparatus for sequentially allocating and timing a plurality of load intervals include a plurality of interval time storage memories, each corresponding with an associated load interval to be timed, and wherein each memory includes a plurality of electrically alterable and electrically interrogatable bistable memory means, such as ferroelectric capacitor storage means, each storing a binary l or binary signal so that the weighted binary content of a memory is a decimal number representative of a desired time duration for an associated load interval. Each of the memory means has an input for receiving an interrogation signal and an output for carrying a binary signal in response to receipt of an interrogation signal. An interrogation means serves to sequentially apply interrogation signals to the plurality of memories so that when any one memory is interrogated the outputs of its plurality of memory means provide a pattern of binary signals. Also, an actuating means receives pulses from a source of equi-time-spaced pulses for actuating the interrogating means to interrogate the next succeeding of theplurality of memories when the decimal number of the pulsesreceived is equal to the decimal weight of the pattern of binary signals on the outputs of the memory means of the memory last interrogated.

In accordance with a more limited aspect of the present invention, there is also provided a plurality of interval program storage memories each corresponding with an associated load interval to be allocated, and wherein each of the memories correspond in structure with the memories in the interval time storage memories.

In accordance with another aspect of the present invention, there is provided a new traffic controller which serves to sequentially allocate and time a plurality of traffic intervals to be displayed by traffic signal light means and wherein the traftic controller comprises a plurality of trafi'ic interval time storage memories, one each for each of the traffic intervals to be allocated and timed. Each of the trafiic interval time storage memories includes a plurality of the above described electrically alterable and electrically interrogatable bistable memory means.

The primary object of the present invention is to provide an improved solid state load sequence controller which is relatively inexpensive to manufacture and is relatively economical to operate.

Another primary object of the present invention is to provide an improved solid state load sequence controller which is relatively inexpensive to manufacture and is relatively economical to operate.

Another object of the present invention is to provide a load sequence controller having electrically alterable and electrically interrogatable interval time storage memories and/or interval program storage memories.

Another object of the present invention is to provide a load sequence controller having interval time and interval program storage memories which incorporate ferroelectric storage capacitors.

A still further object of the invention is to provide an improved trafiic controller for sequentially allocating and timing trafiic intervals, wherein the interval timings and/or programs are electrically alterable and interrogatable.

A still further object of the present invention is to provide an improved trafiic controller incorporating ferroelectric capacitor storage elements.

These and other objects and advantages of the invention will become apparent from the following description of the preferred embodiments of the invention as read in connection with the accompanying drawings, in which: I

FIG. 1 is a combined schematic-block diagram illustration of one embodiment of the invention;

FIG. 2 is a schematic illustration of a ceramic memory single bit device;

FIG. 3 is a schematic illustration of a ceramic memory matrix; and,

FIG. 4 is a combined schematic-block diagram illustration of a second embodiment of the invention.

Referring now to the drawings, wherein the showings are for purposes of illustrating the preferred embodiments of the invention, and not for purposes of limiting same, FIG. 1 illus trates one embodiment of the invention in the form of a variable time, fixed program, two phase traffic controller. This controller serves to sequentially allocate and time main street go and caution intervals and cross street go and caution intervals. the controller generally comprises: a pulse source S of equitime-spaced pulses; a binary counter C; a binary comparator BC; a sequencer-interrogator I; an interval time storage memory matrix TM, having four word line memories TM], TM2, TM3 and TM4; a time write circuit TW; and, a load'control circuit LC.

CERAMIC MEMORY DEVICE The ceramic memory matrix TM preferably takes the form as illustrated in out copending application, Ser. No. 640,717, filed May 23, I967, and assigned to the same assignee as the present invention, and which application is herein incorporated by reference to Pat. No. 3,401 ,377 issued on said application. As disclosed in said patent, the matrix utilizes bistable memory means of the nondestructive readout, dual plate type comprising an easily polarized memory plate and a permanently polarized drive plate having facing surfaces which are secured to each other. The ceramic memory matrix disclosed there incorporates several word lines each having several bits. An understanding of the matrix may be best understood by first considering the construction of a single bit ceramic memory device. A single bit ceramic memory device 10 is shown in FIG. 2, and generally comprises a memory plate 12 constructed of ferroelectric material, such as barium titanate, Rochelle salt, lead metaniobate or lead titanate zirconate composition, for example. In its preferred form, however, memory plate 12 is constructed of lead titanate zirconate composition since it is easy to polarize. Drive plate 14 is preferably constructed of ferroelectric material having piezoelectric characteristics, such as lead titanate zirconate composition. However, the drive plate may be constructed of any material that will change its dimensions upon application of an electrical signal, such as, for example, magnetostrictive material, which upon application of current thereto will undergo physical dimension changes. Drive plate 14 is permanently polarized and need not be constructed of easily polarizable material, such as lead titanate zirconate composition.

Plates l2 and 14 are, in their unstressed condition, approximately flat, and are oriented so as to be in substantial superimposed parallel relationship. The upper surface of plate 12 is coated with an electrically conductive layer 16, and the lower surface of plate 14 is coated with an electrically conductive layer 18. Layers l6 and 18 may be of any suitable electrically conductive material, such as silver. lnterposed between facing surfaces of plates 12 and 14 there is provided a third layer 20 of electrically conductive material. Layer 20 may be constructed of a conductive epoxy, such as epoxy silver solder, so that facing surfaces of plates 12 and 14 are electrically connected together as well as mechanically secured together. In this manner, as will be described below, when drive plate 14 is stressed it, in turn, transmits mechanical forces to plate 12, so as to mechanically stress plate 12 in directions acting both laterally and perpendicularly of its plane.

Drive plate I4 may be pemianently polarized by applying an electric field across its opposing flat surfaces. Thus, as shown in FIG. 2, layer 18 is electrically connected to a single pole, double throw switch S1 which serves to connect layer I8 with either an electrical reference, such as ground, or to an interrogating readout voltage source V,,,. Similarly, layer 20 is connected with the single pole, double throw switch S2. Switch S2 serves to connect layer 20 with either an electrical reference, such as ground, or to a source of polarizing voltage B+. Plate 14 may now be polarized by connecting layer 20 with the B+ voltage supply source and layer 18 to ground potential. Thus, an electrical field of sufiicient magnitude to polarize plate I4 is applied across the opposing faces of the plate. The direction of the electric field is indicated by arrows 22. Thereafter, switches SI and S2 may be returned to positions as shown in FIG. 2 for a subsequent readout operation.

Binary information may be stored in memory late 12 by applying an electric field between the opposing faces of the plate in either one of two directions, so that the plate stores either a binary I or a binaryO signal. Layer I6 is connected to a single pole switch S3. Switch S3 serves to connect layer 16 with either a ground potential, or a 8+ source of polarizing potential, or to an output-circuit OUT. When it is desired to store a binary 1 signal in memory plate 12, switches S2 and S3 are manipulated so that B+ potential is applied to layer 16 and ground potential is applied to layer 20. As shown in FIG. 2, however, plate I2 stores a binary signal, which results from having applied B-lpotential to layer and ground potential to layer 16.

With switches S1, S2 and S3 in the positions as shown in FIG. 2, an interrogating input voltage V is applied to layer 18. If the applied voltage V is of a polarity opposite to the direction of polarization of the drive plate, then the magnitude of this interrogation voltage is kept well below the polarization voltage threshold, i.e., the voltage required to permanently polarize drive plate I4, so that the readout process is nondestructive. Application of the readout voltage pulse causes the drive plate to contract or expand in the direction dependent on its prepolarization, as well as the polarity of the applied readout voltage pulse. The direction of contraction or expansion will be both laterally and perpendicularly of the plane defined by plate 14. Since plates I2 and 14 are bonded together, as by the layer 20 of conductive epoxy, any change in physical dimensions of plate 14 will cause corresponding changes in physical dimensions of plate 12. When the memory plate is thus stressed, it develops a voltage which appears between layers 16 and 20, with the polarity at layer 20 being positive or negative, dependent on the state of prepolarization of the memory plate, as well as the direction of mechanical stress. Thus, with reference to FIG. 2, the output voltage V,, will be a negative pulse representative that a binary 0 signal is stored by plate 12. For a further description of a ceramic memory device as shown in FIG. 2, reference should be made to US Pat. application Ser. No. 640,717.

CERAMIC MEMORY MATRIX Having now described a single bit ceramic memory device, together with the manner in which binary information is stored and interrogated, reference is now made to the ceramic memory matrix of FIG. 3. This matrix includes two word line memories TMl and TM2 which, for example, may correspond with the work line memories TMl and TM2 of the ceramic memory matrix TM of FIG. I. As shown in FIG. 3, each word line memory TMl and TM2 includes four single bit ceramic memory devices 10a, 10b, 10c and 10d, each corresponding with the single bit ceramic memory device I0 illustrated in FIG. 2. The common lines of memory devices 10a, 10b, I00, I 0d in word line memory TMl are connected to write circuits W1, W2, W3 and W4, respectively. Similarly, the bit lines of ceramic memory devices 10a, 10b, 10c, 10d of word line memory TMI are also connected to write circuits W1, W2, W3, W4. Also, in a similar manner, the common lines and bit lines of ceramic memory devices 10a, I0b,.l0c, 10d of word line memory TM2 are connected to write circuits W5, W6, W7, W8.

Each write circuit may be identical and take the form as write circuit WI, shown in detail in FIG. 3. The write circuit WI corresponds with the circuitry shown in FIG. 2 and includes switch S2 and switch S3. Switch S2 serves to selectively connect the common line of ceramic memory device 111a with either ground potential or B+ potential or open circuit, and switch S3 serves to respectively connect the bit line of memory device 10a with either ground potential or B+ potential or open circuit. The drive lines of ceramic memory devices 10a, Ifib, 10c, 10d in word line memory TMI are connected together in common and, thence, through a normally open switch S4 to a C+ voltage supply source in a sequence interrogator circuit I Similarly, the drive line conductors of ceramic memory devices 10a, 10b, 10c, 10d in word line memory TM2 are connected together in common and thence through a switch S4 to a C+ voltage supply source in an interrogator circuit 1,.

In operation, switches S2, S3 in each of the write circuits WI through W8 may be manipulated to prepolarize the memory plate in word line memories TMI and TM2. This writing function is the same for each memory device as previously described with reference to FIG. 2. As shown by the direction of the arrows on the memory plates I2 in word line memory TMl, the pattern of binary signals stored by the four memory devices is 0-1-0-I. Similarly, as shown by the arrows on the memory plates I2 in word line memory TM2, the pattern of binary signals stored is 0-1-1-1. Thus, the decimal number of the weighted binary content of word line memory TMI is 5 and the decimal number of the weighted binary content of word line memory TM2 is 7.

Upon closure of switch S4 in the interrogation circuit l the pattern of the binary signals on the bit lines taken from the four ceramic memory devices of word line memory TMl will be 0-1-0-1. Similarly, when switch S4 in interrogator circuit I, is closed, the pattern of the binary signals on the bit lines of the ceramic memory devices of word line memory TM2 will be 0-1-1-1. As previously discussed with reference to FIG. 2, the duration of the output voltage V, on each bit line corresponds in time with the duration of the interrogating voltage V,,,. Accordingly, the pattern of open circuit binary signals obtained on the bit lines of word line memory TMI or word line memory TM2 exhibits a time duration in accordance with the time duration of application of the interrogating voltage, i.e., the time duration that switch S4 in interrogating circuit I is closed, or that switch S4 in interrogating circuit I is closed.

SEQUENCE CONTROLLER.

Having now described a ceramic memory matrix, circuitry for altering the binary information stored, and circuitry for interrogating the matrix, a description is now presented as to the manner in which the matrix is interconnected with various circuits to provide a load sequence controller. As shown in FIG. 1, the load sequence controller includes an alternating voltage source V which may take any suitable form, such as a 60 cycles per second line frequency source. The pulse source circuit S is coupled to voltage source V and includes a suitable frequency dividing circuit 30 which serves to divide the 60 cycles per second frequency of source V into a frequency of 1 cycle per second. The output of frequency divider 30 is applied to a shaper 32 so as to provide a train of equi-timespaced pulses exhibiting a frequency of one pulse per second. Binary counter C is coupled to pulse source S to receive the train of equi-time-spaced pulses. This binary counter is a four stage counter and has four outputs a, b, c, d which have decimal weights of 8, 4, 2, 1, respectively, for providing a patternofbinarysignals,thedecirnalwdghtofwhichincreasesln aecordanccwiththedecimalnumberofthepulscscountedflhe four outputs'a, b, c, d of the binary counter C are coupled to a binary comparator BC.

The ceramic memory matrix TM includes four word line memories TMl, TM2, TM3 TM4, each of which may be constructed as a schematically illustrated in FIG. 3 with respect to word line memories TMl and TM2. Preferably, however, this matrix is constructed in accordance with an improved matrix disclosed in our previously identified US. Pat. application, Ser. No. 640,7l7. As shown in FIG. 3, each of the four word line memories includes four ferroelectric bistable memory means which serve to store a binary I or a binary O-signal so that the decimal number of the weighted binary content of a word line memory is representative of a desired time duration for an associated load interval. Each of these memory means a, 10b, I 0c, [0d in FIG. 3, has an input in the form of a drive line which are all connected together in common for any one word line memory and thence to one of the outputs l, 2, 3 or 4 of the interrogator I for receiving interrogation signals. Also, each of these bistable memory means has an output in the form of a bit line which serves to carry a binary signal in response to receipt of an interrogation signal. These bit lines for associated bits in the various word line memories may be connected together, as shown in FIG. 3. The bit line output circuits of the matrix TM include circuits g, h, i and j, which are respectively coupled through bit line amplifiers Al, A2, A3 and A4 to a type D, four stage flip-flop register R1. Register R1 includes four D type flip-flops FFI, FF2, FF3 and FF4, each having a set tenninal S and a toggle terminal T. The outputs of amplifiers Al through A4 are respectively connected to set terminals S of flip flops FF 1 to FF4. The output circuits of these four flip-flops are connected to binary comtor BC. In a manner similar to the outputs of binary counter C, the bit line output circuits g, h, i and j of matrix TM and the corresponding outputs of register R1 have decimal weights of 8, 4, 2 and l, respectively.

The output of the binary comparator BC is connected to a reset input of the binary counter C, a reset input of register R1, and to the input of the sequence-interrogator circuit l. Circuit l may'take the form of a circulating ring counter having its output circuits 1, 2, 3 and 4 respectively connected to the commonly connected drive lines of word line memories TMl, TM2, TM3 and TM4. The interrogator circuit I serves to sequentially energize its output circuits 1, 2, 3 and 4 in a cyclical fashion in response to actuating trigger pulses received from the binary comparator BC. The equivalent function of interrogator circuit I is that as performed by interrogator circuits I, and I, shown in simplified form in FIG. 3. Diodes D1 to D4, poled as shown in FIG. I, connect the four output circuits of interrogator circuit I in common and thence to the toggle terminals T of the four stage flip-flop register R1.

Interval time write circuit-TW has four outputs respectively coupled to word line memories TM L TMZ, TM3 and TM4 for purposes of electrically altering the binary state of each memory means in the associated work line memories. This circuitry may take the form as shown by the simplified circuit W1 in FIG. 3 or, alternatively, may take the form of more complex solid state, static element automatic writing circuitry.

The output circuits 1, 2, 3 and 4 of the sequence-interrogator circuit I are coupled to a load control circuit LC. This load control circuit includes signal amplifiers 34, 36, 38 and 40 which are respectively connected to output circuits I, 2, 3 and 4 of circuit l. The output of amplifier 34 is coupled to a main street go signal light MSG, as well as through a diode 42, poled as shown, to a cross street red signal light CSR. The output of signal amplifier 36 is coupled through a diode 44, poled as shown, to signal light CSR and directly to a main street yellow signal light MSY. The output of signal amplifier 38 is coupled to a cross street go signal light CSG as well as though a diode 46, poled as shown, to a main street red signal light MSR. The output of signal amplifier 40 is coupled to a cross street yellow signal light CSY as well as through a diode 48, poled as shown, to signal light MSR.

OPERATION The four word line memories of memory matrix TM serve to store binary'signals-representative of the desired time duration for the various traffic. intervals to be allocated and timed. In the example of FIG. 1, only four traffic intervals are allocated and timed; to wit, main street go, main street yellow, cross street go, and cross street yellow intervals. The time durations for these four intervals are represented by the binary signals stored in word line memories TMI, TM2, TM3 and TM4, respectively. The binary signals stored in these word line memories should be written as desired. Thus, for example, both caution intervals may have a time duration of 3 seconds each. If so, then the circuitry in the interval time write circuit TW is manipulated so that the pattern of binary signals stored in word line memories TM2 and TM4 is 0-0-1-1 which, as is well known, has a decimal weight equal to the decimal number 3. This pattern of binary signals is indicated on word line memories TM2 and TM4 in FIG. 1. Similarly, it may be desired that the time duration for the main street go interval be 9 seconds. Accordingly, the time write circuit TW is manipulated sothat the memory means in word line memory TMI stores a binary signal pattern 1-0-0-l, which is equal to the decimal number 9. This is shown on word line memory TMI in FIG. 1. Lastly, the cross street go interval may be set for 8 seconds which, as shown on memory word line TM3 in FIG. 1, is the binary signal pattern 1-04-0. It is to be appreciated, however, that the assumed durations of these various intervals is for purposes of illustration only, and in practice the time durations are normally longer than that presented in this example.

With matrix TM having its memories written as discussed above, the operation commencing with the main street go interval will now be presented. The main street go interval commences when the sequence-interrogator circuit I energizes its output circuit 1 in response to receipt of a trigger pulse from binary comparator BC. The output signal carried by circuit 1 is a positive signal, as represented by voltage V in FIG. 2, and serves to interrogate word line memory TMl. This interrogating signal has a duration which until the interrogation circuit I receives another trigger pulse from binary comparator BC. During this time period, each of the memory means in word line memory TMl is interrogated to provide a pattern of binary signals on output circuits 3, h, i and j. This pattern of binary signals is in accordance with the state of prepolarization of each memory plate 12 in the several memory means being interrogated. The interrogation signal also permits register R1 to receive this pattern of binary signals from circuits g, h, i and j and provide the same pattern of signals at its output circuits for the duration of the interrogation signal. This pattern of binary signals is applied to the binary comparator BC.

At the same time that the sequence-interrogator circuit I was actuated by a trigger pulse to energize its output'circuit l, the register R1 was reset, or cleared, and the binary counter C was reset to again count pulses from sourceS and provide a pattern of binary signals on its output circuits a, b, c, and d, which pattern changes in accordance with the decimal number of the pulses counted. Initially then, the pattern of output signals on circuits a, b, c and d is -0-0-0. After the first pulse has been counted, the pattern changes to 0-0-0-1 and, then, upon the second pulse the pattern changes to 0-0-1 -0. When nine pulses have been counted the pattern of binary signals on outputs a, b, c and d becomes 1-0-0-1. At that point in time the pattern of binary signals received from the binary counter C is the same as that received from register RI and a match is obtained. Each time such a match is obtained, the binary comparator BC provides an output trigger pulse which is applied to the sequence-interrogator circuit l to energize the next output circuit, in this case output circuit 2, as well as to reset the binary counter C to a zero reading and to reset, or clear, register R1. During the time duration that the nine pulses were being counted by binary counter C, output circuit 1 of the sequence-interrogator circuit I was energized to, in turn, energize both the main street go signal light MSG and the cross street red signal light CSR.

- 'When the main street green interval has timed out, i.e., when the binary comparator BC provides an output trigger signal, the sequence-interrogator is actuated so as to deenergize its output circuit 1 and energize its output circuit 2. At the sanre time, binary counter C is reset to a zero reading and register R1 is reset..'lhe cross street yellow interval is now allocated since a circuit is completed through signal amplifier 36 to energize the main street yellow signal lamp MSY, as well as the cross street red signal lamp CSR. The energization of output circuit 2 of interrogator circuit I serves to interrogate the memory means in the word line memory TM so that the output circuits 3, Ir, i and j of matrix TM now carry the binary signal pattern 0-0-14. This pattern of signals is now carried by the four output circuits of register RI and applied to binary comparator BC. When three pulses from pulse source 8 have been counted, the pattern of binary signals on output circuits 0, b, c and d of binary counter C is 0-0-l-l and a match is ob- Thus, binary comparator BC provides a second trigger signal to reset binary counter C, to reset register R1 and to acmate the sequence-interrogator circuit I. This operation continues for each of the intervals in the same manner as described above, and in a cyclical fashion. The cross street red and main street red signal displays are not in themselves allocated and since, as is conventional, signal lights MSR and CSR are energized whenever the conflicting phase go and yellow lights are energized. In the event it is desired to change the time duration for one of the timed intervals, the interval time write circuit TW is employed as in the manner discussed previously with respect to FIG. 3, so as to change the binary signals stored by the word line memory associated with the interval to be changed.

SECOND EMBODIMENT Referring now to FIG. 4, there is shown a second embodiment of the invention. This embodiment is quite similar to that v as shown in FIG. I, and, accordingly, like components in both FIGS. are. identified with like character references. Before discussing the additional circuitry, a few comments are in order with respect to modifications made in' circuitry found in FIG. 4, which compares with corresponding circuitry in FIG. 1. Thus, binary counter C in FIG. 4 is shown as a six stage binary counter, having s'ix outputs a, b, c, d, e and f, having decimal weights of 32, I6, 8, 4, 2, I. The interval time storage ceramic memory matrix TM of FIG. 4 now includes six word line memories TMl through TM6. Also, each word line memory includes six bits instead of the four bits shown in FIG. 1. Accordingly, the memory matrix TM has six bit line output circuits g, h, i, j, k and 1, having decimal weights of 32, I6, 8, 4, 2, I. Register R1 is a six stage flip-flop register coupled to the output circuits g through by meansiof amplifiers Al to A6. The interval time write circuit W has additional ci r-.

cuitry so that it has the capacity of altering the binary signals stored by six word line memories, as opposed to the four word line memories of FIG. 1. Likewise, the sequence-interrogator I has six outputs, i.e., it is a six stage circulating ring counter,

coupled to the six commonly connected drive lines of the six word line memories TM] through TM6.

In the embodiment of FIG. 4, an interval program storage ceramic memory matrix PM is interposed between the output circuits of the sequence-interrogator circuit I and the load control circuit LC. Memory matrix PM is a 3 bit, six word line desired by an interval program write circuit PW which may be constructed in the same manner as is write circuit W. The drive lines for matrix PM are connected to output circuits 1 through 6 of interrogator circuit 1. Matrix PM has three bit line output circuits p, g, r respectively having decimal weights 7 'of 4, 2 and l. The three bit line output circuits p, 3, ref memory matrix PM are respectively coupled through amplifiers A7,'A8 and A9 to a three stage, type D, flip-flop register R2. Register R2has three flip-flops FF7, FF8 andFF9, each corresponding with flip-flop in register R1 or R1. The three outputs of register R2 are coupled to a decimal decoder BD, such as a diode matrix, having six output circuits s, t, u, v,

w and x.

The load control circuit LC is quite similar to that of load control circuit LC. The inputs of signal amplifiers 34, 36, 38 and 40 'are respectively taken at outputs t, u, w and x ofthe binary to decimal decoder BD. In addition to the circuitry shown in FIG. 1, load control circuit LC also-includes a signal amplifier 50 having its input connected to output circuit s'of decoder BD and its output connected to a main street green advance signal light MSGI. An additional diode'52, poled as shown in FIG. 4', connects the output of amplifier 50 with the cross street red signal light CSR. The load control circuit DC also includes a signal amplifie 54 having its inputconnected to the output circuit v of the decoder BD, and its output connected to a cross street ad-..

vance green light CSGl..Another diode 56, poled as shown, connects the output or signal amplifier 54 with the main street red signal light MSR. The main street advance light MSGl and the cross street advance signal light CSGl may, for

example, take the form of left turn arrows,'which are In-- and decoder ED, is essentially the same as that discussed hereinbefore with respect to the embodiment of FIG. 1. Thus, sequencer l' serves to sequentially apply interrogating signals to the interval time storage wordline memories TMI through TM6. Each time that the pattern of binary signals on the output circuits of registerRl is the same as the pattern of binary signals on output circuits 0 through f of counter C, the binary comparator BC resets the binary counter C', resets register RI, and actuates the interrogator I to apply an interrogating signal to the next succeeding word line memory. In this em bodirnent, however, output circuits 1 through 6 of the sequence-interrogator circuit I are respectively coupled to of the pattern of binary signals on the bit line output circuits p through r. That is, circuit s is energized whenever the decimal weight is l (binary code 001), circuit 1 is energized when decimal weight is 2 (binary code 010), circuit u is energized when the decimal weight is 3 (binary code 011), circuit v is energized when the decimal weight is 4 (binary code 100), circuit w is energized when the decimal weight is 5 (binary code 101), and circuit x is energized when the decimal weight is 6 (binary code 110).

If it is desired that all of the timed intervals be'allocated and that they be allocated in a predetennined order of: main street advance greeri; main street green; main street yellow; cross street advance green; cross street green; and, cross street yellow, then the interval program storage memory matrix PM should be written to reflect this predetermined order. Accordingly, the write circuit TW is actuated so that word line memories PMl through PM6 respectively store binary signals having decimal weights of l, 2, 3, 4, 5 and 6. The pattern of binary signals for this order is indicated on word line memories PM1 through PM6 in FIG. 4.

With the matrix PM being written in the predetennined order discussed above, it will be appreciated when word line memory PM! is interrogated simultaneously with the interrogation of word line memory TMl, the pattern of binary signals on the output circuits p through r of matrix PM is 001. With this pattern of binary signals applied to decoder BD the decoder's output circuit s is energized so as to energize main street green advance signal light MSGl as well as the cross street red sigtal light CSR. When the binary comparator BC again actuates the sequence-interrogator l, word line memories TMZ and PM2 are interrogated. Thus, only output circuit t of decoder ED is energized, whereupon main street green advance signal light MSG! is deenergized and main street green signal light MSG is energized. This sequence of operation is continued through the remaining word line memories and then the sequence is repeated in a cyclical fashion.

It may be desired to change the interval program, as by eliminating the main street green advance interval and allocating the time previously given to that interval to the main street green interval. In such case the write circuit TW is actuated so as to rewriteword line PMl so that it stores the sanne pattern as binary signals being stored by word line memory PM2, i.e., 010. In this case, when output circuit 1 of the sequence-interrogator l is energized, word line memories PMl and TMl are interrogated. However, since the binary content of word line memory PM1 has been changed, the bit line output circuits p through r now carry the binary signal pattern 0-1-0. Accordingly, only output circuit 1 of decoder BD is energized so as to energize both the main street green signal light MSG and the cross street red signal light CSR. 'llne main street green advance signal light MSGl was not energized. After interrogator l is again actuated, word line memory PM2 is interrogated and the bit line output lines p through r carry the same binary sigrnal pattern; to wit, 0-1-0, and again only output circuit r of decoder 80 is energized.

1n the event it is desired to completely eliminate the main street green interval, word line memory PM is altered so that the pattern of binary signals is 0-0-0, and, in addition, word line memory TM is altered-so that its pattern of binary stored signals is 0-0-0. In this event, once the sequence-interrogator circuit 1' is actuated to energize its output circuit 1, the pattern of binary sigials applied to bit line output circuits g through I has a decimal weight of zero. Since the binary counter has been reset to zero, a match is obtained and the binary comparator BC' actuates the sequence-interrogator l to energize its output circuit 2. Also, during this momentary period that output circuit 1 is energized, the pattern of binary signals on bit lines p through r of matrix PM is of a decimal weight of zero and, accordingly, none of the decoder output circuits .9 through x are energized.

Another function that may be performed by the embodiment shown in FIG. 4, is that one of the intervals may be timed without a corresponding load being energized. This function,

while perhaps not of significance to the art of traffic control, has applications in process control fields where it is desired to have a timed off condition. This function may be performed, forexample, by rewriting one of the program word line memories to store a zero signal. Thus, for example, program word line memory PMS may be rewritten to store the binary signal pattern 0-0-0. Accordingly, when word line memory TM3 is,

interrogated, a certain period of time will elapse, in accordance with the binary signals stored in memory TM3, until the sequence-interrogator circuit l' is actuated to interrogate word line memory TM4. During this period, however, the output circuits of register R2 carry a binary signal pattern of 0-0- -0. Thus, no load will be energized.

Although the invention has been shown in connection with preferred embodiments, it will be readily apparent to those skilled in the an that various changes in form and arrangement of parts may be made to suit requirements without departing from the spirit and scope of the invention as defined by the appended claims.

We claim:

1. Apparatus for sequentially allocating and timing a plurality of load intervals and comprising:

a plurality of interval time storage memories each corresponding with an associated load interval to be timed, each said memory including: plurality of electrically alterable and electrically interrogatable bistable memory means each storing a binary one of a binary zero signal so that the weighted binary content of a said memory is a decimal number representative of a desired time duration for an associated load interval, each said memory means having an input for receiving an interrogation signal and an output for carrying a said binary signal in response to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signals to said plurality of memories so that when any one memory is interrogated the outputs of its plurality of memory means provide a pattern of said binary signals; a source of equi-time spaced pulses; and, means for actuating said interrogating means to interrogate the next succeeding of said plurality of memories when the decimal number of the said pulses received is equal to the decimal weight of the pattern of binary signals on the outputs of the memory means of the memory last interrogated,

each bistable memory means comprising an easily polarized ferroelectric memory plate, a drive plate having the property of changing its dimensions upon application of an electrical signal and being pemnanently polarized, said plates being mounted with facing surfaces having an interposed conductive layer, an output conductive layer on the remaining surface of the memory plate and an input conductive layer on the remaining surface of the drive plate, the input and output of the memory means being connected to the said input and output conductive layers respectively.

2. Apparatus as set forth in claim 1 wherein said interrogating means includes a plurality of outputs, corresponding in number with said plurality of memories, for sequentially carrying said interrogation signals.

3. Apparatus as set forth in claim 2 wherein said interrogation means includes circuit means responsive to each actuation by said actuating means to sequentially energize said interrogating outputs one at a time to carry a said interrogation signal for a time duration extending until said interrogation means is again actuated by said actuating means.

4. Apparatus as set forth in claim 3 including load interval control means coupled to each said interrogating output to control allocation of said load interval for a time duration in accordance with the time duration a said interrogation signal is carried by the said interrogating output.

5. Apparatus as set forth in claim 1 including interval time writing circuit means for electrically altering said memory means to selectively change the binary states of the stored binary signals.

6. Apparatus as Set forth in claim 1 wherein each said bistable memory means includes ferroelectric storage capacitor memory plate means having a surface, said plate means adapted to be polarized in one of two stable states; and, piezoelectric driving plate means having a portion thereof secured to at least a portion of said surface in such a manner that application of a said interrogation signal to said driving plate means causes transmission of mechani-- cal forces to said memory plate means in directions acting both laterally and perpendicularly of said surface so that said memory plate means provides an output voltage signal of a polarity in accordance with the state of polarization of said memory plate means.

7. Apparatus for sequentially allocating and timing a plurality of load intervals and comprising:

a plurality of interval time storage memories each corresponding with an associated load interval to be timed;

a plurality of interval program storage memories each corresponding with an associated load interval to be allocated;

each of said memories including:

a plurality of electrically alterable and electrically interrogatable bistable memory means each storing a binary one or a binary zero signal so that the weighted binary content of a said memory is a decimal number, each said memory means having an input for receiving'an interrogation signal and an output for carrying a said binary signal in response to receipt of an interrogation signal; I

interrogation means for sequentially applying interrogation signals simultaneously to different pairs of memories from said two pluralities of memories, whereby the outputs of each memory of said pair of simultaneouslyinterrogated memories carry a pattern of said binary signals;

a source of equi-time-spaced pulses; and,

means for actuating said interrogating means to interrogate the next succeeding pair of memories when the decimal number of the said pulses received is equal to the decimal weight of the pattern of binary signals on the outputs of the memory means of the interval time storage memory last interrogated.

8. Apparatus as set forth in claim 7 wherein said plurality of interval time storage memories correspond in number with said plurality of interval program storage memories, and said interrogating means includes a plurality of outputs, corresponding in number with each said plurality of memories, for sequentially carrying said interrogation signals.

9. Apparatus as set forth in claim 8 wherein said interrogation means includes circuit means responsive to each actuation by said actuating means to sequentially energize said interrogation outputs one at a time to carry a said interrogation signal for a time duration extending until said interrogation means is again actuated by said actuating means.

10. Apparatus as set forth in claim 9 including binary signal decoding means coupled to the outputs of each said memory of said plurality of interval program storage memories to provide a decimal output representative of which one of said interval program memories is being interrogated, and load interval control means coupled to said decoding means to control allocation of a particular load interval in accordance with which one of said interval program memories is being interrogated and for a corresponding time duration thereof.

11. Apparatus as set forth in claim 10 including interval program writing circuit means for electrically altering said memory means of said interval program storage memories to selectively change the binary states of the binary signals stored therein.

12. Apparatus as set forth in claim 11 including interval time writing circuit means for electrically altering said memory means of said interval time storage memories to selectively change the binary states of the binary signals stored 4 therein.

13. Apparatus as set forth in claim 7 wherein each said bistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface, said plate means adapted to be polarized in one of two stable states; and,

piezoelectric driving plate means having a portion thereof secured to at least a portion of said surface in such a manner that application of a said interrogation signal to said driving plate means causes transmission of mechanical forces to said memory plate means in directions acting both laterally and perpendicularly of said surface so that said memory plate means provides an output voltage signal of a polarity in accordance with the state of polarization of said memory plate means.

14. A traffic controller for sequentially allocating and timing a plurality of traffic intervals to be displayed by traffic signal light means and wherein said traffic controller comprises:

a plurality of traffic interval time storage memories one each for each said traffic interval to be allocated and timed, each said traffic interval time storage memory including: I

a plurality of electrically alterable and electrically interrogatable bistable memory means each storing a binary. one or a binary zero signal so that the decimal number of the weighted binary content of a said memory is representative of a desired time duration for an associated trafi'rc interval, each said memory means having an input for receiving an interrogation signal and an output for carrying a said binary signal in response to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signals to said plurality of memories so that when any one memory is interrogated the outputs of its plurality of memory means provide a pattern of said binary signals;

a source of equi-time spaced pulses; and

means for actuating said interrogating means to interrogate the next succeeding of said plurality of memories when the decimal number of said pulses received is equal to the decimal weight of the pattern of binary signals on the outputs of the memory means of the memory last interrogated;

each bistable memory means being of the nondestructive readout, dual plate type comprised of an easily polarized memory plate and a permanently polarized drive plate, the plates having facing surfaces which are secured to each other.

15. A traffic controller as set forth in claim 14 wherein said interrogating means includes a plurality of outputs, corresponding in number with said plurality of memories, for sequentially carrying said interrogation signals.

16. A traffic controller as set forth in claim 15 wherein said interrogation means includes circuit means responsive to each actuation by said actuating means to sequentially energize said interrogating outputs one at a time to carry a said interrogation signal for a time duration extending until said interrogation means is again actuated by said actuating means.

17. A trafi'rc controller as set forth in claim 16 including traffic interval control means coupled to each said interrogating output to control allocation of a said trafiic interval for a time duration in accordance with the tim duration a said interrogation signal is carried by the said interrogating output.

18. A traffic controller as set forth in claim 14 wherein each said bistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface, said plate means adapted to be polarized in one of two stable states; and

piezoelectric driving plate means having a portion thereof secured to at least a portion of said surface in such a manner that application of said interrogation sigtal to said driving plate means causes transmission of mechanical forces to said memory plate means in directions acting both laterally and perpendicularly of said surface so that said memory plate means provides an output voltage signal of a polarity in accordance with the state of polarization of said memory plate means.

19. A traffic controller for sequentially allocating and timing a plurality of trafiic intervals to be displayed by trafiic signal light means to' at least one direction of traffic flow and wherein said tralfic controller comprises:

a plurality of traffic interval time storage memories each corresponding with an associated traffic interval to be timed;

a plurality of trafiic interval program storage memories each corresponding with an associated traffic interval to be allocated;

each of said memories including:

a plurality of electrically alterable and electrically interrogatable bistable memory means each storing a binary one or a binary zero signal so that the weighted binary content of a said memory is a decimal number, each said memory means having an input for receiving an interrogation signal and an output for carrying a said binary signal in response to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signals simultaneously to different pairs of memories from said two pluralities of memories, whereby the outputs of each memory of said pair of simultaneously interrogated memories carry a pattern of said binary signals;

a source of equi-time-spaced pulses; and

means for actuating said interrogating means to interrogate the next succeeding pair of memories when the decimal number of the said pulses received is equal to the decimal weight of the pattern of binary signals on the outputs of the memory means of the interval time storage memory last interrogated.

20. A traffic controller as set forth in claim 19 wherein each said bistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface, said plate means adapted to be polarized in one of two stable states; and

piezoelectric driving plate means having a portion thereof secured to at least a portion of said surface in such a manner that application of said interrogation signal to said driving plate means causes transmission of mechanical forces to said memory plate means in directions acting both laterally and perpendicularly of said surface so that said plate means provides an output voltage signal of a polarity in accordance with the state of polarization of said memory plate means.

21. A traffic controller as set forth in claim 19 wherein said plurality of traflic interval time storage memories correspond in number with said plurality of traffic interval program storage memories, and said inten'ogating means includes a plurality of outputs, corresponding in number with each said plurality of memories, for sequentially carrying said interrogation signals. I

22. A traffic controller as set forth in claim 21 wherein said interrogation means includes circuit means responsive to each actuation by said actuating means to sequentially energize said interrogating outputs one at a time to carry a said interrogation signal for atime duration extending until said interrogationmeansisagainactuatedbysaidactuatingmeans.

23. A traflic controller as set forth in claim 22 including binary signal decoding means coupled to the outputs of each said memory of said plurality of interval program storage memories to provide a decimal output representative of which one of said interval program memories is being interrogated, and traffic interval control means coupled to said decoding meats to control allocation of a particular traffic interval in accordance with which one of said traffic interval program memories is being interrogated and for a corresponding time duration thereof.

24. A traffic controller as set forth in claim 23 including tralfic program writing circuit means for electrically altering said memory means of said traffic interval program storage memories to selectively change the binary states of the binary signals stored therein.

25. A traffic controller as as set forth in claim 24 including traffic interval time writing circuit means for electrically altering said memory means of said traffic .interval time storage memories to selectively change the binary states of the binary signals stored therein.

26. Apparatus for selectively programming a plurality of loads and comprising:

a plurality of electrically alterable and electrically interrogatable bistable memory means each storing a binary one or a binary zero signal, each said memory means having an input circuit means for receiving an interrogation signal and an output circuit means for carrying a said hinary signal in response to the receipt of an interrogation s g interrogation means for applying interrogation signals to saidplurality of memory means so that when a said memory means is interrogated the output circuit means of said memory means carries a binary signal representative of the binary signal stored in said bistable memory means, said interrogating means having an input circuit means for receiving input-pulse signals and a plurality of output circuit means, one coupled to each said memory means, I

for respectively carrying a said interrogation signal in accordance with the number of received input pulse signals; and circuit means connected to said output circuit means of said plurality of memory means and adapted to be connected to a load;

each bistable memory means being of the nondestructive readout, dual plate type comprising an easily polarized memory plate and a pennanently polarized drive plate, the plates having facing surfaces which are secured to each other.

27. Apparatus as set forth in claim 26 wherein said interrogating means includes circuit means for sequentially energizing its output circuit means in accordance with the number of received input pulse signals to thereby sequentially apply interrogating signals to said plurality of memory means.

28. Apparatus as set forth in claim 27 including a source of time spaced pulses; and,

said interrogation means being coupled to said pulse source for interrogating the next succeeding of said plurality of memory means in the response to the receipt of said pulse.

29. Apparatus as set forth in claim 26 wherein each said bistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface, said plate means adapted to be polarized in one of two stable states; and,

piezoelectric driving plate means having a portion thereof secured to at least a portion of said surface in such a manner that application of a said interrogation signal to said driving plate means causes transmission of mechanical forces to said memory plate means in directions acting both laterally and perpendicularly of said surface so that said memory plate means provides an output voltage signal of a polarity in accordance with the state of polarization of said memory plate means.

30. Apparatus as set forth in claim 26 wherein said plurality of bistable memory means is a ferroelectric capacitor matrix and includes a plurality of rows each including at least one ferroelectric storage capacitor memory means; and,

each of said plurality of output circuit means of said interrogating means respectively carry a said interrogation signal to thereby interrogate a selected row of said ferroelectric storage memory means.

31. Apparatus as set forth in claim 30 wherein each said row of ferroelectric storage capacitors includes a plurality of ferroelectric storage memory means each corresponding with an associated load; and,

rogated the output circuit means of said plurality of memory means carry a pattern of binary signals representative of the binary states of said interrogated row of ferroelectric memory means.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3300775 *Nov 6, 1963Jan 24, 1967Amp IncSequential bit binary detector circuit and system
US3302170 *Apr 28, 1964Jan 31, 1967IbmTraffic light control buffer
US3305828 *Apr 7, 1964Feb 21, 1967Gen Signal CorpProgressive traffic signal control system
US3375494 *Dec 22, 1964Mar 26, 1968Siemens AgControl units for programmed operation of traffic signals
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5208584 *Sep 3, 1991May 4, 1993Jonathan KayeTraffic light and back-up traffic controller
US7036124Mar 1, 1999Apr 25, 2006Sun Microsystems, Inc.Computer resource management for competing processes
Classifications
U.S. Classification700/14, 701/117, 340/916
International ClassificationG08G1/07, G08G1/085
Cooperative ClassificationG08G1/085
European ClassificationG08G1/085
Legal Events
DateCodeEventDescription
Dec 28, 1987ASAssignment
Owner name: EAGLE SIGNAL CONTROLS CORP., A CORP. OF DE.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WICKES MANUFACTURING COMPANY, A DE. CORP.;REEL/FRAME:004821/0443
Effective date: 19871218
Owner name: WICKES MANUFACTURING COMPANY, 26261 EVERGREEN ROAD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GULF & WESTERN INDUSTRIES, INC., FORMERLY GULF & WESTERNINDUSTRIES, INC.,;REEL/FRAME:004821/0437
Effective date: 19871215
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GULF & WESTERN INDUSTRIES, INC., FORMERLY GULF & WESTERN INDUSTRIES, INC.,;REEL/FRAME:004821/0437
Owner name: WICKES MANUFACTURING COMPANY, A CORP. OF DE.,MICHI