US 3584741 A
Description (OCR text may contain errors)
United States Patent  Inventor Edward F. Schirmer South Burlington, Vt.  Appl. No. 837,595  Filed June 30, 1969  Patented June 15, 1971  Assignee International Business Machines Corporation Armonk, N.Y.
[S4] BATCH SORTING APPARATUS 15 Claims, 9 Drawing Figs.
52 U.S. Cl 209/74, 209/81  Int. Cl B07c 3/12  Field of Search 209/74, 81; 324/158 T, 158 P; 225/2; 29/583  References Cited UNITED STATES PATENTS 3,503,500 3/1970 Klossika 209/74 Primary Examiner--- Allen N. Knowles Atzorneys- Hanifin and Jancin and Willis E. Higgins ABSTRACT: An array of objects in a predetermined sequence and direction of orientation, such as semiconductor chips, is tested and batch sorted by a sorting fixture having a matrix of locations with individually actuable vacuum pickups, while maintaining a predetermined direction of orientation of the objects. A system for this purpose includes a tester for measuring a characteristic of the objects in the array while maintaining them in a predetermined sequence and direction of orientation. Means for storing a result based on the measurements for each object in the array is connected to the tester. The sorting fixture for batch separation of objects with the desired characteristic on the basis of the stored results from the remainder of the objects is connected to the means for storing to allow selection of the objects on the basis of the stored results. Means engageable by the sorting fixture receives the objects having the desired characteristic. The selection and release of the objects to the means engageable by the sorting fixture are both carried out while maintaining a predetermined. direction of orientation in the selected objects, enabling reorientation of the objects during their handling to be eliminated.
ATENTEDJUN1-5l97l I 3584741 saw 1 or 4 IN VliN UR. EDWARD F. SCHIRMER ATTORNEY PATENIED JUN] 519m SHEET 2 OF 4 PATENTEnJumsssn 3,584,741
SHEET 3 OF 4 12 0 ojo o 0 o 0 40 O 0 Q 32/6 Q 0 4 3a 0 O b o o o o o 40 w M H To 1 7 VACUUM VACUUM I 732 I 73 I n I WL ll 7 L i m J L 7 PEG. 6 1? 76 11 n PATENIED JUN! 5 l97l SHEET '4 OF 4 ELECTRICAL TESTER X-Y SERVOMECHANISM I I I COMPUTER SERVOMECHANISM BATCH SORTING APPARATUS FIELD OF THE INVENTION This invention relates to apparatus for testing and batch sorting an array of objects while maintaining them in a predetermined direction of orientation. More particularly, it relates to such apparatus for testing and batch sorting nondefective semiconductor chips from defective chips and to a fixture for so sorting the chips on a batch basis while maintaining the nondefective chips in a predetermined direction of orientation, and preferably, a predetermined sequence of orientation as well.
In the fabrication of semiconductor chips either as discrete circuit elements or as integrated circuits of the type described by minute Agusta, 64-Bit Planar Double Diffused Monolithic Memory Chip, 1969 IEEE International Solid State Circuits Conference Digest of Technical Papers, yields of twenty percent or less nondefective chips are common, due to the very complex processes necessary or their fabrication. The reasons for such small yields may be appreciated by realizing that the integrated circuit chips described in the Agusta paper contain 664 circuit components in integrated form in a chip of silicon measuring only 0.112 by 0.112. The fabrication of such integrated circuits requires eight different photomask steps to define minute areas for selective diffusion of impurities, to define the intricate aluminum metallization interconnecting patterns, and the like. The chips are therefore tested after fabrication of them is completed and prior to mounting them on a ceramic substrate to form a completed module. Defective chips may then be discarded, only nondefective chips mounted in the modules, and further handling of the defective chips eliminated.
Such semiconductor chips are fabricated in wafers containing up to 100 or more of the chips. After fabrication has been completed, the wafers are mounted on a dicing block with a suitable adhesive, such as glycol phthalate, then diced into individual chips. Testing of the chips may be carried out either while the chips retain their positions in a wafer, before or after dicing (called testing at the wafer level), or after the adhesive mounting the chips on the dicing block has been dissolved away to give individual chips (called testing at the chip level).
DESCRIPTION OF THE PRIOR ART If the testing is carried out at the wafer level, the defective chips are typically marked with a suitable pen, then sorted out manually later. Apparatus for testing at the wafer level is disclosed, for example, in U.S. Pat. No. 3,437,929.
For high volume production of integrated circuits, if testing is carried out at the chip level, the chips are oriented and fed to testing stations by vibratory bowls. Suitable apparatus or high volume testing at the chip level is disclosed in, for example, J. W. Broderick et al., U.S. Pat. 3,392,830, issued .luly I6, 1968.
It should be recognized that, with apparatus of the type described in the above two references, a manual sort operation is necessary to remove scrap partial semiconductor chips around the edges of a circular wafer. If testing is carried out at the wafer level, a manual sort of defective and nondefective chips as well has hitherto been necessary. Such manual sort operations are tedious, time consuming, and prone to error.
Apparatus for testing at the wafer level which does not require a manual sort operation, but in which chip orientation is lost in sorting, is disclosed by W. O. Druschel, IBM Technical Disclosure Bulletin, Feb., 1964, pages 53-54.
With the above approaches, it has been necessary in the high volume production of integrated circuits to utilize vibratory bowls for orienting the integrated circuit chips for testing, for mounting in modules, or both. While vibratory bowls have proven to be highly satisfactory for transistor chips and for relatively simple integrated circuits under high volume production conditions, orientation of more complex integrated circuits, such as those described in the Agusta paper,
is more difficult. Even more complex integrated circuits now under development will not be capable of orientation using vibratory bowls. Such chips will have to be tested and mounted on modules under high volume production conditions without the use of vibratory bowls for orientation.
Apparatus for testing semiconductor chips at the chip level which does not require orientation of the chips is described in U.S. Pat. No. 3,149,765, but such apparatus is not suitable for high volume production use. Thus, while the art of handling and testing semiconductor chips is a highly developed one, there remains a need for chip handling apparatus suitable for high volume production of integrated circuits which does not require orientation of the chips or manual sorting of defective and nondefective chips.
SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide apparatus for the automatic batch separation of objects having a predetermined desired characteristic from similar objects with an undesired characteristic while maintaining the objects in a predetermined direction of orientation.
It is another object of the invention to provide apparatus for selecting semiconductor chips having desired characteristics without handling the chips on a single, serial basis and while maintaining the chips in a predetermined direction and relative sequence of orientation.
It is another object of the invention to provide apparatus for testing semiconductor chips and selecting chips having desired characteristics while maintaining the chips in a predetermined direction of orientation, the apparatus being suitable for use with high volume semiconductor chip production.
It is yet another object of the invention to provide apparatus for releasing diced semiconductor chips adhesively mounted to a dicing block while removing contaminating adhesive from the chips, without losing the orientation of the chips, and for batch selection of chips having a desired characteristic while maintaining the selected chips in a predetermined direction of orientation.
It is a further object of the invention to provide means for handling and testing integrated circuit chips on a high volume production basis that cannot be oriented and fed with vibratory bowls.
These and other related objects may be obtained by using the handling and sorting apparatus herein disclosed. The invention is based on a sorting fixture which has the capability of selecting objects in an array having a desired characteristic from those not having this characteristic on a batch basis, while maintaining a predetermined direction of orientation in the selected objects, and preferably, a predetermined sequence of orientation as well. This sorting fixture may be combined with a tester for measuring a characteristic of the objects in the array. Means connected to the tester is provided in such a combination for storing a result based on the characteristic measured by the tester for each object in the array and its position in the array. The sorter may then be used to select the objects having a desired characteristic while maintaining these objects in a predetermined direction of orientation. To maintain direction of orientation of the objects after they have been released by the sorting fixture, means engageable by the sorting fixture for receiving the objects is also provided.
As applied to semiconductor chips, the sorting fixture of the invention includes a dicing block for separating a semiconductor wafer adhesively mounted on the block into an array containing a plurality of semiconductor chips adhesively mounted on the dicing block. The sorting fixture has a matrix engageable with the dicing block, to be precisely positioned over a semiconductor wafer diced into an array of adhesively mounted chips on the dicing block. The matrix has a location corresponding to each diced semiconductor chip. Means is provided at each location in the matrix for maintaining each semiconductor chip at its corresponding location in the matrix and in a predetermined direction of orientation after separation from the dicing block. Each location contains an individually actuable vacuum means for picking up the chip a each matrix location after separation from the dicing block, thus maintaining each selected chip in a predetermined direction and sequence of orientation with respect to other chips selected from the array.
The sorting fixture for the first time allows semiconductor chips to be tested at the wafer level, the results of the tests to be stored, nondefective chips to be automatically selected on the basis of the stored test results, and the selected chips to be delivered to a desired location, all while maintaining the chips in a predetermined sequence and direction of orientation, in the high volume production of semiconductor chips. This capability, though of special application to the manufacture of semiconductor chips, particularly integrated circuit chips that cannot be oriented and fed with vibratory bowls, makes the invention of value in testing and sorting a wide variety of electrical components or other objects in an array which must be shorted on the basis of their characteristics.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the inven tion, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS In the drawings:
FIG. I is a perspective view of a fixture for sorting semiconductor chips in partially disassembled form and with partial cut aways to show detail;
FIG. 2 is a perspective view of the bottom of the lower portion of the fixture shown in FIG. I, also partially disassembled and with a partial cut away, showing detail not visible in FIG.
FIG. 3 is a section of the fixture shown in FIGS. 1 and 2, but assembled, taken along the lines 3-3 in FIGS. 1 and 2;
FIG. 4 is a top view of a location in a matrix in the fixture of FIG. 1 with a semiconductor chip in place.
FIG. 5 is an enlarged view of area 5 shown in FIG. 3 with semiconductor chips in place, and representing a partial section of three matrix locations of the type shown in FIG. 4;
FIG. 6 is a front view of another embodiment of a location in a matrix ofa fixture for sorting semiconductor chips with a semiconductor chip in place;
FIG. 7 is a partial cross section as in FIG. 5, but of three of the matrix locations of the type shown in FIG. 6;
FIG. 8 is a perspective view of a rack adapted to receive semiconductor chips from a sorting fixture of the invention; and
FIG. 9 is a diagram of a system in accordance with the invention for testing and an nondefective semiconductor chips on a batch basis.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Chip-Sorting Fixture Referring now to the drawings, more particularly to FIGS. 1,2 and 3, the features of n embodiment ofa sorting fixture l9 suitable for use in the batch separation of nondefective semiconductor chips from defective chips while maintaining the selected chips in a predetermined sequence and direction of orientation, in accordance with the invention, are shown. The fixture 19 comprises a base 20 holding a semiconductor dicing block 22 containing a diced semiconductor wafer 24 mounted thereon by a glycol phthalate adhesive 25 in precisely aligned relationship with respect to precision surfaces 26. A top 28 of the fixture contains a matrix 30 of locations 32. Top 28 has legs 34 extending from the top at either side of matrix 30 and adapted to mate with surfaces 26 on bottom 20 in a precision fitting relationship. The precision mating of legs 34 and surfaces 26 enables the matrix 30 to be precisely positioned over semiconductor wafer 24, since wafer 24 has been previously aligned with respect to surfaces 26. In this manner one location 32 in matrix 30 is positioned over each semiconductor chip 3 in diced wafer 24. The spacing between each chip 38 and the size of chips 38 has been exaggerated for clarity. An actual semiconductor wafer 24 of the type shown would be diced into up to I00 or more chips 38. Each location 32 of matrix 30 has an individually actuable vacuum pickup 40 for picking up the chip 38 at each location 32. In operation, semiconductor wafer 24 carried on dicing block 22 is mounted over aperture 41 in base 20 of the fixture. Through suitable visual alignment techniques, the diced semiconductor chips 38 in wafer 24 are precisely aligned with respect to precision surfaces 26 on base 20. Vacuum is then applied to aperture 41 now closed at the top by dicing block 22, from vacuum line 42 to hold dicing block 22 in place temporarily. Clamps 44 are then adjusted by use of thumbscrews 46 to clamp dicing block 22 to base 20 with chips 38 in the desired position. Use of the vacuum to hold the dicing block 22 in place temporarily while clamps 44 are adjusted prevents the clamps 44 from moving dicing block 22 during their adjustment.
With the semiconductor chips 38 in wafer 24 in the desired position on base 20, the base may be itself precisely positioned on an electrical or optical tester for testing semiconductor chips 38. FIG. 2 shows an alignment means 48 on the underside of base 20 used for this purpose. Alignment means 48 has an upper part 50 and a lower part 52. The upper part 50 has a precision groove 53 and a precision surface 54. Lower part 52 has a precision rod 56 which fits into precision groove 53, and a precision pin 49 which fits against precision surface 54 when the upper and lower parts of the alignment means 48 are together. These four precision members serve to locate base 20 of fixture 29 with accuracy in both X- and Y- directions. Screw 58 is used to fasten upper part 50 and lower part 52 together with the four precision members in engagement. Lower part 52 of means 48 is mounted on a tester or other apparatus in which it is desired to align semiconductor chips 38 for automatic stepping inspection or other desired purpose.
After inspection of semiconductor chips 38 has been completed, upper portion 28 of the fixture is lowered into place with each location 32 of matrix 30 overlying one semiconductor chip 38. Screws 60 may then be tightened to fasten upper and lower portions 28 and 20 of the fixture 19 together in the desired relationship.
At this point, the fixture may be immersed in a suitable solvent, such as acetone, for the glycol phthalate adhesive 25 joining chips 38 to dicing block 22. For this purpose, top 28 of fixture 19 is formed from two sections 61 and 62, which clamp together by means of pins 6 and sockets 64. Vacuum lines 65 may be permanently connected to tubes 66 in section 62 of top 28. Tubes 66 in section 62 terminate in polytetrafluoroethylene disc 67, holes 63 of which mate with vacuum pickups 40 in locations 32 of matrix 30 in section 61 of top 28. Registration pins 69 serve to align holes 68 in disc 67 with each vacuum pickup 40. Handles 70 on section 62 facilitate assembly with section 61.
The configuration of the locations 32 in matrix 30, shown in detail in FIGS. 4 and 5, allows the solvent to flow around each chip 38 The configuration there shown is for a chip 338 having a plurality of raised contact pads 71 around the chip periphery. The vacuum pickup means 40 for each location 32 has an end 72 extending below the matrix surface 73 and of the proper size to fit within pads 71 on chip 38. In order to confine the chip 38 at the location 32 in its existing orientation, it is necessary that the end 72 of vacuum pickup 40 extend beyond the top of pads 60 toward chip surface 74. When this is done, the chip will not be free to wash away when the solvent dissolves the adhesive joining the chip to dicing block 22. The end 72 of vacuum pickup 40 may touch surface 74 of chip 3% as shown in FIG. 5, while the adhesive 25 joining chip 38 to dicing block 22 is dissolved, but this is not necessary.
FIGS. 6 and 7 show an alternative embodiment of a matrix location 75 especially adapted for a chip 76 not having a plurality of raised solder pads around the periphery of the chip. In
this embodiment, the location 75 has a plurality of projections, such as pins 77 which surround chip 76 to prevent movement of chip 76 from location 75 after the adhesive joining chip 76 to dicing block 22 has been dissolved.
In both embodiments of the matrix locations, after the adhesive joining the chips 38 or 76 to the dicing block 22 has been dissolved, the fixture is removed from the solvent and section 61 of top 28 rejoined to section 62. Nondefective chips may then be selectively picked up by application of a vacuum to lines 65 connected to their corresponding locations 32 in matrix 30. Defective chips and partial chips 78 around the edge of wafer 24 (shown in FIG. 1) remain on dicing block 22 and may be washed away.
Semiconductor chips 38 which have been picked up by selective actuation of vacuum pickups 40 at their corresponding locations 32 in matrix 30 may be released to a suitable receiver, such as shown in FIG. 8, while maintaining a predetermined sequence and direction of orientation in the chips. As shown, chip receiver 79 has a plurality of rows 80, each approximately the width of a semiconductor chip 38. Suitable registration surfaces 82 are provided to engage legs 34 of top 28 of the chip-sorting fixture in the same manner as surfaces 26 on the bottom of the chip-sorting fixture, thus precisely positioning the matrix 30 with a row in the matrix corresponding to each channel 80. After matrix 30 has been positioned over channels 80 in chip receiver 79, the vacuum holding each chip 38 to vacuum pickup 40 at locations 32 may be released, thus allowing the chips 38 previously selected to drop into channels 80. .lf some of the chips 38 meet stringent test specifications while other chips 38 only meet less stringent test specifications, the chips meeting the most stringent specifications can be released into one chip receiver 79 and the chips 38 meeting the less stringent test specifications released to another chip receiver 79.
The chips 38 so released to chip receiver 79 rest in channels 80 with their contact pads 71 facing upwards. For usual chip joining to a substrate, these pads should be facing down. Chip receiver 79 may be conveniently used to invert the chips by providing a suitable cover 84 which fits over channels 80. Chip receiver 79 may simply be inverted with the cover 84 in place to invert the chips 38.
Chips 38 may be'moved to the ends 84 of chip receiver 79 or removed from the receiver 79 and conveyed to a chip positioning machine or other further manufacturing apparatus by application of a vacuum tochannels 80. When removing the chips 38 from chip receiver 79 it is not necessary to retain the same sequence and direction of orientation of the chips. It is preferred, however, to maintain them in some known sequence and direction of orientation for continued identification of them and to eliminate the necessity to reorient them before positioning on a module or carrying out other manufacturing operations on them.
Chip-Sortin g And Testing System FIG. 9 shows a simplified schematic diagram of a semicon ductor chip-testing and sorting system incorporating a fixture of the type described above. As shown, the base of the chip-sorting fixture 19 is engaged by a suitable X-Y servomechanism 86 for successively positioning semiconductor chips 38 in diced wafer 24 beneath probes 88. Contact is made to a chip 38 with probes 88, then suitable test pulses are applied to chip 38 from tester 90 through cable 92, and the response of chip 38 thereto is sensed. Based on the response of chip 38, the tester 90 classifies the chip 38 as either nondefective or defective. This information, together with the location of the chip 38 in the array is supplied to computer 94 through cable 95. After testing of all of the chips 38 in diced wafer 24 has been completed, top 28 of the chip-sorting fixture is fit into place with bottom 20, precisely positioning matrix 30 over semiconductor wafer 24, with each array location 32 corresponding to a semiconductor chip 38. The adhesive joining chips 38 to dicing block 22 is then dissolved. Based on the stored test results, computer 94 connected to vacuum system 96 by cable 98 selectively actuates vacuum lines 65 to pick up nondefective semiconductor chips 38. Releasing the vacuum in lines 65 so actuated will then release nondefective semiconductor chips 38 selected to a chip receiver 79 positioned beneath top 28 of the fixture. if desired, the computer 94 may be used for selective release of only the semiconductor chips 38 meeting the most stringent test specifications to one chip receiver 79 and release of the remaining semiconductor chips 38 selected to another chip receiver 79.
If desired, an additional tester, such as visual tester 100 may be connected to computer 94 by cable 102. After semiconductor chips 38 have been subjected to electrical testing by tester 90, the base 20 containing the chips 38 may be loaded into visual tester 100. Computer 94 may then instruct X-Y servomechanism 104 associated with visual tester 100 to step sequentially only to the chips 38 which have tested as electrically nondefective. A revision of the test results stored in computer 94 for the chips 38 in wafer 24 may be made from optical tester 100 through cable 102.
The system based on fixture 19 shown in FIG. 9 may be expanded by storing in the computer an identification of the chip receiver 79 in which nondefective chips 38 from a particular sort operation have been released. Since identification of the chips can be maintained, a chip placement machine could also be connected to computer 94 to record the use of particular chips 38 at a particular time. If a similar identification of module substrates onto which the chips 38 are mounted were maintained, ultimate identification of particular chips in modules as coming from particular semiconductor manufacturing lots could be maintained. This would, for the first time, allow actual semiconductor chip reliability data from the field to be obtained and correlated with process conditions for particular manufacturing lots. This has hitherto not been possible due to inability to maintain identification of particular semiconductor chips after wafer dicing has taken place.
It should now be apparent that a sorting fixture and a testing and sorting system capable of carrying out the stated objects has been provided. The sorting fixture selects nondefective objects, such as semiconductor chips, from defective objects of the same type on a batch basis without requiring individual, serial handling of the selected objects. The system allows an array of semiconductor chips or other objects to be tested, the results of the tests to be stored, and the nondefective objects to be selected from the array on a batch basis, all while maintaining a predetermined sequence and! direction or orientation ofthe selected objects. These capabilities allow the fixture and system to be employed in the high volume production of even the most complex integrated circuit semiconductor chips. Handling of such chips, which cannot be oriented using vibratory bowls, is made possible on a high volume production basis, because the necessity for reorientation during handling on the one hand or individual, serial chip handling on the other is eliminated.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
What I claim is:
1. An apparatus for selecting objects from an array having a desired characteristic from those having an undesired characteristic, comprising:
A. means for holding the array of objects,
B. a matrix adapted to be positioned over said means for holding the array of objects, said matrix having a location corresponding to each object in the array, and
C. individually actuable means for picking up selected ones of the objects while maintaining a predetermined orientation of the selected objects, one of said individually actuable means for picking up the objects being provided at each location in said matrix.
2. In combination:
A. an apparatus for selecting objects as in claim 1,
B. means for determining a characteristic of the objects in the array,
C. means connected to said means for determining a characteristic for storing the determination of the characteristic of the objects in the array, and
D. means operatively connecting each of said individually actuable means for picking up the objects and said means for storing the determination of the characteristic of the objects for selective actuation of said means for picking up the objects.
3. The combination of claim 2 in which the objects are semiconductor chips.
4. The apparatus of claim 1 in which the objects are semiconductor chips.
5. An apparatus for sorting semiconductor chips comprismg:
A. a dicing block for separating a semiconductor wafer adhesively mounted thereon into an array containing a plurality of semiconductor chips adhesively mounted thereon,
B. a matrix engageable with the dicing block to be precisely positioned over a semiconductor wafer diced into an array of adhesively mounted chips on said dicing block, the matrix having a location corresponding to each diced semiconductor chip,
C. means for maintaining each chip at its corresponding lo cation in the matrix and in a predetermined direction of orientation after separation from said dicing block, and
D. an individually actuable vacuum means for picking up the chip at each matrix location after separation from said dicing block while maintaining each chip in a predetermined direction of orientation with respect to other chips selected from the array.
6. The apparatus of claim 5 in which the matrix allows the chips adhesively mounted on said dicing block to be contacted with a solvent for the adhesive to separate the chips from said dicing block.
7. The apparatus of claim 6 in which the chips have a plurality of contacts extending above the chip surface and the means for maintaining each chip at its location in the matrix and in a predetermined direction of orientation is a projection on the vacuum means which extends toward the chip surface within the distance the contacts extend above the chip surface when the matrix is engaged with the dicing block.
8. the apparatus of claim 6 in which the means for maintaining each chip at its location in the matrix and in a predetermined direction of orientation is a plurality of members extending between each chip at its location in the matrix and projecting beyond the vacuum means.
9. In combination:
A. The apparatus for sorting semiconductor chips of claim B. a tester for measuring a characteristic of the chips in the array,
C. means for connecting each chip in the array to said tester,
D. means for storing the measurement of the characteristic for each chip in the array and its location in the array, and
E. means operatively connecting each of said vacuum means and said means for storing for selective actuation of said vacuum means in accordance with the stored measurements.
10. A system for testing and sorting an array of objects in a predetermined direction of orientation, based on their individual characteristics comprising:
A. a tester for measuring a characteristic of the objects in the array while maintaining the objects in a predetermined direction of orientation,
B. means for storing a result based on the characteristic measured by the tester for each object in the array and its position in the array,
C. a sorting means for simultaneous batch separation of objects in the array having a desired characteristic from those having an undesired characteristic while maintaining the ob ects having the desired characteristic in a predetermined direction oforientation, and
D. means engageable by the sorter for receiving the objects in the array having a desired characteristic from the sorter while maintaining the objects having a desired characteristic in a predetermined direction of orientation.
11. The system of claim 10 in which the objects are semiconductor chips.
12. The system of claim 10 in which the sorting means comprises a plurality of selectively actuable vacuum means for picking up objects in the array having a desired characteristic.
13. A process for selecting objects from an array having a desired characteristic from those having an undesired charac teristic, comprising:
A. inspecting the objects to determine which objects in the array have the desired characteristic,
B. recording the result of the inspection for each object in the array and its array location, and
C. selecting the objects in the array having the desired characteristic simultaneously as a batch on the basis of the stored inspection results while maintaining a predetermined direction of orientation of the selected objects.
1a. The process of claim 13 in which the objects are semiconductor chips.
15. The process of claim 14 in which the semiconductor chips are integrated circuit chips.