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Publication numberUS3588852 A
Publication typeGrant
Publication dateJun 28, 1971
Filing dateDec 26, 1967
Priority dateDec 26, 1967
Publication numberUS 3588852 A, US 3588852A, US-A-3588852, US3588852 A, US3588852A
InventorsThomas L Mccormack, Maurice A Morin, Donald T Staffiere
Original AssigneeCambridge Memory Systems Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory assembly
US 3588852 A
Abstract  available in
Previous page
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Claims  available in
Description  (OCR text may contain errors)

United States Patent 72] lnventors Thomas L. McCormack 56] References Cited ghehriisfogdiilflssay h v H D Id UNITED STATES PATENTS as 2 926 340 2/1960 Blain et a1 340/174 T. Staffiere, Wilmington, Mass. pp No 699,284 3,026.494 3/1962 Andersen et al 339/17 [22] Filed Dec. 26, 1967 Primary ExaminerStanley M. Urynowicz, Jr. [45] Patented June 28, 1971 Atrorney-Kenway, Jenney & Hildreth [73] Assignee Said -\lorin and said Stafiiere assignors to Cambridge Memory Systems, Inc. Farmington, Mass. ABSTRACT: An assembly of vertically stacked magnetic memory planes and a process formanufacturlng this assembly. Each plane has a matrix of memory elements laid out on x and y coordinates with the drive conductors brought out to the edge of the planes as printed strips. Each row on each plane is serially interconnected with the corresponding rows on the [54} MEMORY M F remainder of the planes by connecting wires soldered into 5 mums 6 D'awmg Figs slots cut into the printed connectors at each edge. The entire [52] 0.8. CI 340/174, assembly is maintained in registration by vertical registration 317/101, 174/68.5, 339/17, 29/604 posts. The assembly can be manufactured using a process in [51] lnt.Cl. Gllc 5/08, which all of the connections on a side of the assembly are Gllc 5/04 wave soldered simultaneously in one operation. A storage [50] Field of Search 340/174; capacity of 6X10 has been achieved in a 10"X10" 5%' block.

PATENTEDJUN28|97| 3,588,852


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THOMAS L. MCCORMACK MAURICE A. MORIN BY DONALD "r. STAFFIERE (I WYW I ATTORNEYS MEMORY ASSEMBLY FIELD OF THE INVENTION This invention relates in general to printed circuit memory planes and more particularly to a magnetic core memory assembly having vertically stacked memory planes and to a process for manufacturing this assembly.

BACKGROUND OF THE INVENTION Under present technology, a matrix of interconnected magnetic cores may be formed as a printed circuit on an insulating circuit card or plane. A number of these planes are then integrated into one assembly by stacking them in closely spaced superimposed relationship. On each plane the magnetic cores are arranged in columns along one coordinate and rows along the other. Each column of cores on a plane must have a separate drive winding, as must each row. The columns in vertical alignment of each of the planes are serially interconnected, as also are the vertically aligned rows. In addition, each plane must have a sense winding and an inhibit winding which passes through all of the cores on that plane.

In the earlier design of these memory arrays, the electrical connections to and between planes were achieved by at taching lugs to the individual lines of the memory plane and then providing wired solder connections from lug to lug. More recent techniques have included the use of special edge connectors which are soldered together or used with mating components. Multiple circuit board arrays also have been interconnected by means of holes passing through the boards with conducting studs driven through the holes or electrodeposited conducting material built up through the holes.

There are a number of important design criteria for these memory arrays. These include information storage density, economy and reliability. High information storage density requires minimum spacing and hence imposes dimensional criticality. Thus, in order to keep the spacing at a minimum all of the tolerances in the system must be tightly controlled. This problem is particularly critical in dealing with matching connectors. In those methods where hand soldering and connectors are used the individual operations required for the manufacturing process make a high capacity storage array uneconomical to manufacture. It is very advantageous from a cost viewpoint to have an assembly which may be massed produced or automatically assembled, at least in some steps of the process. Both attempts to minimize spacing in order to achieve higher information storage density and attempts to mass produce the necessary connections tend to adversely affect the reliability characteristic of the resultant array. Thus faulty soldering joints or inexact matching of connector points results in either actual or incipient failures at some storage point in the memory.

SUMMARY OF THE INVENTION The memory matrix of the present invention is formed as an assembly of vertically stacked memory planes. lnterposed between each of the planes is an insulating spacer which extends around the periphery of the stack in a position slightly recessed from the edges of this tack. The spacers are sealed to their adjacent memory planes thereby sealing the interior of the memory matrix. On each individual memory plane printed circuit conductors are carried to the edges of the plane and the stack of planes is maintained in registration by means of vertical posts such that the printed conductors at the edge of each plane are in precise vertical alignment. Slightly flattened wires are soldered into slots cut into each of the conducting strips at the edge of the planes. The wires at any one side of the stack extend between only two planes before being interrupted and then extend between another two planes before again being interrupted. This sequence is continued down the side of the stack for each conductor position on the plane. Thus, on one side, only every other interplane space is bridged by a conductor. On the opposite side of the stack, wires are similarly positioned except that they interconnect planes of?- set from those on the original side, with the result that the interplane spacers not bridged by conductors on one side, are bridged by conductors on the opposite side. The remaining two sides of this stack have similarly positioned connecting wires. Located at the top and bottom of the stack are printed circuit connector boards which terminate in a series of printed conductors suitable for attachment of spring clip type connectors.

The memory matrix described above is constructed in the following manner. The stack of printed circuit memory planes with interplane spacers is assembled in vertical registration on the support posts and slots are cut into the edges of the boards at each printed conductor position. The stack is then disassembled and any residue from the cutting operation cleaned off the boards before reassembly. After reassembly with the spacers sealed into position, flattened tinned wires are strung through each of the aligned slots the entire height of the stack. Each side of the assembly is fluxed and then soldered in a wave or fountain soldering technique using a soldering machine such as those manufactured by Hollis Engineering Company of Nashua, N.H. After soldering, the entire assembly is cleaned in an ultrasonic degreaser. Using this solder ing technique, wires 0.005 inches thick, spaced only 0.025 inches between centers may be soldered without causing any shorting between adjacent wires. After the soldering and degreasing operation, the wires are sawed at every other interplane spacing on one side of the stack and sawed similarly on the opposite side of the stack and sawed similarly on the opposite side of the stack. However, in the latter case the positions of the cuts are offset by one interplane spacing from those on the original side.

Using the above-described process, memory matrices have been constructed having a storage capacity in excess of 6X 1 0 bits with a plane dimension of approximately l0"Xl0" and a stack height of approximately Szinches. In such an assembly, each side has approximately 3,000 individual solder connections, yet all of the connections on each side may be soldered simultaneously in one operation.

BRIEF DESCRIPTION OF THE DRAWING I viewed on the opposite side of the assembly from the view of FIG. 5.

portion of the assembly of DESCRIPTION OF THE PREFERRED EMBODIMENT With reference now to FIG. 1, there is shown a perspective view of a magnetic core memory assembly embodying the principals of this invention. A plurality of individual memory planes II are stacked in closely spaced vertical superposition between an anodized aluminum top plate 12 and a similar bottom plate 13. Each of the memory planes 1] is a printed circuit card, typically formed of a glass epoxy laminate having a thickness of approximately 0.030 inches with circuitry printed on the top side only. The circuits themselves are a matrix of magnetic cores with columns along the x axis and rows along the y axis. Each x-axis row has a printed drive conductor extending through all of the cores and out to the edges of the plane. Similarly each y-axis column has a drive conductor passing through all of its cores and extending out to the edges of the plane. In addition, there are printed circuit sense andinhibit windings which pass through all of the cores on the plane.

At the top and bottom of the assembly between the memory planes 11 and the covers 12 and 13 are x-axis connector boards 17 and y-axis connector boards 14. The .x-axis connector boards 17 provide for electrical connection to the x-axis row conductors, while the circuit board connectors 14 provide for external electrical connection to the y-axis column conductors. Connectors boards 17 are spaced from the memory planes 11 by means of a spacer 18. again formed of an insulating board material. and having a thickness of approximately 0.250 inches. These spacers 18 are recessed back from the edge of the boards in order to permit the edges of the connector boards 17 and 14 to be engaged by external connectors (not shown). The individual memory planes 11 are separated from one another by glass epoxy laminate spacers not shown) approximately 0.015 inches thick. The entire assembly is held in vertical alignment by a series of registration posts 15, on which the entire assembly is stacked and which are externally smooth columns held to close tolerances, with internal threading to permit attachment to the upper and lower cover plates.

FIGS. 2 and 3 illustrate in detail the mechanical and electrical interconnections between the memory planes 11. The memory planes 11 are supported upon one another by means of a relatively thin strip of spacer 28, which extends around the periphery of each plane. The spacer is formed, typically, of glass epoxy laminate of 0.0l-inch thickness and width of approximately %inches. The spacer is recessed about 0.060 inches from the edge of the board is sealed to both the board below it an above it with a sealant adhesive. Additional strips of spacer material may be included between the planes, as indicated by the dotted lines 33 in FIG. 3, in order to improve the structural characteristics of the assembly.

The electrical interconnection between the planes is most clearly illustrated in FIG. 2. Each of the planes 11 has printed conductor strips 21 carried to the edge. These conductor strips are normally formed of copper using well-known techniques, such as etching the copper cladding on a board to leave insulating strips alternating with conducting strips. At one side of the assembly, pairs of planes are interconnected by means of interconnecting wires 24 soldered into slots 22 which have been cut into the edges of the boards and the conducting strips 21. ln FIG. 2, one such slot 22 is illustrated without the interconnecting conductor for purposes of exposition. The connecting wires 24 are formed by flattening round tinned copper wire so that the wire cross section conforms closely to the section of the slots 22. Typical dimensions for the spacing between centers of the slots is 0.025 inches. Under these circumstances, the connecting wires 24 may be formed of 0.0l0-inch diameter wire flattened to have a width of 0.005 inches and a length of approximately 0.0 l 7 inches. In the portion of the assembly illustrated in FIG. 2, memory planes 11d and 11: are shown interconnected, while a new set of connecting wires 24 starts at planes 11f. At the opposite side of the matrix assembly, the construction is similar except that the connecting wires 24 there interconnect planes 11c and 11f without an electrical connection at that side between planes 11d and 11a.

The planes in the assembly are interconnected on all four sides in similar fashion, with the overall result that each x-axis row is connected in series with all of the remaining x-axis rows in vertical alignment with it and each of the y-axis columns is serially connected with all of the other y-axis columns in venical alignment with it.

In order to make the necessary connections between the memory matrix assembly and external circuitry, the conductors on the memory planes are connected to specially con structed printed circuit connector boards 14 and 17. There are a pair of x-axis connector boards 17 located at the top and bottom of the assembly and similarly there are a pair of y-axis connector boards 14 located at the top and bottom of the assembly. Each of these connector boards is identical and the configuration of the boards is illustrated in H6. 4. While the illustration is shown broken in the center portion, it should be understood that the board 17 is generally square. The boards are formed of copper clad glass filled epoxy board 0.025 inches thick. The cladding is applied to both surfaces of the board and both surfaces have circuits etched on them.

Circuit board 17 has one edge 37 which is intended to mate with a matching connector. This edge 7 has square-shaped notches 46 cut therein to form a pair of connector tongues 36. Edge 38 of circuit board 17 lies opposite to edge 37 and is straight along its entire length. as is edge 40. The remaining edge 39 is cut back most ofits length. The cutback on edge 39 corresponds with the position of the tongues from the y-axis board 14 which would directly overlie it and permits access of a connector (not shown) to the tongues on the y board 14. On the right-hand edge of board 17, the copper has been etched to form a series of conductor pads 42 with the distance between centers of each of the conductors 42 being 0.025 inches. On the upper surface, as shown, every other one of the conductors 42 is an open connection. The remainder of the conductors on this surface are connected to a series of conducting pads 44 on the opposite edge 37. The conducting pads 44 on edge 37 have a separation between centers of 0.050 inches.

The circuit pattern on the lower surface (not shown) of board 17 is identical to that on the upper surface except that conductors corresponding to the open end conductors on the upper surface are actually carried through to conducting 44 at edge 37, while the conductors 42 at edge 38, corresponding in position to those conductors which ran the length of the board on the upper surface, are open ended on this lower surface. On the lower surface, at edge 37, the conducting pads are again set with a separation of 0.050 inches between centers and are aligned with the conductors at this edge on the upper surface. This connector board then has a series of cut conductors on edge 38 set on 0.025-inch centers, which are carried on both surfaces of the board to a series of conductors on the opposite edge 37, with these latter conductors set at 0.050 inches between centers. This board then permits external connectors with conducting points separated by 0.050 inches to be used for connecting to the memory plane connecting wires set at 0.025 inches on center.

In FIGS. 5 and 6, the matrix assembly is shown in sufficient detail to illustrate the interconnection between the connector boards 17 and the memory planes 11. In FIG. 5 this portion of the assembly is shown from the tongue edge 37 of connector board 17. The cover plate 12 has been removed in order to show the detailed construction. Connector board 17 is supported by spacer 28' from connector board 14. The tongue portion 36 of board 17 is positioned above the side edge 40 of the y-axis connector board 14. A spacer element 18, formed of glass filled epoxy board, supports the connector boards 14 and 17 above the memory planes 11. This spacer 18 has a thickness of approximately 0.250 inches in order to provide sufficient clearance under the tongue 36 of the connector board 17 for an external connector to make contact to the conducting pads 44 on the lower surface of the connector board. The memory planes 11a and 11b are electrically interconnected by the flattened connecting wires 24, which are soldered to the conducting strips 21 on both memory plane and memory plane 11b. These wires 24 are then interrupted, so that there is no electrical connection, at this edge, between planes 11b and Us. The wires 24' interconnect planes 11c and 1 1d.

HO. 6 is an illustration of the assembly viewed from the opposite side, that is, looking at edge 38 of connector board 17 On this side of the memory stack the spacer 18 has its edge flush with the edges of connector boards 17 and 14, as well as the edges of the memory planes 11. The printed conductors 42 on the upper surface of connector board 17, at this edge, are spaced 0.025 inches on center and those conductors designated 42a are open ended. Connecting wires 25 are soldered into the slots in conductor strips 42 and 42a on board 17. These connecting wires are soldered to the printed conductors on both the upper and lower surface of board 17. The wires 25 pass over the edge of connector board 14 without being attached to this board and similarly pass over the edge of spacer l8 and are again soldered into slots along the edge of memory plane lla. These wires are then interrupted and memory planes 1 lb and He are electrically interconnected at this edge by wires 26 soldered into slots, as described above on the edges of these planes.

With this arrangement. the conducting pads 44 on the tongue edges of connector board 17 are electrically connected through the printed circuit strips to conducting pads 42 on the opposite edge of the connector board 17 and then through connecting wires to the conductor strips 21 on the first memory plane lla. The conducting strips 21 on memory plane lla pass through the magnetic cores (not shown) formed on the x-axis rows on the memory plane and are then connected at the opposite side of the stack through wires 24 to the conducting strips 21 on plane 1 lb. These conducting strips on plane lib then transverse through the cores on that plane back to the side of the stack shown in FIG. 6 and are then connected through wires 26 to the conducting strips on plane 11c. This wiring pattern is reitinerated down through the stack and terminates in the x-axis conductor board 17 at the bottom of the stack. The y-axis configuration is identical, however, the conducting leads in this instance pass through the cores on the y-axis columns.

A memory array as described has been constructed with each plane being approximately l0" l0 and, with the spacing indicated in the above description, the entire height of a I00 plane array is approximately S'rinch. Each plane had 288 conducting strips as drive leads along each edge. Of these, 256 are connected, so that each plane has 256 rows and 256 columns or a total bit capacity (connected) of 56,336 bits. For a 100 plane array, then, the total bit capacity is approximately 65x10. The extra 22 leads on each coordinate of the plane provide spare rows and columns in the memory. Thus, if there is any electrical failure in the internal printed circuitry, changes can be made in the connectors to substitute a spare row or column for the inoperative one.

The matrix assembly described may be manufactured according to the following process. The connector boards and memory planes are first manufactured using conventional printed circuit techniques with the holes for the registration posts carefully registered with the conductor strips on the edge of the boards. The planes and connectors are then assembled on the registration posts with temporary top and bottom covers. A diamond wheel 0.005 inches thick is used to cut a slot 0.017 inches deep into the center of each of the printed conductors along the edges of the memory planes and along the back edge 38 of the connector boards. The array is then disassembled and cleaned with an alcohol and water flush to remove the particles used in the cutting operation on the boards. After this initial cleaning, the entire array is reassembled with the permanent top and bottom cover plates in place. In this assembly, the interplane spacers are sealed with an adhesive sealant to the planes immediately above and below them. The flattened connecting wires are then strung in the vertically aligned slots and each of the sides of the assembly is fiuxed either with a flux bath or by coating the flux onto the sides.

The next process step is the wave soldering whereby each of the connecting wires is soldered to the conducting strips at the edge of the planes and connector boards. Wave soldering is a technique in which the surface to be soldered is passed through a fountain of molten solder having an oil film at the top. This is done with a conventional 60-40 lead tim solder at a temperature between 450 and 500 F. The oil film on the upper surface of the solder fountain gives the effect of wiping bridges of solder from between the connecting wires. The spacers sealed between the planes prevent the flux or oil from reaching the internal circuitry of the matrix assembly and contaminating it.

After the soldering operation the entire assembly is cleaned in an ultrasonic degreasing bath. The connecting wires are then cut at alternate inte lane spacings. For the purpose of cutting these wires a carbi e circular saw lbmches in diameter, attached to a high speed drill and mounted on a lathe bed has been successfully used.

Having described the invention various modifications and improvement will appear to those skilled in the art and the invention should be construed as limited only by the spirit and scope of the appended claims.

We claim:

1. A magnetic core memory assembly comprising:

a plurality of printed circuit memory planes disposed in closely spaced superimposed relation, each of said planes being formed with a matrix of memory elements distributed in rows and columns along x and y coordinates, each of said rows and columns having printed drive conductors extending to the edges of said planes, said printed drive conductors being slotted at the edges of said planes;

electrically insulating spacers interposed between each of said planes, said spacers extending around the entire periphery of said assembly in a position recessed from the edges of said planes, but outside of said matrix of memory elements, said spacers being sealed to both adjacent planes along the entire lengths of said spacers, thereby enclosing said matrices within sealed volumes;

said planes being supported in vertical registration such that said slots in said drive conductors for each of said rows and columns are in vertical alignment; and

wires fitted into said slots and soldered to said printed conductors for connecting on each side of said assembly, alternate pairs of memory planes, the planes connected in pairs on one side of said assembly being offset by one plane from the planes connected as pairs on the opposite side of said assembly.

2. A memory assembly in accordance with claim 1 wherein said planes are maintained in vertical registration by means of support posts passing vertically through said plurality of circuit planes at spaced-apart positions.

3. A memory assembly in accordance with claim 1 and further including first and second x-axis connector boards and first and second y-axis connector boards, said first x-axis connector board and said first y-axis connector board being positioned above the uppermost memory plane on said assembly and said second x-axis connector board and said second y-axis connector board being positioned below the lowermost plane in said assembly, each of said connector boards having a tongue portion on one edge thereof, said tongue portions including a first set of printed circuit conductors on both surfaces for providing a series of discrete electrical contacts to an external electrical connector, each of said connector boards having a second set of printed conductors on both surfaces extending to the edge of said board opposite to said tongue section, a1- temate ones of said second set of conductors being electrically connected to said first set, the separation between said printed conductors in said second set being substantially identical to the separation between said printed drive conductors on said circuit planes, said printed conductors in said second set being slotted at the edge of said connector boards, and

connecting wires fitted into said slots and soldered to said connector board conductors and into said uppermost circuit plane conductors, thereby providing electrical connection for said drive conductors to external electrical connectors.

4. An assembly in accordance with claim I wherein each of said circuit planes is formed on an insulating board substantially 0.030 inches in thickness and wherein each of said spacers is an insulating board substantially 0.0l5 inches in thickness and 0.025 inches between centers.

5. A memory assembly in accordance with claim 4 wherein lOO of said circuit planes are included and wherein each said circuit planes include at least 256 memory elements.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3895359 *Apr 15, 1974Jul 15, 1975Siemens AgStorage matrix construction
US4288841 *Sep 20, 1979Sep 8, 1981Bell Telephone Laboratories, IncorporatedDouble cavity semiconductor chip carrier
US4984358 *Jun 18, 1990Jan 15, 1991Microelectronics And Computer Technology CorporationMethod of assembling stacks of integrated circuit dies
US5191404 *Sep 30, 1991Mar 2, 1993Digital Equipment CorporationHigh density memory array packaging
US5247423 *May 26, 1992Sep 21, 1993Motorola, Inc.Stacking three dimensional leadless multi-chip module and method for making the same
US5249355 *Oct 31, 1991Oct 5, 1993Hughes Aircraft CompanyMethod of fabricating a multilayer electrical circuit structure
US5249973 *Jul 7, 1992Oct 5, 1993Sumitomo Wiring Systems, Ltd.Card type junction box
US20130319759 *May 31, 2012Dec 5, 2013General Electric CompanyFine-pitch flexible wiring
WO1981000949A1 *Aug 13, 1980Apr 2, 1981Western Electric CoDouble cavity semiconductor chip carrier
U.S. Classification365/55, 439/55, 29/830, 174/263, 365/66, 361/679.31, 29/604
International ClassificationG11C5/08, G11C5/04
Cooperative ClassificationG11C5/08, G11C5/04
European ClassificationG11C5/08, G11C5/04