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Publication numberUS3593161 A
Publication typeGrant
Publication dateJul 13, 1971
Filing dateDec 6, 1968
Priority dateDec 20, 1967
Also published asDE1815768A1, DE1815768B2, DE1815769A1, DE1815769B2, DE1815770A1, DE1815771A1, US3568022
Publication numberUS 3593161 A, US 3593161A, US-A-3593161, US3593161 A, US3593161A
InventorsRitz Gerold
Original AssigneeBosch Gmbh Robert
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Pulse coincidence detection circuit
US 3593161 A
{PG,1 Simultaneous pulses occurring in two or more pulse trains are suppressed, and only discretely appearing pulses of a minimum time separation are propagated. A circuit detects coincidence, by time-extending a pulse representative of the inverse of the logical conjunction of both pulses. The time-extended, inverted pulse is used as an information signal indicative of noncoincidence to control AND gates to another input of which, the pulses, regenerated from the trailing edges of the pulses of the pulse trains, are applied.
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Description  (OCR text may contain errors)

United States Patent Gerold Ritz, deceased late of Stuttgart, Germany; Erika Ritz, Gerold Ritz and Anna Ritz, all

Inventors legal successors, all of Tiengen, Hochrhein,

Germany Appl. No. 782,009 Filed Dec. 6, 1968 Patented July 13, 1971 Assignee Robert Bosch GmbII Stuttgart, Germany Priority Dec. 20, 1967 Switzerland 1801 1/67 PULSE COINCIDENCE DETECTION CIRCUIT 6 Claims, 3 Drawing Figs.

US. Cl 328/109, 307/232, 307/234, 328/110 H031; 5/20 307/232,

References Cited UNITED STATES PATENTS Olson Gauthey .1 Krause Metz Nourney Nourney Primary Examiner-Stanley D. Miller, Jr. Attorney Stephen H. Frishauf MONOSTABLE MULTIVIBRATOR) AND 90 NAND 592 MONOSTABLE 8 108.12 69 MULTIVIBRATORS @F' wisest es m 9-, Q A. 148.16


EW 1% m ml F INVENTOR! 6ap 2/72 10116 -h COINCIDENCEGATE mm M II- $931.1

PULSE COINCIDENCIE DETECTION CIRCUIT The present invention relates to a circuit recognizing when one or more pulses is (or are) coincident with another pulse, and more particularly to such a circuit in which the output therefrom is suppressed upon detection of coincidence. The circuit will be described particularly in connection with a digital system to control the slip frequency of an asynchronous dynamoelectric machine, and forming the subject matter of our application Ser. No. 782,008 filed concurrently herewith, and assigned to the assignee of the present invention.

When pulses commanding respectively reversed count directions are to be applied to a bidirectional digital counter, for example a forward-backward counter, pulses applied to one input of the counter tend to cause the counter to count, for example, forwardly; while pulses to the other counter input cause counting in the opposite direction. Application of pulses to both inputs simultaneously, or with time overlap, should be avoided; even if applied, a forward" count pulse would have no effect on the ultimate count state if cancelled by a backward" count pulse; the counter will thus show a substantially steady state count varying, or hunting about a value of zero. To avoid malfunction, overlapping or coincident pulses, or pulses having a time separation below a predetermined value are, desirably, suppressed. The combination of a coincident pulse-suppressing gate with the counter will be substantially insensitive to noise and stray pulses. Accuracy of a digital arrangement is achieved even by using a counter having only low counting capacity.

It is an object of the present invention to provide a pulse coincidence detection and suppression circuit which is simple and effectively inhibits pulses in pulse trains having time overlap, and which is particularly adaptable for use with bidirectional pulse counters.

SUBJECT MATTER OF THE PRESENT INVENTION Briefly, a NAND gate is provided to detect coincidence of pulses and provide an output which is inverted. The output pulses are time-extended, and provide an information signal which is then indicative of noncoincidence of pulses. The pulses, themselves, are time-extended and the trailing edges of the time-extended pulses of the pulse trains themselves are applied to respective AND gates, controlled by the information signal. The output pulses thus are slightly time-shifted with respect to the input, and separation of the pulses, which do not overlap, is readily obtained by suitable choice of timing of pulse periods of monostable multivibrator circuits in the system.

The structure, organization, and operation of the invention will now be described more specifically with reference to the accompanying drawings, wherein:

FIG. 1 is a schematic circuit diagram of a coincidence circuit to suppress overlapping pulses ofa pair of pulse trains;

FIG. 2 is a timing diagram to illustrate the operation of the circuit of FIG. 1; and

FIG. 3 illustrates a counter coincidence circuit combinatron.

FIG. 1 illustrates the circuit of a coincidence gate 50 (FIG. 3). The function of this circuit is to suppress pulses of a pair of simultaneously arriving pulse trains, which at least partially overlap, that is present time-coincidence. Such a circuit suppresses all pulses having coincident arrival, as illustrated in connection with the graph of FIG. 2.

Beside suppressing the pulse, an indicator circuit (such as a flipflop, the state of which can be sensed) can be triggered.

The coincidence gate of FIG. I has two inputs 53,54 and two outputs v and r. Input 53 has a pulse train 10, and its inverse T6 applied thereto; input 54 has pulse train 12 and its inverse I 2 applied. The pulses are illustrated shaded in FIG. 2, their inverse blank. The notation corresponds to absence of signal, and the notation L" corresponds to line active, that is pressure of a pulse or signal, and generally corresponding to a l in the binary system.

A NAND gate generates pulses I and E from pulse trains 110 and 12, as illustrated in FIG. 2. The leading edge of resultant pulse T6 and 12 triggers a multivibrator 91, having at its output a time extended pulse 15, which is level shifted by z bias or level setting stage 92 about a predetermined potential. The output of stage 92 is a pulse train 16 (FIG. 2). The operation of the bias stage 92 will be obvious from a comparison of pulse trains 15 and 16 in FIG. 2. Pulse train 16 is applied to the inputs of a pair of AND gates 93,94, the outputs of which are applied, each, to a monostable multivibrator 95,96, respectively, and having a short pulse duration t,, (short with respect to the duration of the pulses l0 and 12). The output of multivibrator 95 serves as the v output of the coincidence gate 50, supplying pulses 17 if there is no coincidence and the pulse from input 53 occurs before the pulse from input 54. The output of multivibrator 96 is the r output of coincidence gate 50, delivering pulses 18 if there is no coincidence and the pulse from input 54 occurs before the pulse from input 53.

The inverse pulses III (second row of FIG. 2) trigger, with their trailing edge, a monostable multivibrator 97. Its output pulses 13 are slightly longer than the pulses 10 and are in phase with it. The trailing edges of pulses 13 are differentiated in a differentiating network 98, result in needle or peak pulses 13, and are applied to the second input of AND gates 93. The inverse pulses T2 (fourth row, FIG. 2) trigger, with their trailing edges, monostable multivibrator 99, having output pulses 14 slightly longer then pulses 12 and in phase with it. The trailing edges of pulse 14 are diffe iatad in a differentiating network lllltl, result in needle or peak pulses l4, and are applied to the second input to AND gate 9 3.

The signal at the output of bias stage 92 is an information signal serving to determine that no coincidence of pulses is present. A signal can be is off from stage 92, inverted, and then may serve as a trigger for a monostable multivibrator supplying a pulse indicative of coincidence. Needle pulses 13' or 14 can trigger multivibrators 95 or 96 only when and if signal 16 has enabled AND gates 93,94, in order that an output impulse 17 or 18 is generated.

FIG. 2 illustrated in the first row pulse train 10, seven pulses and in the third row, pulse train 12, six pulses. These, 13 pulses total, have 10 coincident pulses, so that output v delivers only two pulses 17 and output r only one pulse 18. As will be obvious, similar results are obtained in other cases of coincit.' ..:e since, upon coincidence of any .kind, with respect to time, of two pulses, both are suppressed.

The circuit in accordance with FIG. 1 is particularly useful in combination with a bidirectional pulse counter 46 (FIG. 3), of the type having separate forward" and reverse" inputs, because simultaneous activation of both inputs is eliminateda frequent source of malfunction and incorrect counting. Additionally, the outputs that are not coincident can be clearly separated in time further increasing the accuracy of the counter in combination with the coincidence circuit.

FIGS. 1 and 2, and the above description, shows two pulse trains. More inputs can be handled by circuits in accordance with the present invention, by providing additional channels comprising elements similar to multivibrator 97,99 differentiating network 99,100, AND gate 93,94 and output pulse generator circuit 95,96. The NAND gate 90 then is to be constructed as a plural (that is-more than two) input gate, and the information signal 16 applied as the second input to all of the AND gates 93. Other modifications of the circuit, within the scope ofthe inventive concept, will be apparent.

It is claimed:

1. Coincidence gate circuit detecting coincidence of pulses applied to a plurality of inputs (53,54), each input having a pulse train applied thereto;

said circuit having a pair of outputs delivering output pulses if, and only if, the pulses of the pulse trains to the inputs are noncoincident, the respective outputs being activated in accordance with the relative occurrence in time, of said input pulses;

said circuit comprising means (97,99) extending in time, separately, the pulses derived from said inputs and E);

logic means (90) having said pulses (10,12) applied thereto and having an output signal W and 1 1) forming the logical conjunction of the presence of one of said signals only and indicative of no time overlap ofsignals;

circuit means (91) connected to and triggered by the output from said logic means and providing an output information signal (16) of a time duration longer than said input pulses;

conjunctive gates (93,94) having the trailing edges (13,

14') of said time-extended pulses, as well as the information signal (16) applied thereto;

level change means (92) interconnecting said circuit means (91) and said conjunctive gates (93,94), the output of said level change means providing said information signal;

and output means connected each, to a conjunctive gate (93,94), said output means being activated by said conjunctive gates to provide a pulse only if said first monostable multivibrator has no pulse, and simultaneously the trailing edge ofa time-extended pulse is present.

2. Circuit according to claim 1 including further pulse generating means (98,100) responsive, respectively, to the trailing edges of said time-extended pulses, and having their respective outputs connected to said conjunctive gates (93,94).

3. Coincidence circuit according to claim 1 having two inputs, and two pulse trains applied thereto, in combination with a bidirectional pulse counter (46) having a forward count input (v) and a reverse count input (r); one output (17) of said coincidence gate circuit being connected to the forward count input (v), and the other (18) to the reverse count input (r) whereby the operation of said counter (46) is stabilized due to suppression ofoverlapped pulses, and separation of applied pulses by the extension of the pulses tin time.

4. Coincidence gate circuit detecting coincidence of pulses applied to a plurality of inputs (53,54), each input having a pulse train (10,12) applied thereto;

said circuit having a pair of outputs (v,r) respectively activated in accordance with the relative occurrence, in time, of said input pulses, said circuit delivering output pulses (17,18) if, and only if, the pulses ofthe pulse trains to the inputs are noncoincident; said circuit comprising means (97,99) providing pulse trains (13,14) time-delayed with respect to the pulses applied to said inputs;

conjunctive logic means connected to said inputs and providing an output (W and E) upon failure to detect simultaneous application ofinputs; means (91) time-extending said outpuflm and E) to provide a noncoincidence information signal (16);

and output gate means (93,94) responsive a. to said time-delayed pulses (13,14) 14) and b. to said information signal,

said information signal being applied to said output gate means (93,94) to control said output gate means to deliver output pulse trains having pulses only which are not overlapping.

5. Circuit according to claim 4, wherein said conjunctive logic means include a NAND gate (90) detecting simultaneous applications of inputs and providing an output indicative of the negative of said simultaneous application.

6. Coincidence gate circuit according to claim 4 having two inputs, and two pulse trains applied thereto, in combination with a bidirectional pulse counter (46) having a forward count input (v) and a reverse count input (r); one output (17) of said coincidence gate circuit being connected to the forward count input (v), and the other (18) to the reverse count input (r) whereby the operation of said counter (46) is stabilized due to suppression of overlapped pulses and separation of applied pulses by the time delay ofpulses.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2867724 *Nov 23, 1956Jan 6, 1959Gen Dynamics CorpControl circuit
US3019350 *Oct 21, 1957Jan 30, 1962IBM France CompanyGauthey
US3112450 *Aug 15, 1962Nov 26, 1963Bell Telephone Labor IncPulse resolution circuit with gated delay means and flip-flop providing selective separation between random inputs
US3192478 *Oct 26, 1962Jun 29, 1965Beckman Instruments IncBidirectional counter adapted for receiving plural simultaneous input signals
US3268743 *Sep 16, 1964Aug 23, 1966Hewlett Packard CoPulse time-relationship detector employing a multi-state switching circuit
US3327226 *Nov 16, 1964Jun 20, 1967Hewlett Packard CoAnticoincidence circuit
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3710265 *Apr 1, 1971Jan 9, 1973Howe Richardson Scale CoQuadrature-to-serial pulse converter
US3906378 *Jun 26, 1974Sep 16, 1975Eisai Co LtdElectronic circuit for eliminating coincidental signal from hybrid signals
US3922610 *Jan 28, 1974Nov 25, 1975Basf AgPulse anti coincidence methods and circuits
US4155045 *Aug 29, 1977May 15, 1979Telefonaktiebolaget L M EricssonMethod and apparatus for detection of phase difference between two electrical signals
US4502014 *Nov 24, 1982Feb 26, 1985Rca CorporationCoincident pulse cancelling circuit
US4763025 *Mar 10, 1986Aug 9, 1988Diesel Kiki Co., Ltd.Frequency discrimination circuit
DE2627713A1 *Jun 21, 1976Jan 13, 1977Western Electric CoSchaltungsanordnung zur feststellung der identitaet zwischen zwei bit-impulszuegen
U.S. Classification327/22, 327/43
International ClassificationB60T8/172, H02P23/06, H03K21/02, H02P27/04, G06F7/60, B60T8/17, H02P23/08, B60T8/1761, H03K5/22, B60L9/18, H02P27/16, H03K21/00, H02P3/18, H03K5/00, B60L9/00, H03K5/24
Cooperative ClassificationC10M2215/086, B60T8/17613, C10M2203/10, C10M2223/045, H03K21/02, C10M2217/046, C10M2217/06, H02P23/065, C10M2215/28, C10N2210/02, H03K5/22, C10M2219/046, H02P3/18, C10M2219/044, C10M2215/04, H03K5/24, C10N2240/08, G06F7/605, B60T8/172, H02P23/08, C10N2240/06, C10M2205/06, H03K5/00006, C10M2215/26
European ClassificationH03K5/00C, H02P23/08, H03K5/22, H03K5/24, H03K21/02, H02P3/18, B60T8/1761B, G06F7/60H, B60T8/172, H02P23/06B