US 3600667 A
Description (OCR text may contain errors)
United. States Patent  Inventor William D. Wynn  References Cited Lake 1 UNITED STATES PATENTS 3; Q A' 35 3 2 1969 3,096,475 7/1963 Brooks 323/22 (1) m d 17'1971 3,350,628 10/1967 Gallaheret al. 323/4 1 e 3,408,559 10/1968 Bambace et al. 323 22 (T)  Assignee The United SlatesofAmerlcaas 3 417 321 12/1968 Cl 323,22 T
mined by'the Secretary of the Army 3,509,448 4/1970 Bland 323/22 x (T) Primary Examiner-Gerald Goldberg POWER SUPPLY HAVING PARALLEL Attorneys-Harry M. Saragovitz, Edward J Kelly, Herbert DISSIPATIVE AND SWITCHING REGULATORS Ber] and Aubrey J, Dunn 1 Claim, 1 Drawing Fig.
521 US. Cl 323/22 T, 307/242, 307/297, 323/25 ['5 i] Int. Cl. G05! 1/56 ABSTRACT: The parallel combination of a dissipative-type  Field of Search 323/4, 9, regulator and a switching-type regulator is controlled by a dif- 7 16-25; 307/242, 297 ferential amplifier to provide steady state power to a load.
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l' 1: i I g 2 4 I fig FILTER 1 /Q2 I J P0 HER SOURCE I LOAD R8 \R6 5 1 Al LEE] R7 8 POWER SUPPLY HAVING PARALLEL DISSIPATIVE AND SWITCHING REGULATORS SUMMARY OF THE INVENTION A This invention relates to a low voltage-high current regulated power supply having high efficiency and a fast response time. To achieve the desired parameters, advantages is taken of the advantages of both the series or dissipative-type of regu later and theswitching-type of regulator. The series or dissipative-type of regulator offers a fast response time at the sacrifice of efficiency while the switching-type of regulator offers high efficiency at the sacrifice of response time.
To provide a power supply with the advantages of both types of regulators without the disadvantages of either, both types are used simultaneously with the outputs paralleled. Both regulators are chosen to be capable of supplying the entire load alone. The switching-type of regulator is connected as a slave to the dissipative regulator. When the current through the dissipative regulator exceeds a predetermined low level, the output from the switching regulator will increase until it is supplying the major portion of the load current. The dissipative regulator supplies current at a fast response time. The switching regulator then assumes the load current, supplying it more efficiently than does the dissipative regulator.
BRIEF DESCRIPTION OF THE DRAWING present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the drawing, under steady state conditions, all but a small percentage of the power to load is supplied through switching transistor Q3. Duty cycle control 2 switches Q3 at a fixed rate with the on time being varied as required to deliver a predetermined average voltage from power source 4 to the filter formed by inductor L1 and capacitor C1. A small keep alive current flows through transistor Q1 and constitutes the small percentage of the power to the load that is not supplied through switching transistor Q3. Amplifier Al compares the output voltage to a voltage provided by the voltage reference circuit 8 and provides an error correction signal to Q1. The output voltage signal, provided to amplifier Al, is reduced by voltage dividers R6 and R7 to a level compatible with the reference voltage. Q1 then changes the power delivered to the load until the output voltage is correct and the error signal at the input to Al is near zero. Voltage reference circuit 8 may be any device for establishing a voltage reference, Le, a zener diode. A small resistor R1 is placed in series with the output of transistor QI. Any increase or decrease in the voltage across R1 is sensed by amplifier A2 through resistor R2. Resistors R1, R2, and R3 comprise a voltage divider which, under steady state conditions, establishes a zero differential input voltage at the input of A2. During this steady state condition the current through R1 would be equal to that predetermined keep alive" current supplied through Q1.
T1 and Q4 may be considered as a blocking oscillator, but with one important difference. That difference is that the core in T1 has a very square-type hysteresis loop, preferably with a Br to Bm ratio of approximately 90 percent. Winding D of transformer T1 is a reset winding. Circuit action is initiated by a pulse from pulse generator 6, any state of the art device for delivering a pulse having a predetermined pulse repetition rate. This pulse causes O4 to saturate. With Q4 saturated, the input DC voltage causes current to flow through winding A of transformer T1 to provide outputs from windings B and C of transformer T1. The output from winding B locks Q4 in saturation. The output from winding C of T1 causes power switch Q3 to saturate and deliver power to-the LC filter composed of inductor L1 and capacitor C1. Q4 conducts until T1 saturates. When t-Tl saturates, the outputs from windings B and C of T1 reduce to zero and Q3 and Q4 cease to conduct, thus ending the power pulse. The resultant rise in collector voltage on Q4 will cause O5 to saturate and begin a reset cycle for T1. The extent to which the core is reset is determined by the time between the end of a power pulse and the beginning of the next power pulse and the DC level supplied by A2. The DC level supplied by amplifier A2 is in turn controlled by the current through R1.
An increase or decrease in the output load current from the predetermined steady state value will cause a change in voltage at the input of A2. This voltage at the input of A2 will cause the output of A2 to increase or decrease, respectively, to thereby adjust the on" time of transistor Q3. By varying the on time of Q3, the average power supplied to the load is regulated.
A sudden increase in load current, a decrease in load voltage, will be sensed by A1. Q1 will be biased on" to supply the increased load current. The change in the voltage across R1 will be sensed by A2 and the on time of Q3 adjusted to supply current to the load and increase the output voltage until Q1 reduces its output back to the predetermined maximum value. Rectifier CR2 is provided to bypass sensing resistor R1 when vary large load steps occur. Capacitor C2 and resistor R5 determined the particular transfer function of A2. The response time of A2 must be slow compared with the response time of A1 in order to maintain stability.
In the case of a sudden load removal, Q2, with associated components CR5 and CR6, will act to absorb the energy stored in L1. Q2 is normally biased for very light conduction. In some applications where a small voltage surge upon removal of the load may be acceptable, Q2 may be omitted by making Cl large in comparison to L1. Bias voltage via filter 10 is supplied to A1, A2, and pulse generator 6.
The area 12 comprises essentially the components of a switching regulator while area 14 comprises essentially the components of a dissipative or series-type regulator. I
I claim: 4
l. A regulated power supply comprising:
a dissipative-type regulator;
a switching-type regulator;
a power source; and
first and second load terminals; said dissipative-type regulator and said switching-type regulator being connected in parallel between said power source and said load terminals, wherein: said power source has first and second output terminals; said switching-type regulator comprises:
a first transistor having base, emitter, and collector electrodes;
an inductor connected between said emitter and said first load terminal;
a first differential amplifier having first and second input terminals and a first output terminal, said first input terminal being resistively connected to said first load terminal, said second input terminal being resistively connected to said second load terminal; and
said dissipative-type regulator comprises:
a second transistor having base, emitter, and collector electrodes;
a sensing resistor connected between said emitter of said second transistor and said first load terminal;
a second differential amplifier having first and second input terminals and an output terminal, with its output terminal connected to said base of said second transistor, its first input terminal resistively connected to said first load terminaL-and with its second input terminal resistively connected to said first and second load terminals;
a voltage reference circuit connected between said first input terminal of said second differential amplifier and said second load terminal; said second load terminal being connected to said second output terminal of said power source; said second input terminal of said first differential amplifier being resistively connected to said of said second transistor, said emitter being resistively connected to said 'emitter of said second transistor, and said collector being connected to said second load terminal.