US 3603844 A
Description (OCR text may contain errors)
United States Patent  Inventor Fred A. Fritz 3,316,451 4/1967 Silberman 317/80 llockessin, Del. 3,424,924 1/1969 Leisinger et al. 307/252 1211 Appl. No. 846,398 3,453,496 7/1969 Wright et al. 317/80  Filed July 31,1969 3,541,393 11/1970 Diswood 319/80  Patented Sept. 7, 1971 I  Assignee Hercules Incorporated :77: 'g' g Wilmington, Del. army 1 am Y M LTl ER lNlTlATIN  gtgfgs DELA U P 10D G ABSTRACT: A device for providing electronically delayed 5 Claims, 4 Drawing Figs rnulti ple point initiating current to electrical initiators in blasting circuits is provided. The device has a plurality of firing en-  US. Cl 317/80, wits each f which employs a fi i Capacitor connected to a 317/143-5 silicon controlled rectifier. A plurality of buffer circuits con- [5 l] lnt.Cl F231 7/02 named in parallel are provided, each h g circuit having at  Field of Search 307/ 106-108, least one capacitor which is connected to the 1 gate f a I 12, 252-53, 25154;:317/1485 silicon controlled rectifier of a firing circuit. A timing circuit B, 151, 139, 80; 102/702; 373/275 C; 32 equentially actuates discharge of each buffer capacitor into the gate of the silicon controlled rectifier of a corresponding  Rem-ewes Clad firing circuit whereby the silicon controlled rectifier is made UNITED STATES PATENTS conductive allowing the firing capacitors to discharge into the 3,312,869 4/1967 Werner 317/80 firing circuit.
T- w sT s5 s3 El q 18 c I d I 2 l 1 E3 29 I $4 I TIMING 8i E4 FIRING I 16 I BUFFER CIRCUIT I l I CIRCUIT I 'H I g: s I I 7 E8 (B3) I I K| E9 I I 9 I Il- EN l I 1 I I4\ I 1 I 1- I I (82) I I I I 12 INVERTER o b I 3 POWER SUPPLY I 1 PATENTED SEP 712m SHEET 1 OF 2 FIRING CIRCUIT TIMING 8| CIRCUIT F BUFFER FIG.I
BUFFER CIRCUIT-N TIMING CIRCUIT-N TIMING CIRCUIT-l FIG.2
FRED A. FRITZ INVENTOR ATTORNEY ELECTRONIC DELAY MULTIPERIOD INITIATING SYSTEM This invention relates to an electrical initiating system for explosive charges and more particularly to a multiperiod electronically delayed initiating device for initiation of blasting caps.
An improved method and system for detonating an explosive composition to enhance its explosive characteristics in a borehole is disclosed in U.S. Pat. No. 3,457,859 to R. G. Guenter. This improvement is accomplished by detonating the explosive composition at more than one point along its length within a time interval sufficient to produce more than two coexisting detonation fronts. This technique is now more commonly referred to as multiple point initiation.
Of primary importance in multiple point initiation is the ability of the initiation device to detonate all the caps within a given delay period within about 50 microseconds. This order of detonation simultaneity is required to have the caps detonate the explosive and not vice versa; and have all the caps detonate before this detonation severs lead wires to undetonated caps. The term delay period as used herein is defined as the time interval allowed for any number of preceding charges to be initiated and to act upon their assigned target such as rock areas in order to fragment and move out the rock prior to detonation of succeeding charges.
Delay blasting caps such as short-period delay blasting caps lack the detonation simultaneity within a given delay period required for multiple point initiation and the delay precision required for multiple point initiation. Commercially available switching devices lack the current switching capability required to fire large parallel cap loads generally required in blasting operations.
Accordingly, a primary object of this invention is to provide an electronically delayed multiple point initiating device having the capability to provide for continuous adjustment of the delay intervals between any series of initiations of blasting caps and having high current carrying capacity to reliably initiate large numbers of blasting caps connected in parallel.
Other objects of the invention will appear hereinafter the novel features and combinations being set forth in the appended claims.
Broadly, in accordance with this invention an electronically delayed multiple point initiating device for providing current to electrical initiators of a blasting circuit is provided comprising a) a plurality of parallel connected firing circuits comprising resistance means, blocking diode and capacitor connected in series and a silicon controlled rectifier, said capacitor being charged to potential desired in the blasting circuit when a first switching means is positioned conductive between a first DC power source and the capacitor, said capacitor being connected through the normally open silicon controlled rectifier to the blasting circuit, b) a plurality of buffer circuit means connected in parallel, each buffer circuit comprising at least one capacitor connected to the gate of the silicon controlled rectifier of the firing circuit, said buffer capacitor being charged when a second switching means is positioned conductive between a DC power source and the buffer capacitor, and c) timing circuit means connected to a power source and to each of the bufi'er circuit means for sequentially actuating discharge of the buffer capacitors into the firing circuit whereby the silicon controlled rectifiers in the firing circuit are made conductive thereby sequentially discharging the firing capacitors into the blasting circuit.
Representative embodiments of the invention have been chosen for purposes of illustration and description and are shown in the accompanying drawings wherein:
FIG. 1 illustrates a representative power supply system for providing power to the timing, buffer, and firing circuits shown in the form of block diagrams.
FIG. 2 illustrates a typical timer and buffer circuit for use in this invention.
FIG. 3 illustrates the firing circuit of the electrical initiating system of this invention.
FIG. 4 illustrates a circuit for suppression of transients in the cable connecting the power supply with the buffer, timing and firing circuits.
Referring now to FIG. I, a battery B-I is shown connected to a power inverter 10. A power switch Sl having contacts a,b on-power input lead 12 to the inverter and contacts 0 and d on power output lead 14 from the inverter is shown in the open position. Power switch S1 connects power output lead 14 to ready switch S2 and to charge switch S3. Two batteries, B-2 and 8-3, are connected to the negative lead 16 (common base connection) of the inverter. Upon closing of switch S1 and S2, capacitors C 1-1 to C I-N in the buffer circuit (shown in FIG. 2) are charged to the output voltage of B-2 through conductor 18. Upon closing of charge switch S energy storage capacitors C3-l to C3-N of the firing circuit (shown in FIG. 3) are charged to the voltage required for discharge into the blasting circuit. Upon closing of firing switch 4relay Kl is activated which in turn applies voltage from power source 8- 3 through conductor 20 to both the first buffer circuit and to the first timing circuit whereby the storage voltage E1 is discharged through output contacts 1 into the first blasting circuit. Through subsequent operation of the timing and buffer cir cuits, the storage voltages E2EN are sequentially discharged through output contacts 2 to N into the blasting circuit.
In FIG. 2 the buffer and timing circuits are shown. Buffer circuit 1 is connected in parallel with buffer circuit 2 and buffer circuit N; N being used to designate any given number of buffer circuits identical with buffer circuit 1 and connected in parallel therewith. Each buffer circuit is connected to power from battery B-2 through conductor 18.
Buffer circuit 1 which is illustrative of the other buffer circuits comprises resistors Rl-I, R2-1, R3-I; capacitor Cll; diode D1-1 is and silicon controlled rectifier SCRl-l. Resistor Rl-l is connected to battery B-3 through conductor 18 and to capacitor Cl-I. One lead of resistor R3-l is connected to the control gate of silicon controlled rectifier SCRl-l, and the other lead is connected to conductor 20.
The cathode lead of silicon controlled rectifier SCRl-l is connected in series to resistor R24 which in turn is connected to common bast I6. One lead of capacitor C1-I is connected at the junction of resistor RI-l and the anode lead of silicon controlled rectifier SCRl-l and the other lead is connected to common base 16. The anode lead of diode Dl-l is connected to the junction of silicon controlled rectifier SCRl-l and resistor R2-l. The cathode lead of diode DI-l is connected to the control gate of a silicon controlled rectifier in the firing circuit fully described hereinafter.
Timing circuit 1 of FIG. 2 which is illustrative of the timing circuits is comprised of variable resistor R4-l, capacitor C2-l, Shockley Diode D2-1, silicon controlled rectifier SCR2-l and resistors RS-l and R6-I. This timing circuit provides the delay period between discharge of firing capacitors in the firing circuits. In the timing circuit, one lead of variable resistor R4-l is connected through conductor 20 to battery B3 and the other lead is connected to capacitor C2-1. The anode of Shockley diode D2-I .is connected at the junction of capacitor (32-1 and variable resistor R4-1, and the cathode of Shockley diode D2-1 is connected to the gate of silicon controlledQrectifier SCRZ-I. RS-l connects the gate of silicon controlled rectifier SCR2-I to the common base 16 and is used to establish bias conditions for both the gate of silicon controlled rectifier SCR2-I and Shockley diode D2-l. The cathode of silicon controlled rectifier SCR-l is connected through resistor R3-2 to the gate of silicon controlled rectifier' diode D3I; silicon controlled rectifier SCR3-1; capacitor C3-I; and output connections. One lead of resistor R7-l is connected to the output from inverter I through switches S1, S2 and S3 and through conductor I4. The other lead of resistor R7-I is connected to diode D3-l which is connected in series to capacitor C3-I. A blccder resistor R9-I is connected across capacitor C3-I to common base 16. One lead of resistor R8-I is connected at thejunction of capacitor (33-1 and diode D3I and the other lead is connected to the anode of silicon controlled rectifier SCRlI. Capacitor C3-I is connected to the output connections through resistor R8-l and silicon controlled rectifier SCR3-l which in its natural state is nonconductive. Resistor RIO-l is used to establish bias conditions for the gate of silicon controlled rectifier SCR3-I.
FIG. 4 illustrates a typical radio frequency suppression circuit which serves the function of suppressing transients which otherwise could establish a high frequency oscillation within the cable connecting the power means for operation of the device with the buffer, timing and firing circuits which comprise the output unit of the device. The radio frequency suppression circuit comprises capacitors Cl-F, C2-F, C3-F and C4-F; resistors Rl-F, R2-F and R3F; and inductors Ll-F and L2-F. The capacitors are all connected in parallel with common base 16 and with inverter through conductor 14. Capacitor C1-F is connected at the junction of resistors Rl-F and R2-F which are connected across switch S1. Inductors L2F and LlF are connected in series to resistor R3-F which is connected to switch S3.
Charging of Capacitors of the Buffer and Firing Circuits Capacitors Cl-l through C1-N of the buffer circuits previously described are charged by closing switch S1 and ready switch S2. Current flows through conductor 18 through resistors Rl-l to RIN charging capacitors (31-1 to Cl-N to the voltage value of power source B2. Following charging of the capacitors of the buffer circuit (FIG. 2), the capacitors of the firing circuit (FIG. 3) are charged by closing switch S3. When switch S3 is closed, current flows through conductor 14 into the firing circuits charging the capacitors C3-l to C3-N. For example, current flows through resistor R7-l, through diode D31 and charges capacitor C3-I. In like manner the other firing capacitors are charged.
Operation of Buffer, Timing and Firing Circuits The buffer control and period delay circuits described and energized by closing of switch S4 (after switches S1, S2 and S3 are closed). When switch S4 is closed relay K1 is activated closing the associated contacts and the voltage from battery B3 is applied through resistor R3-1 to the control gate of silicon controlled rectifier SCR1I of the buffer circuit and to variable resistor R4-l of the first timing circuit. The voltage applied to the gate of silicon controlled rectifier SCR11 makes it conductive thereby allowing capacitor Cll of the buffer circuit to discharge immediately through resistor R2-1 and diode Dl-l into the gate of silicon controlled rectifier SCR3-l of the first firing circuit. Through operation of the firing circuit hereinafter described, output voltage is sent immediately into the blasting circuit. The delay period from discharge of the first storage capacitor until discharge of the second storage capacitor in the second firing circuit is determined by current flow through the timing circuit, and more specifically by the time required to build up the voltage on the capacitor C21 of the timing circuit to a higher voltage than the breakover voltage of Shockley diode Dl-l. When the breakdown voltage of the Shockley Diode D2-l is exceeded this diode becomes conductive and voltage is immediately applied to the gate of SCR2I of the timing circuit thereby making it conductive. With silicon controlled rectifier SCR2I conductive current flows to both silicon controlled rectifier SCR1-2 of the second buffer circuit which becomes conductive and discharge capacitor CI-Z through resistor R2-2 and diode Dl-2 into firing circuit 2 and current flows to the second timing circuit which responds in the same manner as timing circuit 1 previously described. Operation of the timing circuit then continues to sequentially activate the buffer circuit discharging the buffer capacitors into the firing circuit and initiating the next timing sequence until ultimately the lust firing capacitor is discharged. Diodes DI -I through |)l N isolate the buffer circuits from transients which appear at the gates of silicon controlled rectificrs SCR3-I and SCRJ-N.
The firing circuit is energized by discharge of the voltage of the buffer capacitors such as Cl-ll through resistor R2-1 and diode Dl-l into the gate of silicon controlled rectifier SCR3-I thereby making SCR3-l conductive. With silicon controlled rectifier SCR3-l conductive capacitor C3-l previously charged to the voltage necessary for operation of the blasting circuit is discharged.
The foregoing descriptions of a buffer circuit, timing circuit, and radio frequency suppression circuit are illustrative of circuit means that can be employed in combination with the firing circuit heretofore described to provide the multiperiod electronically delayed initiating system of this invention. The timing circuit can be replaced with other suitable timing circuits such as a ring counter circuit, or a shift register. Any suitable means for supplying direct current to the electronic delay multiperiod initiating device can be employed.
A typical multiperiod initiating device is prepared having the same circuits as set forth in FIGS. 1, 2, 3 and 4. The parts parameters utilized in these circuits are as follows:
FIG. I-Power Circuits l2-volt battery B2 45-volt battery B-3 l2-volt battery Kl Potter and Brumfield; Potter and Brumfield; KRPI IAG, l2 DC Inverter G.E. Pl-S494787-Gl FIG. 2 Bufi'er and Timing Circuits FIG. 4 -Transient Suppressant Circuit The foregoing multiperiod initiating system successfully detonates in excess of 50 Vibrocaps (a static resistant, No. 8 strength E.B. cap manufactured and sold by Hercules Incorporated) connected in straight parallel without period overlap and with the required simultaneity so that all caps detonated the explosive charge as desired.
What I claim and desire to be secured by Letters Patent is:
l. A device for providing electronically delayed multiple point initiating current to electrical initiators of a blasting circuit for initiation thereof, said system comprising a. a plurality of firing circuits connected in parallel between a first DC power source and a common base connection, said firing circuits comprising resistance means, blocking diode and firing capacitor connected in series and a silicon controlled rectifier having an anode, cathode, and control gate, said firing capacitor being charged through the resistance means by the first DC power source to the potential desired in the blasting circuit, one lead of the firing capacitor being connected to the cathode of the silicon controlled rectifier, the anode of the silicon controlled rectifier being connected to the blasting circuit,
a plurality of buffer circuit means connected in parallel between a second power source and the common base connection, each buffer circuit means comprising at least one buffer capacitor connected to the gate of the silicon controlled rectifier of the firing circuit, said buffer capacitor being charged by the second DC power source and timing circuit means connected to each of the buffer circuit means for sequentially actuating discharge of the buffer capacitors into the firing circuits whereby the silicon controlled rectifiers in the firing circuits are made conductive thereby sequentially discharging the firing capacitors into the blasting circuit.
2. The device of claim 1 wherein the buffer circuit means comprises a resistance meansconnected in series with the buffer capacitor, a second silicon controlled rectifier having an anode, cathode and control gate, and a blocking diode having an anode and a cathode, the anode of the second silicon controlled rectifier being connected to the junction of the resistance means and buffer capacitor, the anode of the blocking diode being connected to the cathode of the second silicon controlled rectifier, the cathode of the blocking diode being connected to the control gate of the silicon controlled rectifier of the firing circuit, said buffer capacitor being charged through said resistance means by the second DC power source.
3. The device of claim 2 wherein the timing circuit means is comprised of plurality of timing circuits connected in series, said timing circuits comprising a first variable resistance means and timing capacitor connected in series, a Shockley diode, having an anode and a cathode, and a third silicon controlled rectifier having an anode, cathode and control gate, the anode of the Shockley diode being connected at the junction of the timing capacitor and first variable resistance means and the cathode of the Shockley diode being connected to the control gate of the third silicon controlled rectifier, the cathode of the third silicon controlled rectifier being connected to the control gate of the second silicon controlled rectifier of the succeeding buffer circuit and to the variable resistance means of the succeeding timing circuit; the anode of the third silicon controlled rectifier being connected to a third DC power source, the timing circuit being activated upon application of the third DC power source whereby potential is built up on the timing capacitor until the avalanche breakdown voltage of the Shockley diode is exceeded whereby voltage is applied to the control gate of the third silicon controlled rectifier making it conductive and permitting current to flow to both the silicon controlled rectifier of the succeeding buffer circuit making it conductive and to a succeeding timing circuit.
4. The device of claim 3 in which a radio frequency suppression circuit is connected between said first DC power source and the firing circuit.
5. The device of claim 4 in which the radio frequency suppression circuit comprises a switching means, a first resistance means and at least one inductor connected in series with the first DC power source, a plurality of capacitors connected in parallel between the first DC power source and the common base connection, each capacitor having one lead thereof connected to a lead of each inductor, a second and a third resistance means connected in series across the switching means, and another capacitor connected between the common base and the junction of the second and third resistance means.
7 7g? UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent 3,603,844 Dated September 7, 1971 Invent 1-( Fred A- Fritz (Case 3) It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
Col. 1, line 72 of the patent, after circuits insert all Col. 2, line 19 of the patent, switch 4relay Kl should read switch S relay K Col. 2, line 35 of the patent, omit is Col. 2, line 42 of the patent, bast should read base Col. 3, line 67 of the patent, Dl-l should read Col. 4, Figure 1, line 35 of the patent, 12 DC should read 12 VDC Col. 4, lines 7 & 8 of Figure 2 of the patent,
8 Jyfd. 50 DC and 5 fd. 15 DC should read 8MFD, 50 VDC and SMFD, l5 VDC-respectively.
Col. 4, Figure 3, omit R second line.
Col. 4, Figure 3 of the patent, opposite C3, A
" 860 fd. O 450 DC should read 860 MFDv'j45O VDC Col. 4, lines 1 and 4 of Figure 4 of the patent,
0. O5A1fd. O 6QO v. and 10 h. 0 200 m. should read 0. 05 MFD1L' 6OO v. and 10 H 200 MA L. respectively.
Signed and sealed this l th day of April 1972.
EDWARD M.FLETCHER,JR ROBERT GOTTSGHALK Attesting Officer Commissioner of Patents