|Publication number||US3605026 A|
|Publication date||Sep 14, 1971|
|Filing date||Jul 14, 1969|
|Priority date||Jul 17, 1968|
|Also published as||DE1936266A1, DE1936266B2, DE1936266C3|
|Publication number||US 3605026 A, US 3605026A, US-A-3605026, US3605026 A, US3605026A|
|Inventors||Bowden Keith Romilly Roskrudge|
|Original Assignee||Rosemount Eng Co Ltd|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (13), Classifications (22)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent 1 i 1 I l i 1 APPARATUS FOR PROVIDING A PULSE TRAIN HAVING A MEAN FREQUENCY PROPORTIONAL TO A DIGITAL NUMBER II Claims, 5 Drawing Figs.
328/55, 328/37. 328/140, 33l/38, 331/48 Int. Cl 03k 1/16 Field of Search .7 328/72, 73,
 I References Cited UNITED STATES PATENTS 3,277,3l7 l/l966 Eckl 328/72 X 3,504,204 3/l970 Carrive 328/72 X Primary Examiner-John S. Heyman Attorney-Bugger, Peterson, Johnson and Westman ABSTRACT: The apparatus provides a series of output pulses having a mean frequency in accordance with a digital input; such pulses may be used for controlling power, e.g. discrete cycles or half cycles of AC power, fed to a load. The digital number is put in a recycling storage medium, e.g. a shift rcgister or delay line and, in one arrangement, a gate is arranged to pass or not pass a pulse from a pulse train according to one selected digit in each cycle of the storage medium, each digit being selected, during a given time interval, for a number of times corresponding to the significance of the digit. With a shift register, it is more convenient to control the shifting by shift pulses such that each digit is put in an output stage, to control a gate, for a number of times in given time interval proportional to the significance of the digit.
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SHEEY 3 0f 3 CLUCK BINARY UIVIBER APPARATUS FOR PROVIDING A PULSE TRAIN HAVING A MEAN FREQUENCY PROPORTIONAL TO A DIGITAL NUMBER BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to apparatus for providing a pulse train of which the mean frequency is proportional to a digital number. By using a pulse train with pulses synchronized with an alternating frequency supply, the pulses in the pulse train may be used to control the supply of power to a load using a thyristor, triac or other triggered switch and thus the invention finds particular application in the control of power supplied to a load in accordance with numerical digital data. The invention however is not necessarily restricted to the control of alternating current power' but finds application more generally in the conversion of numbers available in a register to quasi 1 analogue signals in the form of frequencies or, by a further frequency to voltage conversion, to voltage analogue signals. The apparatus of the invention may thus find application in digital control and in hybrid digital/analogue control systems.
2. Prior Art In U.S. Pat. No. 3,491,283, issued Nov. 20, 1970 .I. S. Johnston assigned to the same assignee as the present application, there is described a system for producing control pulses for controlling the supply of electric power from an alternating supply in accordance with a digital number which is continuously available.
SUMMARY OF THE INVENTION According to the present invention apparatus for providing a series of output pulses having a means frequency in accordance with a digital input comprises a pulse generator supplying a series of pulses at a frequency at least as great as the maximum output frequency required, a recycling storage medium storing a digital number in serial form representing said digital input, and a gate controlling the feeding of pulses from said pulse generator to an output, the gate being controlled by each digit at an output from said storage medium for periods which, in a given time interval, correspond to the significance of that digit. By this arrangement, a digital number which is possibly available only intermittently (e.g. in a complex control system where various inputs appropriate to different control purposes are considered in sequence to produce output control signals), may be put in said storage medium and it serves to provide a train of output pulses having a mean repetition rate corresponding to'the magnitude of the digital number. These pulses may be synchronized with an alternating frequency mains supply and can, for example, be used to operate a controlled switch, e.g. a thyristor or triac to provide pulses of power to a load of a mean magnitude over a time period proportional to the digital input number.
The recycling storage medium may be, for example, a delay line, the delay line cycle time being short compared with the pulse period. In this case, said gate may be arranged to pass or not pass a pulse according to the digit value of one selected digit in each cycle, each digit being selected, during said given time interval, for a number of times corresponding to the significance of the digit.
A similar arrangement may be employed with a shift register as the storage medium. With a shift register, however, it is more convenient to have the gate controlled according to the digit in a selected stage of the shift register and to apply shift pulses to the shift register so that the various digits are put in said selected stage, to effect control of the gate, a number of times in said given time interval proportional to the significance of each digit.
Thus the invention furthermore includes within its scope, apparatus for producing a series of output pulses having a means frequency in accordance with a digital input comprising a pulsegeneratorsupplying a series of pulses at a frequency at least as great as the maximum output frequency required, a gate for controlling the feeding of pulses from the pulse generator to an output, a shift register into which said digital input is put, one stage of said shift register being arranged to control said gate in accordance with the binary digit in that stage, and means for applying shift pulses to said shift register so that the various digits of said digital input are put in said one stage to control said gate for a number of periods which, in a given time interval, correspond to the significance of the respective digits.
Very conveniently the shifting of the number in the shift register is effected after each pulse from said pulse generator so that the aforementioned gate passed or does not pass a pulse according to the appropriate digit value of one digit; the number is then shifted so that the next possible pulse is controlled by another digit. For example if a 5 bit binary number is employed in the register, the most significant digit may control each alternate pulse from the pulse generator, e.g. the first, third, fifth etc., the next most significant digit may control each fourth pulse, e.g. the second, sixth, 10th etc., the next most significant digit may control each eighth pulse, e.g. the fourth, 12th, etc., the next digit may control the eighth and 24th pulses and the least significant digit may control the sixteenth pulse. Ideally, with a five-digit number the 32ND pulse should always be gated by a zero but in practice it may be allowed to appear as a random bit; this gives a maximum error of only 1 part in 32 which is equal to the inevitable digitizing error using a 5 bit representation.
To provide the necessary shift of the number in the register for this purpose, there may be provided a high-frequency pulse source generating shift pulses at a suitable higher frequency than the aforementioned pulse generator (which will be referred to hereinafter as the main pulse generator) so that the total shift required can then be effected in the interval between successive pulses from the main pulse generator, a binary divider giving noncoincident outputs of submultiples of the frequency of the main pulse generator in binary stages, a counter counting successive pulses fed to the shift register and comparator means comparing the output from the counter with the output from said binary divider to gate the pulses from said high-frequency pulse source so as to provide the appropriate number of shift pulses after each pulse of the main pulse generator.
Conveniently for an n-stage shift register, the high frequency generator produces pulses of at least n times the frequency of the main pulse generator.
As previously indicated, if the apparatus is to be used for controlling power fed from an alternating power supply circuit to a load using a thyristor or other controlled switch, conveniently the alternating power supply is used to provide the pulses from the main pulse generator. Most conveniently the pulses are at a frequency twice that of the alternating supply source and the controlled switch is arranged to conduct for half a cycle each time it is triggered by one of said pulses. The alternating power supply would generally be an alternating mains supply at a frequency of 50 or 60 cycles per second. A pulse train at twice the supply frequency may readily be obtained by full wave rectification of a signal at the mains frequency, thereby giving a pulse train at exactly twice the mains frequency.
If it is desired to control the power in whole cycles instead of half cycles, a divide-by-two pulse frequency divider may be provided at the input to the aforementioned binary divider so that that divider and hence the associated counter and the shift register only change after each complete cycle of the main supply frequency.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a timing diagram illustrating output signals from a binary divider in a shift pulse train generator in the apparatus of FIG. 1; and
FIGS. 4 and 5 illustrate further embodiments of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1 there is illustrated diagrammatically a load energized from an alternating power supply source 11, typically a mains supply; the power through the load is controlled by means of a thyristor or other controlled switch system 12. In this particular example it will be assumed that the source 11 is a mains supply at a frequency of 50 Hz. A pulse train at a frequency of 100 Hz. is obtained from this mains supply by means of a full wave rectifier 13 and a pulse shaper 14 giving the pulse train output on a lead 15. This output on lead 15 and the output from the last stage of a 5-bit shift register 16 are applied together to an AND-gate 17, the output signal of which controls the controlled switch circuit 12. The signals in the shift register are altered in position by shift pulses on an input lead 18. These shift pulses are generated by a shift pulse generator 46 which will be described later. The shift register 16 has a feedback circuit so that the number in the shift register can be recirculated through the register on application of the shift pulses. This feedback circuit will be further described later together with the means for inserting new data into the shift register.
The shift pulse train applied on the lead 18 to the shift input of the shift register 16 is arranged so that each bit of the number in the register appears at the output stage of the register, to gate the 100 Hz. signal on lead 15, with a frequency in proportion to the binary significance of that number.
With a 5 bit shift register, the control of the output is most conveniently effected by gating the appropriate number of pulses in each group of 32 pulses on the lead 15. One form of shift pulse train which could be used would be to make the most significant bit, representing half power, to be at the shift register output stage during 16 successive 100 Hz. pulses, the next bit for the next eight of the 100 Hz. pulses and so on. However such pulse trains will give a rather uneven output level, even during the cycling of a fixed number. This uneven output level may not be important, depending on the time constant of the load. It is preferred however to use a pulse train which gives the smoothest possible output level. This is one for which the most significant bit is at the shift register output stage for every alternate 100 Hz. pulse, the next bit for every fourth pulse, the next bit for every fourth pulse, the next bit for every eighth pulse and so on. The required pulse trains for a 5-bit shift register are shown in FIG. 2. In this figure the bits in the shift register are identified by the numbers 0,1,2,3 and 4,0 being the most significant bit and 4 the least significant. These numbers along the top line, marked (a), of FIG. 2 indicate which of the bits in the shift register is at the output stage for each 100 Hz. pulse. The middle line, marked (b) shows the 100 Hz. pulses. The bottom line, marked (0), of FIG. 2 shows the number of shift pulses required to effect the necessary change in position in the shift register. This is a number between 1 and 4. Ideally the 32 nd pulse should always be gated by a 0 to account for the absence of the sixth and subsequent digits in the number. This could be arranged for example by adding a further input to the AND-gate 17 to inhibit every 32 nd 100 Hz. pulse on lead 15. In practice this is unnecessary since, if a random bit is allowed to appear, it would cause a maximum error only of l part in 32 which is equal to the inevitable digitizing error using a 5-bit representation.
The particular shift pulse train generator illustrated in FIG. 1 generates the pulses shown in FIG. 2. Referring to FIG. 1, I00 Hz. pulses on a lead 32 are fed through a divide-by-two unit 33 and thence applied through a lead 34 to a five stage binary divider 19. The use of this divide-by-two unit 33 will be explained later; it is required for whole cycle control. If the control is to be of half cycles ofthe power fed to the load, then the stage 33 is omitted. In the following description it will for convenience be assumed that this stage 33 is omitted and that the I00 Hz. pulses appear on lead 34. The binary divider 19 contains five stages which give noncoincident outputs at submultiples of the input frequency on leads 20 to 24 respectively (such a binary divider is described for example in the aforementioned U.S. Pat. No. 3,491,283. The last stage also pro vides a second output on a lead 49 which is at a different time from that on the lead 24. These output pulses on the various stages constitute a set of noncoincident signals of duration th of a second so that each lasts from one input pulse on the lead 34 to the next. The timing of the various output pulses on the leads 20 to 24 and 49 is illustrated in FIG. 3. A pulse source 31 of some suitable frequency which is at least n times higher than the lOO Hz. where n is the number of bits used in the shift register, is provided to give the shift pulses. The output of this shift pulse generator 31 is fed to an AND-gate 42 and thence to the aforementioned lead 18. From the lead 18, the pulses are applied not only the shift input of the shift register 16 but also to a modulo five counter 25. This counter has outputs on leads 26 to 30 representing successive counts. The signals on leads 20 and 26 are applied to an AND-gate 35. Signals on leads 21 and 27 are applied to an AND-gate 36. The signals on leads 22 and 28 are applied to an AND-gate 37. The signals on leads 23 and 29 are applied to an AND gate 38 and the signals on leads 24 and 30 are applied to an AND-gate 39. The outputs from the five AND-gates 35 to 39 are applied to an OR-gate 40. To this OR-gate is also applied the output on lead 49. The output from the OR-gate 40 is inverted by an inverter 41 and thence applied to the aforementioned AND- gate 42.
The operation of the shift pulse generator is as follows: Suppose that the binary divider 19 is in a state where output 20 is 1. Since none of its other outputs is 1 at this time, only AND- gate 35 can possibly give a 1 output, and that only when the counter 25 is in the state for which output 26 is 1. If the counter is in any other state, none of the AND-gates 35 to 39 gives a 1 output, so the OR-gate 40 has a 0 output, and the inverter 41 has a 1 output. AND-gate 42 therefore allows pulses out of the high-frequency pulse generator 31 to the shift pulse output 18 and to the pulse input of the counter. The counter steps round until it reaches the state at which there is an output on lead 26, whereupon AND-gate 35 gives a 1 output, the OR-gate 40 gives a 1 output, the INVERTER 41 has a 0 output, and further pulses from the pulse generator 31 are inhibited.
After the next 100 Hz. pulse on lead 34, the binary divider changes to another state (say 21) and the output of AND-gate 35 changes to 0. As before, AND-gate 42 allows pulses out of pulses generator 31, this time until the counter reaches the state at which there is an output on lead 27 (after only 1 shift pulse), when further pulses are inhibited by the 1 output of AND gate 36.
The next 100 Hz. pulse 34 changes the binary divider back to the state giving an output at 20, whereupon in the same manner pulses are allowed out (4 in this case) sufficient to return the counter to the state where there is an output on 26.
In this way, the state of the counter 25 is made to follow the demands of the binary divider l9, and the shift pulse output 18 generated is such as is necessary to cause this.
When an output on lead 49 of the binary divider appears, at the 32nd input pulse, shift pulses are completely inhibited by the connection to the OR-gate 40, so that the counter remains in its previous state at which there is an output on lead 26.
The shift pulse output on lead 18 obtained from the shift pulse generator 46 is used to step the data in the shift register 16 in the control system. This keeps the shift register in step with the counter 25 and hence with the binary divider 19. So long as the data shift register 16 is filled in an appropriate manner that is to say with the most significant bit at the output stage when the binary divider 19 and the counter 25 are in stages giving outputs at 20 and 26 respectively, then each bit in the shift register will subsequently appear at the output of the shift register for a proportion of the time proportional to its significance.
It will be noted that, if power to a number of separate loads is to be controlled, the shift pulse generator can be common to a number of separate shift registers containing separate information regarding the particular control of each individual load. Thus the control circuits for each individual load are relatively simple.
The shift register 16 could be filled by parallel transfer but a serial input permits the use of a cheaper component and reduces the number of interconnections. FIG. 1 also illustrates one arrangement of a circuit for putting information into the shift register 16 by serial input. The input data in serial form on a lead 43 is fed through an AND gate 44 and an OR gate 50 into the shift register 16. This is done during a time period determined by a FILL THIS REGISTER" input on a lead 45 which is applied to the AND-gate 44 and also to an inverter 47. The output from the inverter 47 is applied to an AND-gate 48. The second input to this AND-gate 48 is from the output of the shift register 16. The output from the AND-gate 48 forms a second input to the OR-gate 50. The FILL THIS RE- GISTER signal on. lead 45 can conveniently be arranged to occur at a time when the most significant bit is at the output of the shift register. Data is then transferred into the shift register by an extra burst of five pulses mixed with the pulse train on the lead 18 to form the shift pulses from the generator 46.
The waveforms on the leads 43, 45 and can be common to a large number of output circuits. Only the FILL THIS REGISTER" input on lead 45 is unique and selects this particular output circuit for insertion of new data. Normally when the FILL THIS REGISTER signal is not present, the inverter 47 gives a I output and the number in the shift register 16 circulates through the AND-gate 48.
To meet the ideal requirement previously mentioned that every 32nd 100 Hz. pulse should be omitted, the 100 Hz. pulse train on lead 15 can be inhibited by the output 49 of the binary divider before distribution.
1 'In practiceit is necessary that shifting in the shift register 16 should riot occ u'r during the presence of a pulse on the 100 Hz. output pulse lead 15 and that the changes in the binary divider 19 should occur in synchronism with the high frequency pulse generator 31. It is therefore convenient to use, as the 100 Hz.
input 32 totlie binary divider 19, a pulse following the back edge of the high-frequency pulse from the high-frequency pulse generator 31 which next follows the back edge of the I00 Hz. pulse on lead 15. Using flip-flops which switch at the back edge of a clock pulse, the sequence of events is then I. 100 Hz. pulse on lead 15 is gated to the controlled switch 12 or not according to the bit in the output stage of the shift register 16,
2. the binary divider 19 is changed to define the bit required next,
3. shift pulses on lead 18 occur sufficient to change the counter 15 and the shift register 16 to matching new positions ready for the next 100 Hz. pulse.
The 100 pulse on lead 15 is gated to the thyristor to continue the cycle this time in accordance with the appropriate bit now in the output stage of the shift register 16. If new data is to be inserted this is done immediately after the step (3) and before the next I00 Hz. pulse is gated to the controlled rectifier 12. This is only done when the new position is appropriate. Since the most significant bit is in the output stage every alternate pulse, it is not a serious restriction to wait for this in order that the filling up may be done in the normal way with the most significant bit first. Such a wait is only for one twenty-fifth of a second.
The divide-by-two pulse frequency divider 33 in the input to the binary divider 19 is provided so that the input on lead 34 is a 50 Hz. pulse train. This has the result that the binary divider 19 and hence the counter 25 and the data shift register 16 only change after every alternate 100 Hz. pulse on lead 15 thereby giving whole cycle control of the controlled switch 12.
FIG. 4 illustrates a modification of part of the apparatus of FIG. 1 to show how the number stored in the shift register may be monitored. This facility may be desirable for example in an automatic control system in which the digital data is transmitted to a central station and used for automatic control pur poses and also for monitoring. In FIG. 4 the same reference characters are used as in FIG. 1 to indicate corresponding elements. The FILL THIS REGISTER" signal has been split into two parts, a This Register signal and a Fill" signal, this being convenient in a multistore system. These two parts are applied to an AND-gate 60, the output of which is applied to inverter 47 and AND gate 44. The This Register" signal on an input line 61 is also fed to an AND-gate 62 to gate the output from the shift register 16 for feeding to a monitor output line 63. Thus, by selection of the This Register" input 61, the selected output can be monitored. In a multistore system, the Fill" signal on lead 64 may be common to all the stores as may also be the monitor output line 63.
The shift register 16 may be arranged to store a plurality of separate digital numbers, e.g. eight 5-bit numbers. In this case, eight separate flip-flops forming eight stages at the end of the register are used to provide outputs representing one digit of each of the eight numbers. The numbers would be interleaved so that these eight flip-flops carry digits of equal of equal significance. The shift pulses would now have to be in bursts of eight or multiples of eight so that the appropriate digits of different significance are set in these end flip-flops as required. Each of these flip-flops may then gate a pulse train to give an individual output pulse train of a means repetition frequency proportional to its own particular number, in a manner similar to that described with reference to FIGS. 1 to 3. The pulses in bursts of eight may be obtained by increasing the frequency of the pulse generator 31 and putting a divide-by-eight circuit in the input to the counter 25. The state of this divide-by-eight counter may be used also for synchronizing filling and monitoring of the store.
FIG. 5 illustrates the use of a synchronous shift register, such as a delay line. In FIG. 5, this shift register is shown at 70 and it is assumed that this contains 16 bits in this example. The input and feedback is similar to that of FIG. 1 and the same reference characters are used.
In this arrangement the shift pulses are a regular sequence if the unit 70 is a shift register requiring input shift pulses. These are derived from a clock 71. If the unit 70 is a delay line, the clock period corresponds to the time period for each effective step of the delay line (the delay need not be in steps) i.e. onesixteenth of the total delay period. The output from the end of the shift register is fed to a first flip-flop 72 which is thus filled when the appropriate new bit goes to the end of the shift register, which instant varies within the cycle of the l6-bit period. A second flip-flop 73 is always filled from the first flipfiop at the end of a complete period, and thus is filled at equal intervals. There is thus a synchronous output, the period being determined by the total shift register delay period. To effect the necessary gating, the clock pulses from clock 71 are fed to a divide-by-l6 unit 74 and the output of this is fed to an AND gate 75 and is also fed to an output lead 76 as a synchronizing pulse for filling or monitoring. The AND gate 75 has a second input from the clock 71 and gives an output which is used for controlling the filling of the flip-flop 73 and is also fed to a binary divider 77. This binary divider 77 corresponds to the divider 19 of FIG. 1 while the divide-by-l6 unit 74 corresponds to the counter 25 of FIG. 1. A gate unit 78 containing AND- gates and an OR gates (similar to gates 35 to 40 of FIG. 1) compares the outputs for divide-by-l6 unit 74 and divider 77 to provide an input to an AND-gate 79, having a clock pulse as a second input, to select the appropriate clock instant in each l6-bit period at which the flip-flop 72 is to be filled.
For controlling power from an alternating current supply, the divide-by-l6 unit 74 must be phase-locked to the AC supply. It is then possible to replace the second flip-flop 73 by an AND-gate, having arranged that its clock pulse is appropriately phased for thyristor firing.
For a multiple store, a delay line may be employed capable of storing many digital numbers. For example, a 256 microsecond glass delay line may be employed to store 4,096 bits, that is 256 numbers each of 16 bits. The clock pulses may be fed to a divide-by-l6 counter (corresponding to unit 74) with an associated binary divider unit (corresponding to divider 77) and set of AND-and-OR-gates (corresponding to unit 78) to provide an indication of when a bit of desired significance is at the output of the delay line, and a further divide-by-256 counter (fed from the output of the divide-by-l6 counter) to indicate which of the 256 numbers the bit belongs to. These may be used together to gate the appropriate bit from each number into the appropriate one of a set of 256 output flip-flop pairs (corresponding to 72, 73).
ln some cases, it may be preferred to store the digital control number as binary-coded decimal number. In this case, the binary divider 19 of FIG. 1 would be replaced by one or more decades of a binary-coded decimal divider, so that each bit in the shift register is put in the output stage the appropriate number of times according to the significance ofthat bit.
The systems described provide outputs representing numbers inserted in a shift register or delay line. Such apparatus can usefully be part of a control system, in which the present output signal can be monitored, modified (by reference to other criteria) and rewritten in the output store, at frequent intervals, so as to provide a virtually smoothly varying output signal.
In any system, by making the binary divider" have less stages than there are bits/points in the register (and in the counter 25), other numbers can be stored in the same register or registers, interleaved with the output" numbers, without interfering with the output in any way, yet accessible for monitoring. This could be particularly useful in a multipoint controller, when any variables relating to each loop individually could be conveniently stored, to be available for the main controller" electronics as required.
1. Apparatus for providing a series of output pulses having a mean frequency in accordance with a digital input comprising a pulse generator supplying a series of pulses at a frequency at least as great as the maximum output frequency required, a recycling storage medium storing a digital number in serial form representing said digital input, said storage medium having an output to which each digit in turn is applied as the number is cycled through the storage medium, a gate controlling the feeding of pulses from said pulse generator to an output, and recycling control means controlling the recycling so that each digit is brought to said output of said storage medium for periods of time corresponding to the significance of the digit whereby the gate is controlled by each digit at said output from said storage medium for a number of periods which, in a given time interval, correspond to the significance of that digit.
2. Apparatus as claimed in claim 1 wherein said recycling storage medium is a shift register and wherein the gate is controlled according to the digit in a selected stage of the shift register and wherein shift pulses are applied to the shift register so that the various digits are put in said selected stage, to effect control of the gate, a number of times in said given time interval proportional to the significance of each digit.
3. Apparatus as claimed in claim 1 in combination with a load, an alternating power supply, a power circuit connecting said power supply to said load a controlled switch in said power circuit said controlled switch being operatively responsive to said output pulses.
4. Apparatus as claimed in claim 3 wherein said pulse generator comprises rectifier means rectifying said alternating power supply to provide pulses at a frequency twice that of the alternating supply and wherein said controlled switch is arranged to conduct for half a cycle of the alternating supply each time it is triggered by one ofsaid pulses.
5. Apparatus as claimed in claim 3 wherein said pulse generator comprises rectifier means to rectify said altemating power supply and wherein said controlled switch is arrange to conduct for one cycle of the alternating supply each time it is triggered by a gated pulse from said pulse generator.
6. Apparatus for providing a series of output pulses having a mean frequency in accordance with a digital input comprising a pulse generator supplying a series of pulses at a frequency at least as great as the maximum output frequency required, a gate for controlling the feeding of pulses from the pulse generator to an output, a shift register into which said digital input is put, one stage of said shift register being arranged to control said gate in accordance with the binary digit in that stage and means for applying shift pulses to said shift register so that the various digits of said digital input are put in said one stage to control said gate for a number of periods which, in a given time interval, correspond to the significance of the respective digits.
7. Apparatus as claimed in claim 6 wherein, to provide the necessary shift of the number in the shift register, there are provided a high frequency source generating shift pulses at a higher frequency than said pulse generator and arranged so that the total shift required in effected between successive pulses from said pulse generator, a binary divider giving noncoincident outputs of submultiples of the frequency of the main pulse generator in binary stages, a counter counting successive pulses fed to the shift register and comparator means comparing the output from said counter with the output from said binary divider to gate pulses from said high frequency pulse source as to provide the appropriate number of shift pulses after each pulse of the main pulse generator.
8. Apparatus as claimed in claim 7 and wherein said shift register has n-stages and wherein said high frequency pulse source has a frequency at least as great as n times the frequency of said pulse generator.
9. Apparatus for providing a series of output pulses having a mean frequency in accordance with a digital input comprising a pulse generator supplying a series of pu lses at 'a frequency equal to the maximum output frequency required, a recycling shift register storing a digital number in serialform representing said input, said shift register having an output stage, means applying shift pulses to the shift registerso that the various digits are put in said output stage for' n'umber of times in a given time interval corresponding to the' significance of the respective digits, a gate controlling the feeding of pulses from said pulse generator to an output, and means responsive to the digit in said output stage controlling said gate so that the number of pulses fed to the output in said given time corresponds to the significance and magnitude of the digits in said shift register.
10. Apparatus as claimed in claim 9 wherein said means applying shift pulses to the shift register comprises a highfrequency generator, shift signal gating means gating the out put from said high-frequency generator, and control means controlling the shift signal gating means at the frequency of the pulse generator output so that the shifting of the number in the shift register is effected after each pulse from the pulse generator.
1 1. Apparatus as claimed in claim 9 wherein said shift signal gating means comprises a divider and counter providing, in response to each alternate pulse from the pulse generator (eg. the first, third, fifth etc.), shift pulses to put the next most significant digit in said output stage, and in response to each alternate one of the remaining pulses shift pulses to put the next most significant digit in said output stage and so on.
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|US4604582 *||Jan 4, 1985||Aug 5, 1986||Lockheed Electronics Company, Inc.||Digital phase correlator|
|US6313618||Feb 16, 1999||Nov 6, 2001||Crouzet Automatismes||Method for controlling the dissipation of an electric signal and implementing device|
|WO1999042913A1 *||Feb 16, 1999||Aug 26, 1999||Crouzet Automatismes||Method for controlling the dissipation of an electric signal and implementing device|
|U.S. Classification||327/114, 377/72, 331/38, 341/144, 377/39, 331/48, 327/231|
|International Classification||G05F1/10, G06F7/68, G05B11/01, H03M1/82, H02M5/02, H02M1/08, H02M5/257, G06F7/60, G05B11/30|
|Cooperative Classification||H02M5/2576, G06F7/68, H02M1/083|
|European Classification||H02M1/08C, H02M5/257C2, G06F7/68|