|Publication number||US3608301 A|
|Publication date||Sep 28, 1971|
|Filing date||Apr 30, 1970|
|Priority date||Apr 30, 1970|
|Publication number||US 3608301 A, US 3608301A, US-A-3608301, US3608301 A, US3608301A|
|Inventors||Loewengart Harry R|
|Original Assignee||Quasar Microsystems Inc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (12), Classifications (18)|
|External Links: USPTO, USPTO Assignment, Espacenet|
P 23, 1971 H. R. LOEWENGART 3,608,301
DIGITAL CLOCK HAVING AUTOMATIC INDICATION OF POWER FAILURE Filed April 30, 1970 United Sm t-es Patent Otfice 3,608,301 Patented Sept. 28,, 1971 3,608,301 DIGITAL CLOCK HAVING AUTOMATIC INDICATION OF POWER FAILUR E Harry R. Loewengart, New York, N.Y., assignor to Quasar Microsystems, Inc., Brentwood, N.Y. Filed Apr. 30, 1970, Ser. No. 33,275 Int. Cl. G04c 3/00 U.S. Cl. 58-23A 15 Claims ABSTRACT OF THE DISCLOSURE In an electrically operated timepiece means are provided to detect the failure of the electrical power supply, and to thereupon disable the time indication. That indication remains disabled even after the electrical power is restored, and is only re-enabled when the timepiece is reset to the correct time.
The present invention relates generally to electrically operated timepieces, and particularly to a device for detecting a failure in the electrical power supply to the timepiece.
Electrical timepieces are commonly used to indicate the time, primarily in homes and commercial establishments. In a conventional electric clock the timing signals are derived from the known and precise frequency of the electrical power supply which may be used to drive a synchronous motor. In recent years, digital clocks, in which the time is displayed in a digital readout form as opposed to the movement of hands on a clock face, have gained widespread acceptance. In one type of digital readout, devices such as display tubes provide separate indications of hours, minutes, and if desired, seconds.
The electrical timepiece is able to provide an accurate 1ndication of time only as long as it receives an uninterrupted power supply. When there is an interruption in the A.C. power supply to the clock, due, for example, to a power failure, or the dislocation of the clock connection to the A.C. power outlet, the clock becomes inoperative, and will resume operation only after electrical power is restored thereto. It is common for the owner of an electrical clock to be unaware that there has been a failure in the supply to the clock if he does not happen to view the clock in the period during which it is inoperative as a result of the power failure. Thus, after the resumption of power following a power failure, the clock will once again be operative but will give an incorrect indication of time by an amount equal to the duration of the power failure. If the individual viewing that indication is not aware that a power failure has occurred, he will usually be unaware that the clock indication is incorrect.
Power failure indicators have been provided in electric clocks such as a red disc appearing in a window on the clock face. These have not been entirely effective as they are often not clearly apparent to the viewer, and moreover, the indications are often removed when the power is restored without ensuring that the clock indication is reset to the correct time setting.
Thus it is all too frequent an occurrence for an individual to obtain an incorrect time indication from an 'electric timepiece after the occurrence of a temporary It is another object of the invention to provide an electrical timepiece in which the likelihood of an incorrect time indication following an interruption of power to the clock is significantly lessened.
Broadly described, the electrical timepiece of the present invention comprises means for detecting the occurrence of an interruption or failure of electrical power to the timepiece, and to thereupon disable the time indication. After the power is restored the time indication remains disabled until the timepiece is restored to the correct time setting.
The invention is herein described with reference to a digital clock in which time indication is given by a display of hours, minutes, and seconds digits provided by a series of display devices such as display tubes. Upon the failure of power to the clock a switch is deactuated to disable the display devices so that a time indication is no longer visible. That switch means remains deactuated even when power is restored to the display devices until a time reset member is operated. The operation of that reset member reactivates the switch means and thus re-enables the time display, while at the same time, applying a series of pulses to update the setting of the time indicator to the correct time.
To the accomplishment of the above and to such further objects as may hereinafter appear, the present invention relates to an electric timepiece having an automatic power failure indication, as defined in the appended claims and described in the following specification taken together with the accompanying drawing in which the single figure is a schematic circuit diagram of an electric digital clock incorporating the power failure indicator of the invention.
The circuit of the present invention causes the time display of an electrically operated timepiece to be disabled upon a failure of the supply of electrical energy to the timepiece, and permits that display to be re-enabled after such a failure only after the time indication is reset. As herein shown the circuit of the invention is incorporated in a digital timepiece, although it is to be understood that it can be used as well to equal advantage in other types of electrically operated timepieces such as those in which the timing mechanism is controlled by a synchronous electric motor.
Referring now to the single figure, the basic timing signals for the timepiece are derived from the 60 cycle A.C. power line source 10 which is applied to a power supply generally designated 11. That 60 cycle signal is processed in a manner to be described below to operate a series of display tubes Tl-T6 which in combination provide a visual, digital display of the time in terms of hours, minutes and seconds. Namely, tube T1 presents the tens digit of the hour (either 0 or 1); tube T2 represents the units hour digit (0-9); tube T3 represents the tens minutes digit (0-5); tube T4 represents the units minutes digit (0-9); tube T5 represents the tens of seconds digit (O5); and tube T6 represents the units of second digit (0-9). Tubes Tl-T6 are respectively connected through resistors R1-R6 to a high voltage (e.g. volt D.C.) line 12. The voltage at line 12, which is derived from power supply 11 in a known manner, actuates the display medium in each tube to enable it to provide one of its available digital displays.
In accordance with the present invention, a failure in the A.C. line source 10 such as Would occur when the clock is accidentally disconnected from the A.C. power source, causes tubes T1-T6 to be effectively disabled. Since the timing operation is interrupted as a result of a power failure, the indication of tubes T1T6 is caused to remain disabled even when power is restored until the timing indication is manually reset to correct its reading.
In the embodiment of the invention herein described, a reduced A.C. voltage at the line frequency is derived in a known manner in power supply 11 at line 13 which is connected through a resistor R7 to the emitter of a UJT Q1. The base of UJ1 Q1 are respectively connected through a resistor R8 to a DC. supply and to ground. UJT Q1 acts as a pulse shaper to convert the input 60 cycle A.C. signal to a chain of pulses having a repetition rate of 60 p.p.s.
The output pulse chain from UJT Q1 is applied to terminal CA of a counter 14. Counter 14 performs a 2:1 division between terminals CA and A, and a 5:1 division between terminals CB and D. As a result counter 14 acts as a decimal counter and produces at its terminal D, a pulse chain having a rate of 6 p.p.s. That pulse chain is applied to the CB terminal of a counter 16 which produces a 2:1 division between its terminals CA and A, and a 6:1 division between its terminals CB and D. As a result the pulse chain at counter 16-terminal D is at 1 p.p.s.
The pulse chain from counter 16 is applied to the CA terminal of a counter 18 which is identical to counter 14 in its arrangement. Terminal A of course 18, which thus has a pulse appearing thereat every two seconds, is connected to the CB terminal of that counter so that a pulse appears at terminal D of counter 18 every seconds. Terminals A and D of counter 18, as well as the intermediate terminals B and C of that counter are connected to a decoder-drive 20 which supplies driving signals to display tube T6 to in turn change the numerical indication of that tube each second.
Terminal D of counter 18 is also connected to the CA terminal of counter 16 with the result that a pulse appears at counter 16-terminal A every 20 seconds. The latter pulse signal is connected to one input of a decoder-driver 22, and to one input of a flip-flop 24. One output of fiipfiop 24 is in turn connected to a second terminal of decoder 22, and to an input terminal of flip-flop 26. The output terminals of flip-flop 26 are in turn connected to another terminal of decoder 22 and to an input terminal of flip-flop 24.
The inputs to decoder 22, which are connected to tube T5 cause the digital readout provided by that tube to change every ten second as desired. The combination of flip-flops 24 and 26 also define a divided-by-three counter which produces a pulse each 60 seconds at a line 28. That line is connected through a filtering network comprising a capacitor C and a grounded inductance L1 to the CA terminal of a counter 30, which is identical in arrangement to counters 14 and 18. A pulse is thus caused to appear every two minutes at counter 30-terminal A which pulse is connected to one terminal of a decoder 32, which in turn is connected to tube T4 as well as to terminal CB of that counter. A pulse at terminal D of counter 30 thus appears once every 10 minutes. Terminals B-D of counter 30 are also connected to a decoder 32, which together with the signal derived from terminal A of that counter, cause the digital readout at tube T4 to change once each minute.
Terminal D of counter 30 is also connected to terminal CB of a counter 34 which is identical in its arrangement to counter 16. A signal at counter 34terminal D thus appears once each hour. Terminals B-D of counter 34 are connected to a decoder 36 which provides operating signals to display tube T3. Terminal D of counter 34 is also connected to counter 34-terminal CA. As a result, terminal A of counter 34 has a pulse appearing thereat once every 2 hours. Terminal A of counter 34 is connected to terminal CB of a counter 38 which is identical in its arrangement to counters 14, 18 and 30, and to one input terminal of a decoder-driver 40. Decoder-driver is in turn connected to tube T2 and produces operating signals therefor.
Terminals D and CA of counter 38 thus have a timing signal present thereat once overy 10 hours, and terminals D-B of counter 38 are connected to decoder 40, which is thus effective to change the digital readout of tube T2 once each hour. Terminal A of counter 38, which changes its level every ten hours, is connected through a resistor R9 to the base of a first driver transistor Q2, and to the emitter of a second driver transistor Q3. The collectors of these transistors are respectively connected to the two input lines of tube T1. The emitter of transistor Q2 is connected through a diode D1 to ground, and the base of transistor Q3 is biased by resistors R10 and R11 connected in series between a DC. source and ground.
Terminal A of counter 34 and terminals A and B of counter 38 are respectively connected to the three inputs of a NOR gate 42 which produces a uniquely negative output when all of its inputs are positive. This occurs for a time reading equivalent to 13 on tubes T1 and T2 which is impermissible in a 12 hour clock. To prevent this improper time reading, the output of gate 42 is applied as an input to a NOR gate 44, the output of which is connected to the reset terminal of counter 38. Thus,
for a negative, e.g. 13 oclock signal at the output of gate 42, counter. 38 is reset, and tubes T1 and T2 combine to provide a proper 1 oclock readout.
When it is desired to reset the complete time indication to zero, a normally closed reset switch SW1 is operated to disconnect a point 46 from ground. At this time point 46 is connected through a resistor R12 to a positive D.C. source and becomes positive. Point 46 is connected 'to an inverter 48 and to a line 50. The output of inverter 48 is connected to the reset terminals of flip-flops 24 and 26, and to a second input of NOR gate 44, which in turn provides a second inversion to produce a reset signal for counter 38. Line 50' is connected to the reset terminals of counters 16, 18, 30 and 34. The operation of reset switch SW1 is thus efiective to reset all counters to zero, except counter 14, and flip-flops 24, 26, so that the digital readouts of tubes T1-T6 are all reset to zero.
In accord with the present invention, upon the failure of the external A.C. power source 10, the DC. voltage is removed from line 12, and as a result, tubes Tl-T6 are all disabled. Moreover, line v12 thereafter remains disabled, even once A.C. power is stored, until the time setting is reset to make corrections for the time elapsed during the power failure.
To this end, an SCR Q4 has an anode-cathode circuit connected in series intermediate power supply 1 1 and line 12. The gate of SCR Q4 is connected to ground through a clamping diode D2, and to line 12 through a resistor R13. The cathode of SCR Q4 is connected through a capacitor C2 to the emitter of a UJT Q5. That emitter is also connected through series connected capacitors C3 and C4 to ground, and. through a resistor R14 to the low-voltage D.C. terminal of power supply 11. One base of a UJT Q5 is connected through a resistor R15 to that low-voltage terminal, and the other base of UJT Q5 is connected to the junction point of capacitor C1 and inductor L1 at the CA-terminal input of counter 30. UJT Q5 is, in this manner normally biased in an oif condition. A'normally closed minute reset switch SW2 is connected in shunt across capacitor C3, and a normally closed hours reset switch SW3 is connected in shunt across capacitor C4, the latter capacitor having a significantly lower value of capacitance as compared to that of capacitor C3. Thus, in normal operation, both capacitors C3 and C4 are bypassed, thereby connecting the emitter of UJT Q5 directly to ground.
In operation, the failure of the A.C. power source 10 removes the DC. voltage from the anode of SCR Q4 thereby rendering that device non-conductive. As is well known, SCR Q4 will remain non-conductive even when a DC. voltage is restored to its anode, until a suitable actuating signal is developed across its gate and cathode terminals. Thus, after a power failure and the subsequent restoration of power, SCR Q4 remains off and display tubes Tl-T6 remain disabled.
When reset switches SW2 and SW3 are both in their normal position, UJT Q remains off. When a power failure occurs, in addition to the disabling of the display tubes, the counting signals at line .13 are disabled, so that the counters 1'6-38 would no longer produce correct timing signals to their respective display tubes, even if the latter were enabled to provide visual digital displays of the counted timing signals. For this reason it is required to reset the clock to the proper time setting to correct for timing operation that was lacking during the period in which the A.C. power source was not present.
To this end, the user must operate one or both of reset switches SW2 and/or SW3. This operation places one or both of capacitors C3 and C4 in operative connection between the emitter of UJT Q5 and ground, thereby causing that device to conduct and to produce an oscillating sawtooth signal at a frequency determined by the net capacitance between the emitter of UJT Q5 and ground. That sawtooth signal performs two significant operations in the clock circuit. Firstly, it is applied through capacitor C2 to render the cathode of SCR Q4 negative with respect to its gate, thereby once again rendering SCR Q4 conductive, reestablishing the high voltage on line 12, and thus enabling display tubes T1-T6. Secondly, the sawtooth waveform is applied to counter 30 to update the output signals for that counter along with counters 34 and 38, if necessary, to return the now visual time indication to a proper setting.
When a relatively minor correction to the time is required, only switch SW2 need be operated; for a more substantial correction, switch SW3 should also be operated either alone or along with switch SW2 to increase the rate at which timing pulses are applied to the counters.
Thus, as desired, the resetting of the time indication after the restoration of A.C. power to the clock following a power failure, re-enables the visual indication of the time while at the same time, correcting the reenabled time indication to the correct time. Significantly, the time indication can only be re-enabled following a power failure by the operation of resetting members SW2 and/ or SW3. Thus it is not possible for the clock to provide other than a correct time indication once the A.C. power is restored following a failure thereof.
While the present invention has been herein specifically described for use in a digital clock having hours, minutes and seconds indications, it may be used with obvious equal advantage in a digital clock having only hours and minutes indications, or in an electric clock having movable hour and minute hands with appropriate means for rendering those hands visible to the user.
Thus, while only a single embodiment of the invention has herein specifically been described, it will be apparent that many variations may be made therein, all without departing from the spirit and scope of the invention.
1. In an electrically operated timepiece having time indicating means and means for connecting a source of electrical power to said indicating means to operate the latter, the improvement which comprises means for disabling said indicating means upon an effective failure of said electrical power source, and means for resetting said indicating means to a desired setting and for re-enabling said indicating means only upon the operation of said resetting means.
2. The timepiece of claim 1, in which said disabling means comprises switch means having a control terminal operatively interposed between said electrical source and said indicating means.
3. The timepiece of claim 2, in which said re-enabling means comprise second switch means actuated upon the operation of said resetting means and effective when so actuated to actuate said first-mentioned switch means.
4. The timepiece of claim 3, in which said indicating means comprises pulse-controlled counting means, said second switch means when actuated by said resetting means comprising means for producing a series of repeating pulses, said pulses being effective to update said counting means and to actuate said first switch means.
5. The timepiece of claim 4, in which said second switch means comprises a control terminal operatively connected to said resetting means and to said first switch means, and an output terminal operatively connected to said counting means.
6. The timepiece of claim 5, comprising capacitance means connected between said second-switch means control terminal and a reference point, said resetting means being effective when actuated to vary the value of capacitance of said capacitance means.
7. The timepiece of claim 6, further comprising means for clamping the control terminal of said first switch means to a reference level, said second switch means being effective when actuated to establish a potential at the output terminal of said first switch means for actuating the latter.
8. The timepiece of claim 3, in which said second switch means comprises a control terminal operatively connected to said resetting means and to said first switch means, and an output treminal operatively connected to said a timing means. 1
9. The timepiece of claim 8, comprising capacitance means connected between said second-switch means control terminal and a reference point, said resetting means being effective when actuated to vary the value of capacitance of said capacitance means.
10. The timepiece of claim 9, comprising means for clamping the control terminal of said first switch means to a reference level, said second switch means being effective when actuated to establish a potential at the output terminal of said first switch means for actuating the latter.
11. The timepiece of claim 4, comprising capacitance means connected between said second-switch means control terminal and a reference point, said resetting means being effective when actuated to vary the value of capacitance of said capacitance means.
12. The timepiece of claim 11, further comprising means for clamping the control terminal of said first switch means to a reference level, said second switch means being effective when actuated to establish a potential at the output terminal of said first switch means for actuating the latter.
13. The timepiece of claim 3, further comprising means for clamping the control terminal of said first switch means to a reference level, said second switch means being effective when actuated to establish a potential at the output terminal of said first switch means for actuating the latter.
14. The timepiece of claim 4, in which said resetting means comprises first and second members, effective when selectively actuated to actuate said second switch means and to establish a predetermined frequency of said pulses.
15. The timepiece of claim 14, comprising capacitance means connected between said second-switch means control terminal and a reference point, said members being effective when actuated to vary the value of capacitance of said capacitance means.
References Cited UNITED STATES PATENTS 2,430,782 11/1947 Poole 340248X RICHARD B. WILKINSON, Primary Examiner E. C. SIMMONS, Assistant Examiner US. Cl. X.R.
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|U.S. Classification||368/187, 968/958, 968/910, 340/654, 968/505, 368/66|
|International Classification||G04G5/00, G04C10/04, G04G9/10, G04G5/02, G04C10/00, G04G9/00|
|Cooperative Classification||G04C10/04, G04G5/02, G04G9/10|
|European Classification||G04G9/10, G04C10/04, G04G5/02|