US 3609749 A
Abstract available in
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Description (OCR text may contain errors)
United. States Patent 1 inventor Walter}!- Mcclelland 3,346,853 10/1967 Koster et al 340/324 x Park R dg, 3,351,929 11/1967 Wagner 340/324 13;] Qpp- 1969 3,432,846 3/1969 Jones et al. 340/324 x I z f 1971 Primary Examiner-John W. Caldwell 73 A T l t C Assistant ExaminerDavid L. Trafton sslgnee t i g Attorneys-J. L. Landis and R. P. Miller ABSTRACT: A negative image cursor is provided for marking CHARACTER DISPLAY SYSTEM HAVING a selected location on a cathode-ray tube screen which dis- NEG ATWE 1M AGE CURSOR plays, 1n hurnan readable form, alphanumenc characters and 11 Claims, 9 Drawing Figs other graph1cs and symbols outpulsed at a clock rate from a reclrculatmg memory assoc1ated w1th a keyboard or computer U-S- A, ontrolled data te -minaL A equence of unblanking pulses 3 315/22, 315/30 ranged in a pattern indicative of each character to be dis-  ll!- Cl 606i 3/14 l d on th screen in dot raster form is normally applied to  FIG of Search 340/3241, th t b ith a olarit effective to form a brightened 324 A; Ins/26122130 character against a darkened screen background. During the clock period corresponding to the address of the screen loca-  Reerences C'ted tion to be marked, the polarity of the unblanking pulses in the UNITED STATES PATENTS corresponding sequence is inverted so that the marked 3,284,663 11/1966 Stocker 340/324 X character shows up darkened against a locally brightened 3,336,587 8/1967 Brown 340/324 background to define the cursor.
I '29 T I UNBLANK/NG CA 7/4005 DEFLEC T/ON 1 CIRCUITS I I ,2 TUBE C/RCU/ T5 ,8, 1 .J
SCREEN FORMAT CONTROLLER T [1627 26 P0?//;2/i3/;4P5P6P7 1 11 1 32 44 SCREEN ADDRESS CLOCK WE I. T lzzg CONTROLLER I GENERATOR SWITCH 1 G PULSE I I 3 I p0 ENERATORITQIQ P7 33 PAGE I CURSOR 46 I ar e DISPLAY l GENE/2A TO I P7 R I wR/ TE Al/A lLABLE CHARACTER l MEMORY DISPLAY I .1 I P6 I I I CMRACTER 45 REC/RCULA T/NG ANo STD/8L5 CHARACTER I TOR I MEMORY F/L TER g: 522 /9 I f f I P0 24 2/ I m P/ P7 I 22 23 DATA our To a CABLE 2/ PAIENIEU3EP28IIIII la- 'sIImuurs I i I FL/P I 38 FLOP C/RCU/ T 7a? I II II DEFLECT/ON 4 OPERATIONAL AMPLIFIER c/Rcu/rs OF was /2 I I I I I I I I I I 7'0 HOR/Z0/I/774 0 I I I I I I I I I l I ROM GATE /3/ OF 27 442 SCREEN FORMAT I CONTROLLER 3/ FROM OVERFLOW DETECTOR 37 OF SCREEN ADDRESS CONTROLLER 26 a; l g'tqg 45 gm cuRsOR' GENERATOR 46 "2 7 T T I FROMGATE I 48 s I 8 I /3/ OF I I SCREEN. I AND AND AND I CO/I/ T /Q'O ZTF RO I I A I I I I I I P0 P/ p5 I my I v I I l I FROM /sr FR M2 FROM 7 I 49 COL. OF cOL. OF COL. OF
START OF PULSE FROM 'FORMAT'CONTROLLER CHARACTER PERIOD DEFLE C T/ ON VOLTAGE I l r I j I I I '7 I I V q a2 l -'7 l CHARACTER bl PER/ODS BACKGROUND OF THE INVENTION The visual presentation, on the screen of a cathode ray tube, of digitally encoded alphanumeric characters and other graphics and symbols has now become a common way to provide rapid access to digitally encoded data at an input-output terminal of an information processing system. A variety of methods of generating and positioning the characters on the screen are in general use. Many such systems basically operate on digitally coded characters which are entered in separate locations of a local memory at the terminal; the characters are cyclically outpulsed from the memory at a clock rate to be displayed on the tube screen in a plurality of address locations individually representative of the memory locations.
The display may employ a television-type presentation in which each character to be made visible is generated in the form of a dot raster defined by a plurality of horizontally spaced vertical strokes of the tube beam, each stroke having a succession of spaced dot" positions which are selectively unblanked during the stroke to define the likeness of the character. One such dot raster is suggested in US. Pat. No. 3,423,749, issued to C. E. Newcomb on Jan. 21, 1969. In general, the required pattern of video unblanking pulses for controlling the visibility of dots in the'raster at the display address on the screen is obtained from a suitable character generator responsive to the digitally encoded character then outpulsed from the memory.
It is desirable, for purposes of isolating an existing character on display at a particular screen location or for indicating the screen location of the next character to be displayed, to provide a suitable marker at the selected location. Several schemes are now employed to provide such marker (or cursor"). One of these is suggested in 0.8. Pat. No. 3,336,578, issued to C. .I. Brown, and involves a scheme for enhancing the brightness of a selected portion of the display. Such brightening is accomplished by locally intensifying the unblanking pulses applied to the tube at the location of the selected character. Another form of cursor that has been used takes the form of underlining, i.e., brightening a lower row of dots in the raster of the character location to be marked.
A common problem when using such brightening cursors is that when the display consists of large numbers of closely spaced, relatively small characters, it may be very difficult for the operator to distinguish the marked character location from the remaining character locations without excessive concentration and mental fatigue.
SUMMARY OF THE INVENTION To solve this problem, an improved cursor indication for a display of alphanumeric characters in a data terminal has been provided by the present invention. A negative image, imposed upon a locally brightened character raster, is provided at the screen address location to be marked. Such negative image, which stands out considerably from the remainder of the characters, is accomplished by inverting the polarity of the video unblanking pulses from the character generator during the generation of the raster at the location to be marked on the screen.
To accomplish this, the video output from the character generator is normally passed through a specified one of two parallel channels operating in phase opposition; the outputs of the channels are coupled to the unblanking input of the cathode-ray tube. The parallel channels are switched for one character display period upon each occurrence of count coincidence between a pair of substantially identical binary counters, one of which is advanced in synchronism with the outpulsing of the successive characters from the memory and the other of which is normally settable by the operator to a count associated with the desired cursor location on the screen. During such switched period, the video output from the character generator is inverted to form the cursor.
The data terminal is provided with facilities for normally blanking the display of certain characters which are used to designate various control functions that are not directly significant as information to an observer. Means are additionally provided for preventing the blanking of such characters whenever they appear at the position marked by the negative image cursor, so that the operator can always see the contents of the memory location corresponding to the count set in the second counter.
BRIEF DESCRIPTION OF THE DRAWING The nature of the invention and its advantages will appear more fully from the following detailed description taken in conjunction with the appended drawings, in which:
FIG. 1 is a perspective view of a data terminal employing a cathode-ray tube display, the latter being provided with a negative image cursor in accordance with the invention;
FIG. 2 is a pictorial diagram of an enlarged portion of a selectively unblanked dot raster used to define a character on the screen of the cathode-ray tube of FIG. 1;
FIG. 3 is a block diagram of the terminal of FIG. 1;
FIG. 4 is a pictorial diagram of a screen address controller suitable for use in the arrangement of FIG. 3;
FIG. 4A is a combined block and schematic diagram of a portion of a deflection circuit suitable for use in the arrangement of FIG. 3;
FIG. 4B is a block diagram of a portion of a character generator suitable for use in the arrangement of FIG. 3;
FIG. 5 is a block diagram of a negative image cursor generator in accordance with the invention for use in the arrangement of FIG. 3;
FIG. 6 is a block diagram of a display format controller suitable for use in the arrangement of FIG. 3; and
FIG. 7 is a waveform diagram of the horizontal sweep voltage for the display of FIG. 1.
DETAILED DESCRIPTION Referring to the drawing, FIG. 1 illustrates a data terminal ll provided with a cathode-ray display tube 12. The display format on the tube screen includes, for illustrative purposes, a plurality of words (only a few of which are shown) consisting of characters distributable in a plurality of character locations I3-l3 on the screen. To facilitate the description, it will be assumed that the locations I3 are arranged in 2 vertically spaced horizontal lines 14-14 (two being shown) of 2" character positions each. (For purposes of this description, M=5 and N=4.) It will be understood that arrangements other than such a binary distribution can also be used if desired.
As best exemplified by an enlargement shown in FIG. 2 of the character R momentarily displayed at a screen address location 13a (FIG. 1), each character on the display is conventionally defined by a 7X12 rectangular matrix 16 (FIG. 2) consisting of seven vertical strokes (represented pictorially by lines 17a-17g) each having 12 successive, normally blanked dots. As shown, selected ones 18-18 of the dots are unblanked when the character is to be displayed to form the likeness of the character. (Where two or more successive dots are unblanked in each stroke, the dots run together" as shown to form a continuous line.)
The input character data to be displayed is supplied to the tenninal 11 (FIG. I) in digitally encoded form (illustratively in conventional seven-bit USASCII format). The characters are either locally generated at the terminal 11 by composing a message, e.g., on a conventional alphanumeric teletypewriter keyboard 19, or are incident from a remote location not shown, such as a computer terminal or other device, via a telephone line or other data input cable 21. The data processed by the terminal 11 may on command be transmitted back to the remote device over the cable 21.
Referring now to the overall block diagram of the terminal 11 shown in FIG. 3, the characters to be displayed are written into a local clock-controlled recirculating memory 22 via a storable character" filter 23 and an AND gate 24. The AND gate, which is normally closed, is open only in the presence of a WRITE AVAILABLE CHARACTER" indication (described below). The characters read into and stored in successive addresses of the memory are cyclically recirculated and read out in a conventional manner.
A screen address controller 26 is effective, upon the outpulsing of successive characters from the memory 22, for controlling suitable deflection circuits 27 of the cathode-ray tube 12 in such a manner that the successive address locations 13- I3 (FIG. l) on the tube screen correspond to successive address locations in the memory 22 (FIG. 3).
The output of the memory 22 is applied to a video pulse generator 28, which provides a succession of unblanking pulses to suitable unblanking circuits 29 for the tube 12. Such pulses control the visibility of the dots making up the abovedescribed character raster at each display address on the tube screen in the likeness of the corresponding digitally encoded character applied to the input of the pulse generator 28 from the memory 22.
When keyboard access to the display is selected, it is usually desirable to incorporate means for providing a movable cursor or marker to indicate the location of the next character to be displayed on the screen in a manner analogous to the window on a typewriter carriage after a key is depressed. Additionally, when changing, adding, or deleting a display character on the screen, such a cursor is useful in marking the appropriate character position. The required cursor is generated in the video pulse generator 28 as described below.
The USASCII data stored in the memory 22 may include both information characters, i.e., those which are directly significant to an operator reading the display on the screen (c.g., letters, numbers, punctuation), and control characters useful primarily for machine processing (e.g., those used to trigger the start and stop of incoming and outgoing messages, the italicizing of portions of the display, the start of a new line, etc.). As shown in FIG. 3, all of the characters (both information and control) which are entered into and outpulsed from the memory 22 may be transmitted from the terminal ill via the cable 21. For operator convenience at the terminal ll, however, a screen format controller 31 (described below) is provided for selectively displaying only the information characters upon the appropriate setting of a mode switch 32 associated therewith. For example, when the switch is set in the PAGE DISPLAY mode, the controller 31 blanks each control character (except at the cursor location); additionally, if desired, the controller is adapted to move the next information character into the space normally occupied by the suppressed control character to close up the display. A visual indication of the entire contents of the memory may be obtained by setting the mode switch 32 in the MEMORY DISPLAY position.
The various circuitry shown in FIG. 3 are synchronized by timing (or stroke") pulses from a suitable clock generator 33. The generator 33 provides, on eight separate output leads, eight staggered repetitive sequential stroke pulses (designated FO-P7) of equal duration and repetition period. The various stroke pulses Pit-P7, which are used to control the individual blocks in the drawing, are designated by one or more input lines labeled P0, Pit-P7, respectively, at such blocks. The overall cycle P-P7 will be referred to as the character period," and each individual cycle within the character period will be designated a stroke period."
During the reading out of 2 successive characters (32, in this case) from the memory 22 during a corresponding number of character periods, the screen address controller 26 causes the deflection circuits 27 to horizontally sweep the tube beam in a conventional manner through each of the corresponding 32 display locations l313 (FIG. 1) of the associated line 14, and thereafter to step the beam down to a succeeding line on the display so that a complete display frame will be completed after the beam sweeps through all 2 lines (16, in this case). At this time, a suitable vertical retrace network (not shown) in the deflection circuits 27 (FIG. 3) returns the beam to its initial position, which is assumed to be the top left-hand comer of the display. (The character period is made sufficiently small so that the frames are successively repeated at a flicker-free rate on the screen.)
In addition to providing horizontal sweeping and vertical stepping of the beam to form the frame raster, the deflection circuits 27 also generate the individual character rasters (exemplified in FIG. 2) in a conventional manner by superimposing, at each screen address location traversed by the beam during the horizontal sweep, eight horizontally spaced, vertical sweeps at the stroke rate (i.e., eight times the character rate) in synchronism with the respective stroke pulses P0P7 (FIG. 3).
As shown in FIG. 4, the screen address controller 26 comprises a pair of conventional, substantially identical (M+N) bit binary counters 34 and 36. (In this case, M+N=9.) The counter 34 (hereafter sometimes referred to as the display character register) is subdivided into a five-bit character section 34a and a four-bit line section 34b. The lowest (zero) order bit of the character section 34a is advanced one count by each stroke pulse P7 at a time one-eighth of a character period after the preceding stroke pulse P6 has triggered a readout of a character from the memory 22 (FIG. 3) to the video pulse generator 28.
Each time the character section 34a (FIG. 4) has advanced through 32 counts, a conventional overflow detector 37 supplies a momentary output pulse to reset the section 34a to zero and advance the lowest order stage of the line section 34b by one count. Additionally, as best shown in FIG. 4A, the output of the detector 37 is applied to the set input of a flip-flop 37a in the deflection circuit 27 for initiating a retrace of the horizontal sweep at the end of each line of 32 characters. (The retrace interval is assumed to be negligible for purposes of this description.)
The sweep generator, represented in simplified form at 38, illustratively consists of an operational amplifier 39 whose output is fed back to a first input thereof through an integrating capacitor 40. A variable reference voltage represented by a battery 41 is applied to a second input of the amplifier 39 to position the sweep in the usual manner.
A normally inoperative discharge circuit 42 of any suitable type is connected across the capacitor 40. The discharge circuit is activated to discharge the capacitor 40 and thereby reset the sweep in response to an output pulse from an assertive output Q of the flip-flop 37a. The flip-flop is reset at the termination of the pulse at the output of the overflow detector 37 by coupling the output of such detector to a clear input C of the flip-flop through an inverter 43.
The output of the detector 37 is also applied to the unblanking circuit 29 (FIG. 3) in a conventional manner to maintain the cathode-ray tube screen blanked during the retrace interval.
Each count registered by the line section 34b (FIG. 4) is applied to a digital-to-analog converter (not shown) in the deflection circuit 27 to provide a conventional staircase voltage which is stepped in height by one increment of voltage for each count registered in the line section until the registration of the last (16th) count. In a conventional manner, each staircase voltage increment, which persists for an interval (32 character periods) necessary for one horizontal sweep of the beam, is applied to the vertical deflection circuits for the cathode-ray tube 12 to step the beam down by one line so that successive horizontal sweeps of the beam occupy successive lines of the display. When the line section 34b overflows, a second overflow detector 44 is operated to reset the staircase generator and the line section 34b so that the deflection circuit 27 restores the position of the beam to the start of the first line of the display.
The second counter 36 (hereafter sometimes referred to as new character register") is also divided into a five-bit character section 36a and a four-bit line section 36b. Both sections of the counter 36 are wired to be selectively movable eitner up or down by increments of one count through a cursor positioning logic network 44a (FIG. 3). The network 44a may be responsive to operator-selected, nonstorable commands generated by depressing certain keys on the keyboard 19 (FIG. 1). Such nonstore commands are separated from the input data stream of storable information and control characters by means of the storable character filter 23 (FIG. 3), which in practice may be a plurality of conventional decoding gates. The network 44a is also arranged to advance the character section 360 (FIG. 4) by one count after each new character is written into the memory 22 (FIG. 3) through the AND gate 24.
Corresponding bit outputs of the counts in the counters 34 and 36 (FIG. 4) are coupled to a coincidence gate 44b. Upon coincidence of the counts (which will normally occur once during each frame at the same count if the cursor is not moved), the gate 44b will outpulse a cursor control indication as a binary one over an output lead 44c. Such indication is applied to the video pulse generator 28 to cause a cursor to be produced at the screen location scanned by the beam during the next succeeding character period.
Since, as indicated above, successive address locations on the screen are swept by the tube beam during successive character periods, the cursor may be manipulated in a desired way on the screen: e.g., to the right (by moving the count of the character section 36a forward); to the left (by moving such count backward); downward (by moving the count of the line section 36b forward); and upward (by moving such count backward).
The cursor control indication on the lead 440 is also applied to the AND gate 24 (FIG. 3) as a WRITE AVAILABLE CHARACTER indication to condition the gate 24 to enter new data from the keyboard 19 (FIG. 1) or cable 21 into the memory 22 (FIG. 3) during the stroke pulse P0 of the next character period. In addition, the lead 44c is coupled to the format controller 31 to inhibit control character blanking at the location of the cursor when the mode switch 32 is in the PAGE DISPLAY" position.
The video pulse generator 28 consists of (l) a character generator 45 containing a plurality of diode-controlled crosspoint matrices (not shown), each matrixrepresenting a unique one of the USASCII characters storable in the memory 22; and (2) a cursor generator 46 controlled by the cursor control indication on the lead 440 and interconnecting the output of the character generator 45 with the input of the unblanking circuit 29.
The character generator 45 may be of the general type disclosed in U.S. Pat. No. 2,987,715 issued to C. E. Jones, Jr., et al. on June 6, I961, or, alternatively, of the type disclosed in application, Ser. 190,496,016, filed by Robert W. Love on Oct. 14, 1965. (Such application is referred to in column 3 of the above-mentioned Newcomb patent.) In particular, the generator 45 registers each successive coded character output from the memory 22 and, starting with stroke pulse P0 of the following character period, converts each registered character into a Q-bit serial bit pattern (in the form of unblanking pulses) for application to the unblanking circuit 29 through the cursor generator 46. (0 represents the number of dot positions in a character raster, i.e., 84 in the example shown in FIG. 2.)
The unblanking pulse pattern is produced in synchronism with the generation of the character raster at the corresponding location on the screen. The seven strokes of the character raster are synchronized with the stroke pulses P0-P6 (FIG. 3) from the clock generator 33, while the last stroke pulseP7 provides one stroke period of intercharacterspacing. (During this latter period, the screen is blanked.) It will be understood that in some applications, it may be desirable to increase the number of strokes between characters.
Within the character generator 45, the particular .crosspoint matrix representing the coded character registered at its input is selected in a conventional manner in accordance with the states of the respective bits making up the USASCII format in which such character is encoded. Once the appropriate matrix is selected, the required code pattern is generated by exciting, in succession, the intersections of all rows of the matrix with successive ones of the columns of the matrix. (The number of columns corresponds to the number of strokes in a character raster, seven in this case; the number of rows corresponds to the number of dot positions in each stroke, I2 in this case.) Selected ones of the intersections in each matrix are provided with diodes interconnecting the associated rows and columns. The physical arrangement of the diode-controlled intersections within the matrix follows the physical shape of the character to be defined, in the general manner shown in FIG. 2 with each position 18 defining the location of a diode.
Each bit of the unblanking pulse pattern corresponds to the excitation of a separate intersection in the associated matrix. Arbitrarily, a binary one of such bit occurs when the excited intersection is diode-equipped and, in particular, is represented by a pulse appearing at the output of the associated column when the diode is made conductive. A binary zero of the bit represents the column output of an excited intersection that is not diode-equipped; such output is manifested by the absence of a pulse.
The resulting 84bits generated during the scanning of the l2 rows of each successive one of the seven columns in the selected character matrix are successively coupled to a common video output lead 47 (FIG. 3) by a gating arrangement 48 (FIG. 48) forming part of the character generator 45. With the gating arrangement 48, the output of the seven columns of the selected matrix are respectively applied to the first inputs of a plurality of AND gates 48a-48g. Stroke pulses P0-P6 are individually coupled to like second inputs of the successive gates 48. The output of the screen format controller 31 is applied in common through an inverter 49 to like third inputs of the gates 48 so that the detection of a control character by the controller 31 when the latter is in the PAGE DISPLAY mode will normally disable all the gates 48 during the character period in which such control character would normally be displayed on the screen.
Thus, except when inhibited by the screen formatcontroller 31, the first 12 bits representing the first column in the selected character matrix are coupled to the lead 47 during the first stroke (coincident with P of the corresponding character raster on the screen. The next 12 bits representing the second column in the selected matrix are coupled to the lead 47 during the second vertical stroke (coincident with P of the character raster; and so on.
As will be seen below, the cursor generator 46 (FIG. 3) provides a direct communication between the video output lead 47 and the unblanking circuit 29 except when a cursor control indication is present on lead 44c. Normally, therefore, as the beam traces out a character raster, the beam is selectively unblanked when the bits of the pattern outpulsed from the character generator 45 during such raster generation exhibit a binary one. Since the dot locations in the character raster corresponding to the occurrence of the unblanking pulses represent the diode-equipped intersections in the selected cross-point matrix, the likeness of the associated character will normally be traced out, as shown in FIG. 1, in brightened form against the normally dark screen background.
In accordance with the invention, the cursor generator 46 (FIG. 3) is arranged to provide a negative or reverse image of the dot raster at the screen location corresponding to the count in the new character register 36 (FIG. 4); such screen location is addressed in the character period following that in which the cursor control indication is generated on lead Me. With this arrangement, the portions of the marked character raster that are ordinarily left blanked arebrightened, while those portions that are ordinarily brightened to form the character are blanked. In the illustrative screen display shown in FIG. 1, the negative image cursor (designated by the numeral is positioned at the location of the erroneous letter O on the first line 14 at the end of the word that obviously should read negotiations.
It will be appreciated that this form of cursor stands out much more satisfactorily than those using enhanced brightening, underlining, and the like. Accordingly, such cursor is particularly advantageous when crowded displays having a large number of relatively small characters are employed.
An illustrative embodiment of the negative-image cursor generator 46 is shown in FIG. 5. The video output lead 47 from the character generator 45 is applied in parallel to the inputs of a pair of parallel video channels 111 and 112. The channel 111 includes a single AND gate 113, to a first input 113a of which the lead 47 is coupled. The channel 112 includes a second AND gate 114 having a first input 114a coupled to the lead 47 and an output coupled to an inverter 116.
The channel 111 is normally kept open by a conditioning signal applied to a second input 113b of the gate 113 in the manner described below. The gate 114, on the other hand, is normally closed so that the channel 112 is deactivated.
The channel 111 is normally operative to couple video unblanking pulses from the character generator 45 directly to the unblanking circuit 29 with a polarity effective to display the characters in brightened form against a darkened screen background. When the cursor control indication appears on lead 440, however, the gate 113 is closed and the gate 114 is opened to couple the video pulses via channel 112 to the unblanking circuit 29 with their polarity inverted because of the action of the inverter 116. The resulting reversal of the bit states at the screen location of the cursor defines a darkened character against a brightened background.
In order to effect the above-described operation of the channels 111 and 112, the output lead 440 from the screen address controller 26 is applied directly to a set prime input S of a flip-flop 117 and through an inverter 117a to a clear prime input C thereof. With this arrangement, when a binary one" (representing the occurrence of a cursor control indication) appears on the lead 44c and thus the input S, a subsequent excitation of a trigger input T of the flip-flop 117 will cause an assertive output Q thereof to assume its active or binary "one" state; on the other hand, when a binary zero appears on lead 440 (as during the absence of a cursor control indication), the action of the inverter 117a will activate the clear prime input C of the flip-flop 117; and the subsequent application of a trigger pulse to the input T will reset the output to its quiescent binary "zero" state. The stroke pulse P is coupled to the trigger input T of the flip-flop 117.
The output 0 of the flip-flop 117 is coupled to a first input of an AND gate 118. A second input of the AND gate is coupled to stroke P0. The output of the AND gate 118 is coupled to a direct set input 8,, of a flip-flop 119 (no separate trigger input is employed here). A direct clear input C of the flipflop 119 is coupled to stroke pulse P7.
An assertive output 0 of the flip-flop 119 is coupled to the second input 114!) of the AND gate 114 in the channel 112. A complementary, or reset, output Q of the flip-flop 119 is coupled to the second input 113b of the AND gate 113 in the channel 1 1 l.
Ir operation, the binary one normally present at the output 0 of the flip-flop 119 will keep the gate 113 open while the binary zero normally present at the output Q of flip-flop 119 will keep gate 114 closed. When'a cursor control indication appears on lead 440, the input S of the flip-flop 117 is primed so that stroke pulse P5 switches its assertive output Q to its active state and thereby primes the AND gate 118. Upon the occurrence of the stroke pulse PO at the beginning of the next character period, the AND gate 118 is opened to trigger the set input S of the flip-flop 119. This action reverses the states of the outputs Q and Q of the flip-flop 119. As a result, the gate 113 is closed and the gate 114 is opened to invert the video pulses applied to the unblanking circuit 29.
By the time the next succeeding stroke pulse P5 occurs, the cursor control signal will have been terminated to prime the input C of the flip-flop 117. The stroke pulse P5 will therefore reset the output Q to disable the AND gate 118.
Two stroke periodsgter, the pulse P7 will reverse the states of the outputs Q and Q of the flip-flop 119 to reopen channel 111 and reclose channel 112.
As indicated above, facilities are provided in the screen format controller 31 (FIG. 3) to keep the negative-image cursor visible on the screen irrespective of whether the mode switch 32 is set in the PAGE DISPLAY or the MEMORY DISPLAY mode. The resulting arrangement of the controller 31 is shown in FIG. 6. The digitally encoded characters outpulsed from the memory 22 are applied to a character recognition circuit which, in practice, may be a plurality of conventional decoding gates (not shown) individually responsive to control characters but not to information characters. The outputs of such gates may be wired together so that a binary one appears on an output lead 121 of circuit 120 during each character period that a control character is outpulsed from the memory.
The output of circuit 120 is applied directly to one input of a NAND gate 122 and through an inverter 123 to one input of a NAND gate 124. Corresponding second inputs of the gates 122 and 124 are coupled to stroke pulse P7. The outputs of the gates 122 and 124 are individually applied to first inputs of a pair of NAND gates 126 and 127, whose outputs are respectively cross-coupled to second inputs thereof to define a flipflop 128. The output of the flip-flop (taken from gate 127) is applied through an inverter 129 to a first input of a multipleinput AND gate 131. Since the flip-flop 128 is set and reset by the successive stroke pulses P7 when a control character is detected, a binary one will appear at the output of the inverter 129 during the character period following the detection of the control character. Thus, the first input of the gate 131 is excited during the period that the control character would normally be displayed on the screen. The remaining inputs are excited in the manner described below to condition the gate for operation.
When the controller 31 is properly conditioned, its output (which is taken from the gate 131) is in the form of a pulse having a one character period duration coincident with the above-described output of the inverter 129. Such output pulse is applied to the AND gates 480-483 (FIG. 4B) in the character generator 45 to maintain the display blanked for the duration of the normal display period of the detected control character.
If desired, the output of gate 131 may also be applied through a manually settable switch 142 (FIG. 4A) to the first input of the operational amplifier 39 in the deflection circuit 27 to stop the buildup of charge on the capacitor 40 for the duration of the output pulse from the gate 131. This in turn stops the sweep during the corresponding character period (as depicted schematically in FIG. 7) and effectively closes up" the space normally occupied by the blanked control character. Thus, when the switch 142 (FIG. 4A) is set in its closed position, the screen location normally assigned to the blanked control character is occupied by the following information character outpulsed from the memory 22 (FIG. 3). The remaining information characters on the associated line will be correspondingly shifted.
In order to condition the AND gate 131 (FIG. 6) for operation, a second input thereof is coupled to the output of the mode switch 32. When the PAGE DISPLAY mode is selected, a binary one" is applied to the second input of the gate 131. A third input of the gate 131 is controlled by the cursor control indication on lead Me in such a manner (described below) that a deactivating binary zero" is applied to such third input when the cursor is present. This assures that, despite the coincidence of a PAGE DISPLAY mode selection and the outpulsing of a control character from the memory, the screen address of an outpulsed control character will not be blanked in the presence of the cursor at that location. Thus, the operator can always see the contents of the memory position corresponding to the count set in the new character register 36 (FIG. 4).
In order to instrument this cursor override function in the PAGE DISPLAY mode, the lead 440 (FIG..6) is applied to a first input of an AND gate 133. A second input of the AND gate 133 is coupled to stroke pulse P7. The output of the AND gate 133 is coupled to a reset input of a flip-flop 134. A reset output of the flip-flop 134 is coupled to a set prime input S thereof so that such input is normally primed. A clear prime input C of the flip-flop is normally deactivated. A trigger input T of the flip-flop is coupled to stroke pulse P6. An assertive output Q thereof is coupled to the third input of the gate 131.
During the stroke pulse P6 of a character period in which a control character is outpulsed from the memory 22 in the PAGE DISPLAY mode, the normally set flip-flop 134 is triggered to apply a binary one to the third input of the gate 131; the latter remains closed, however, since the first input thereof is inactive. During the following stroke P7, when the flip-flop 128 is activated to apply a binary one to the first input of the gate 131, the gate 133 and thus the reset input of the flip-flop 134 will remain deactivated in the absence of a cursor indication on lead 44c so that a binary one" remains on the third input of the gate 131. Since the second input of gate 131 is also coupled to a binary one by virtue of the setting of mode switch 32 to the PAGE DISPLAY mode, the gate 131 will be opened during such stroke pulse P7 to blank the display of the control character during the next character period.
However, when a cursor control indication is present on lead 440 at the same time that a control character is outpulsed from the memory, the occurrence of stroke pulse P7 during the corresponding character period will open the gate 133 to reset the flip-flop 134. A deactivating binary zero is therefore applied to the third input of AND gate 131 during the next character period to inhibit the blanking of the control character at the location of the cursor on the screen.
What is claimed is:
1. In a normally blanked CRT display apparatus for characters that are successively applied to the apparatus for display at a succession of separate address locations thereof:
means for generating a succession of unique unblanking bit patterns individually representative of the successively applied characters;
means for normally outpulsing the successive bit patterns in serial form to the apparatus to selectively unblank the corresponding address locations; and
means rendered effective during the outpulsing of only a selected one of the successive bit patterns for inverting the states of the associated bits to provide a negative image cursor indicating the location of a selected character.
2. In a CRT display apparatus for alphanumeric characters which are storable in the form of digitally coded data in a plurality of separate locations of a memory and which are cyclically outpulsed from the memory at a clock rate, wherein characters outpulsed from successive locations of the memory are applied to a normally blanked display in a plurality of address locations individually representative of the memory locations and addressed in synchronism therewith, an improved arrangement for visibly marking a selected address location on the display to form a cursor, which comprises:
means operative at the clock rate for generating a succession of unique unblanking bit patterns individually representative of the characters stored at the successive locations of the memory;
means for normally applying the bits of each generated bit pattern in serial form to the apparatus to selectively unblank the corresponding address location, said location being unblanked when the then-occurring one of the bits is in a prescribed one of two states so that the location is normally defined by a prescribed contrasting pattern on the display; and
means rendered effective during the address of the selected location on the display for inverting the bits of the corresponding bit pattern so that the display at the selected address location is locally defined by the negative of the normal contrasting pattern.
3. Apparatus as defined in claim 2, further comprising, in combination, first and second multibit binary counters having a bit capacity at least equal to the number of address locatrons;
means for successively advancing tiifita'cdiimfimh' h increments of one count at the clock rate in synchronism with the outpulsing of successive characters from the memory; and
means for independently moving the second counter through a selectable number of counts to control the location of the cursor.
4. Apparatus as defined in claim 3, further comprising coincidence means for generating a cursor control indication during the clock period in which the counts of the first and second counters coincide.
5. Apparatus as defined in claim 4, further comprising means rendered effective upon the generation of the cursor control indication for advancing the second counter by one count.
6. Apparatus as defined in claim 4, in which the inverting means comprises means rendered effective upon the generation of the cursor control indication for reversing the states of the bits in the bit pattern applied to the display during the next clock period.
7. Apparatus as defined in claim 6, in which the display is provided with an unblanking input, and in which the statereversing means comprises, in combination, first and second parallel video paths interconnecting the output of the bit pattern applying means and the unblanking input, the outputs of the respective paths being in phase opposition:
a first bistable circuit exhibiting a first stable state when a set input thereof is activated and a second stable state when a clear input thereof is activated;
mean for enabling the first path when the first bistable circuit is in its first state and for enabling the second path when the first bistable circuit is in its second state;
a normally disabled control gate;
means rendered effective upon the occurrence of the cursor control indication for conditioning the control gate for operation at the beginning of the next clock period;
means operative at the start of said next clock period for momentarily operating the conditioned control gate to activate the set input of the first bistable circuit; and
means rendered effective at the end of said last-mentioned next clock period for activating the clear input of said first bistable circuit.
8. Apparatus as defined in claim 7, in which the conditioning means comprises, in combination, a second bistable circuit exhibiting a first stable state when a set input thereof is activated and a second stable state when a clear input is activated;
means for coupling an output of the second bistable circuit to the control gate to condition the latter when the second bistable circuit exhibits its first state;
means for activating the set input of the second bistable circuit during the clock period in which the cursor indication is generated; and
means for activating the clear input of the second bistable circuit at the end of the next clock period.
9. Apparatus as defined in claim 4, in which the display has up to 2 address locations arranged in N lines of M characters each, each of the first and second counters has a 2 count capacity, and the apparatus further comprises, in combination, means for scanning the address locations in successive lines of the display at intervals of M clock periods in synchronism with the advance of the first counter through M counts;
means coupled to the output of the memory for detecting selected ones of the characters; and
means normally rendered effective upon the detection of one of the selected characters for blanking the display during the next clock period.
10. Apparatus as defined in claim 9, further comprising means rendered effective upon the generation of the cursor control indication for inhibiting the operation of the blanking means during the next clock period.
11. Apparatus as defined in claim 9, further comprising means rendered effective upon the detection of one of the selected characters for stopping the scanning means during the blanking of the display.