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Publication numberUS3611117 A
Publication typeGrant
Publication dateOct 5, 1971
Filing dateNov 20, 1969
Priority dateSep 25, 1959
Also published asDE1810099A1, DE1810099B2
Publication numberUS 3611117 A, US 3611117A, US-A-3611117, US3611117 A, US3611117A
InventorsSchneider Heinz
Original AssigneeWandel & Goltermann
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Voltage stabilizer with reversible binary counter for alternating-current lines
US 3611117 A
Abstract  available in
Images(4)
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Claims  available in
Description  (OCR text may contain errors)

United States Patent [72] Inventor Heinz Schneider Eningcn, Germany [2]] Appl. No. 878,334 [22] Filed Nov. 20, 1969 [45] Patented Oct. 5, 1971 [73] Assignee Wandel u. Goltermann Reutlingen, Germany [32] Priority Nov. 21, 1968 [33] Germany [31] P 1810 099.7

[54] VOLTAGE STABILIZER WITH REVERSIBLE BINARY COUNTER FOR ALTERNATING- CURRENT LINES 12 Claims, 7 Drawing Figs.

[52] US. Cl 323/45, 323/62, 323/75 E [51] Int. Cl G05f 1/30 [50] Field of Search 323/22 SC, 24, 45, 48, 50, 62, 75 E [56] References Cited UNITED STATES PATENTS 3,018,431 1/1962 Goldstein 323/45 3,201,683 8/1965 Hjermstad et al 323/45 10/1967 lngman 4/1968 May Primary ExaminerJ. D. Miller ABSTRACT: A plurality of transformers, having their secondary windings cascaded in either or both conductors of an AC line to be regulated, have graded voltage-transformation ratios corresponding to binary voltage increments to be impressed in aiding or opposing relationship upon the line in order to compensate for deviations of its output voltage from a predetermined magnitude. The transformers are fed from a common source of alternating current, synchronized with the line current, via enabling circuits responsive to the setting of respective stages of a reversible binary counter which is stepped forward or backward by pulses from a voltage-level sensor, a switchover circuit reverses the sense of the count upon the arrival of the counter in its zero positions, with simultaneous reversal of the phase of the impressed compensating voltages, to provide both positive and negative counts and to prevent discontinuities in the compensating voltage.

B INTFGRIITUR? PATENTEDUBT SIS?! 3, 11 117 SHEET u [1F 4 MINI?!"- |H||||| HHlll llllll fs Y 1 FIG 7 llllll Heinz Schneider INVENTOR.

Attorney VOLTAGE S'IABILIZER WITH REVERSIBLE BINARY COUNTER FOR ALTERNATING-CURRENT LINES My present invention relates to a system for stabilizing the output voltage of an alternating current line.

Conventional voltage stabilizers of this type, using saturable reactors or controlled rectifiers, operate with a certain lag which not only delays the reestablishment of a desired voltage level but also may lead to prolonged hunting. In practice, the restoring action of such stabilizers may extend over to half-cycles of the operating frequency and may introduce distortions with a harmonics content of 2-5 percent. This distortion must be compensated by harmonics suppressors, thereby further complicating the system. Other types of voltage stabilizers, in which a substantially instantaneous correction is achievable through the use of variable-gain amplifiers responsive to a detected voltage deviation, require the expenditure of considerable energy to compensate for the losses in the essentially resistive amplifying elements.

The general object of my present invention is to provide an improved voltage stabilizer which avoids the aforestated drawbacks and provides virtually instantaneous correction with practically no distortion and without major expenditure of supplemental energy.

This object is realized, pursuant to the present invention, by the insertion of a series of transformers in an AC line to be regulated, the voltage-transformation ratios of these transformers being graded for the introduction of different voltage increments into the line under the control of respective stages of a reversible counter responsive to positive or negative deviations of the line voltage from a predetermined magnitude.

The reversible counter, which is preferably of the binary type, advantageously is provided with switchover means responsive to the arrival of the counter at the lower end of its range (thus, in an all-zero position) for reversing the sense of the count in response to applied stepping pulses and for concurrently inverting the phase of the voltage increments introduced by one or more of the line transformers. The switchover in the all-zero position affords a continuous transition from positive to negative counts, or vice versa, and prevents major jumps in the impressed compensating voltage.

The number of the line transformers, or of their cascaded secondary windings, need not necessarily equal the number of counter stages but may constitute a multiple of the latter number if, with the aid of a suitable binary coder, the sinusoidal driving voltage applied to the corresponding primary windings is multiplied by different constants, depending on which stage among a group of such stages assigned to a respective line transformer has been set.

The driving voltage for the line transformers, synchronized with the line voltage to be stabilized, may be derived from the line directly or through the intermediary of a phase reverser. In either case, the line transformers are selectively enabled to pass an aiding or opposing fraction of this sinusoidal driving voltage. With the driving voltage completely suppressed in the input of any such line transformer, its secondary winding constitutes a virtual short circuit; if its aiding or opposing phase is present, the voltage increment impressed upon the line will be of the corresponding polarity.

It is possible, however, to simplify the'system by keeping all the line transformers constantly energized with driving voltage of aiding or opposing phase; in this case, a near balance of the several voltage increments concurrently introduced into the line can be achieved by reversing the phase of the highestorder increment (of relative magnitude 2") with reference to all the other voltage increments (of relative magnitudes l, 2, 4,...2").

For the selective enabling of the line transformers in this manner, I prefer to utilize semiconductive devices such as two-way solid-state controlled rectifiers of the type known as triac. A pair of such triacs, one in series and one in parallel with the associated transformer primary, can be used for alternately short circuiting or driving (with either phase) the corresponding secondary.

The above and other features of my invention will be described in greater detail hereinafter with reference to the accompanying drawing in which:

FIGS. 1, 3 and 5 are circuit diagrams of different embodiments;

FIGS. 2, 4 and 6 show partial modifications of the system of FIGS. 1, 3 and 5, respectively; and

FIG. 7 is a set of explanatory graphs relating to the system of FIG. I.

In FIG. 1, l have shown a transmission line with two conductors L', L" connected between a pair of input terminals I and a pair of output or load terminals 2. A multiplicity of voltage transformers 4a,...4n (only two shown) have their secondary windings inserted in conductor L, in series with the primary winding of a current transformer 3. The primary windings of transformers 4a,...4n are shunted by respective triacs l2a,...l2n and are in series with other triacs 6a,...6n, each pair of triacs being controlled by a respective trigger stage l4a,...l4n. All of these transformer primaries are connected, through the respective triacs 6a,...6n, across a pair of bus bars 8, 9 emanating from a source of reversible driving voltage 10 energized from line L, L". Q

A voltage-sensing circuit, connected across the output end of the line, includes a voltage transformer 16 working into a rectifier 17; a constant-voltage source 21 superimposes its output upon that of rectifier 17 with the aid of a pair of resistors 18, 20. The resulting composite voltage is fed to an integrator 19 working into a threshold device 22 which has a pair of output leads 22 22, terminating at an electronic switchover network 23; a third output lead 22, of device 22 is returned to the input of integrator 19 for resetting same to zero whenever the device 22 responds to either a positive or a negative potential exceeding its corresponding threshold level.

A reversible binary counter 24, with stages 240,...24n, has a forward-counting input F and a reverse counting output R adapted to receive stepping pulses P from either of the two output leads 22,, 22, of threshold device 22 in accordance with the setting of switch 23. This switch is reversible by the output of a coincidence gate 25 having inputs connected to all the counter stages; gate 25 responds when all the bits concurrently stored in the several counter stages are either 0 or I. Another output lead ll of gate 25 terminates at voltage source 10 to reverse the polarity of its output in step with the reversal of switch 23.

The stages 24a,...24n of counter 24 work into individual stages 26a,...26n of a buffer register 26 which is triggerable by the output of a zero detector 27 energized from transformer 3. Detector 27 generates a pulse whenever the line voltage goes through zero on its positive (or negative) swing, i.e., once per cycle. At that instant, the settings of the counter stages as stored in register 26 are transferred to the corresponding trigger circuits 140,...1411, which may be constituted by flipflops, whereby these circuits are either maintained in their previous condition or tripped into their alternate condition to unblock the associated triacs 6a,...6c or l2a,...l2n. In the first case, a corresponding voltage increment is impressed upon line conductor L to compensate for a deviation of the load voltage from a desired level as determined by the setting of reference-voltage source 21; in the second case, the corresponding line transformer is short circuited so as to constitute only a negligible impedance.

The voltage-transformation ratios of transformers 4a,...4n are graded in binary steps to introduce voltage increments of relative magnitudes i1, 1:2,...in, respectively. Through the cumulative superposition of these increments, the line voltage can be stabilized with an accuracy determined by the magnitude of the unit increment introduced through transformer 40.

In the operation of the system of FIG. 1, the appearance of a clock pulse cp on the output lead 27, of zero detector 27 changes the state of one or more of the trigger circuits l4a,...l4n if, in the immediately preceding cycle, the voltage sensor generally designated 28 has picked up a voltage deviation exceeding the negative or positive threshold of device 22. If the resulting voltage correction is still not sufficient to compensate for the deviation, device 22 generates an output pulse on lead 22, or 22,, depending on the polarity of this deviation. Regardless of that polarity, the integrator 19 is immediately reset and, according to the magnitude of the deviation, may cause the generation of one or more additional stepping pulses of the same polarity within the cycle, thereby increasing or reducing the count of pulse counter 24 in accordance with the number of pulses thus generated. The next clock pulse, therefore, finds the counter in a position in which a different number of register stages 26a,...26n are set to switch the associated trigger circuits l4a,...l4n.

Let us assume, for example, that in response to underenergization of line L, L" the device 22 generates stepping pulses on lead 22, and that switch 23 transmits these pulses to forward" input F of counter 24, causing the intervention of one or more line transformers 4a,...4n in aiding relationship with the line voltage. If, as the result of overcorrection or because of circuit changes, the line voltage thereafter becomes excessive, the stepping pulses P are shifted to lead 22 so as to reach the input R with ensuing reduction of the count. If, in the course of such reduction, the counter 24 returns to zero, coincidence gate 25 reverses the switch 23 and (e.g., through an associated bistable circuit or flip-flop not shown) the voltage source so that the next stepping pulse or pulses again advance the counter into or past its No. 1 position in which transformer 4a is energized. With the alternating voltage on bus bars 8, 9 now in phase opposition to the line voltage, the counter output is weighted negatively so that the line overvoltage is further reduced until equilibrium is established.

Advantageously, gate also blocks the energization of input R as long'as the counter 24 is in its zero position; in the event of a full count, i.e., with the counter at the opposite end of its range, gate 25 may similarly inhibit the energization of input F. By these measures the counter is prevented from overor undershooting its range which would cause the system to behave erratically. Naturally, complete compensation is not possible as long as the voltage deviation exceeds the range of voltage increments afforded by the several line transformers 4a,...4n

The integrator 19 may include a square-law amplifier or other nonlinear impedance. If the time constant of this integrator is sufficiently small, as compared with a cycle length of the line voltage, enough pulses may be generated during each line cycle to step the counter through a major part of its range or even past the limiting position of ill ...11. In this case, with the gate 25 arranged to reverse the switch 23 also in that limiting position, the system may operate in the manner illustrated in FIG. 7 where graph (a) represents the composite voltage developed at the junction of resistors 18 and 20. This composite voltage consists of a raw-rectified sinusoidal voltage V from circuit 17 superimposed upon a constant voltage E of opposite polarity, obtained from circuit 21, the voltage level E representing a reference potential between two levels V, and V which for purposes of this explanation may be considered the positive and the negative threshold established by the device 22. The spacing of these levels, in relation to the amplitude of the sine wave, has of course been exaggerated for the sake of clarity.

The ratio of the integrated areas (horizontally shaded) above level V, and below level V,, respectively designated by a plus and a minus sign, determines the position of the counter 24-and therefore the setting of the buffer register 26at the instant of emission of a clock pulse cp by the zero detector 27; these clock pulses, shown in graph (c) of FIG. 7, occur at instants t coinciding with every other trough of the wave v. Graph (b) shows the stepping pulses P, and P respectively appcaring on leads 22, and 22, of FIG. 1 during integration of the negative and positive areas; the actual polarities of these pulses are, ccourse, arbitrary. The wavy line in graph (c) represents the resulting advances and retreats of the counter with the forward strokes indicated at fs and the reverse strokes at rs. In the cleared position 0...0 the sign of the corrective voltage increments changes, as explained above, so that the counter can be considered as having a range between a positive limit-H ...l and a negative limit 1 I.

In the first cycle partly shown in FIG. 7, the system is supposed to be in balance, with the positive and negative areas of the composite voltage curve in graph (a) substantially equal. Under aconditions the clock pulse cp marking the beginning of the next cycle occurs with the counter in its all-zero position as indicated at C,,. In the immediately following cycle,as assumed for the purpose of this description, the load voltage suddenly rises so that the positive pulse train P is lengthened with reference to the negative pulse train P,; with switch 23 in a position in which the pulses P are applied to backwardcounting terminal R, counter 24 executes a reverse stroke rx which here is long enough to overstep the negative range limit I ...l. As the counter reaches that limit, gate 25 reverses the switch 23 so that the final phase rs of this reverse stroke is carried out in a forward-counting direction, this phase terminating with the end of the corresponding pulse train P The next pulse train P, then reverses the sense of counting in an inverted phase fs' of another forward stroke fs, with gate 25 again tripping the switch 23 in the full-count position. ln,the example chosen, this forward stroke fs is shown to stop short of the opposite range limit +l ...l. There follows another backward stroke rs with an inverted terminal phase rs and a further forward stroke fs with an inverted starting phase fs'. During the latter stroke there occurs the next clock pulse cp which finds the counter in a position C wherein one or more register stages areset and the corresponding line transformers are energized in opposing phase relationship with the line voltage to compensate for the excessive load voltage.

In the third cycle shown in FIG. 7, an overcorrection is assumed to have occurred whereby the peaks of the sine wave have been lowered to such an extent that the negative pulses P, are more numerous than the positive pulses P As a result, the counter on its forward strokes fs reaches an inversion point at the positive range limit +l l; the next clock pulse cp then occurs at an instant when the counter registers a positive reading +C to introduce corrective voltage increments in aiding phase relationship with the line voltage.

In the preceding description it has been assumed that no polarity reversal of voltage source 10 takes place in the fullcount position of the counter. If the gate 25 causes such a reversal not only in the all-zero position but also in the all-one position of the counter, the inverted portions of the forward and reverse strokes fs and rs will be as diagrammed at fs" and rs". It will be noted that this does not cause any shift of the reading points C C and +C.

In FIG. 2'I have shown a partial modification of the system of FIG. 1 in which the junction of resistors 18 and 20 is connected to an input of a gate 30 forming part of an analogdigital converter 28 replacing the voltage sensor 28. Gate 30 is paired with another gate 31, the two gates being alternately blocked and unblocked by a control circuit 29 to feed an integrator 19' replacing the integrator 19 of FIG. 1. With gate 30 conductive, integrator 19' receives the composite voltage from elements 17 and 21 of FIG. 1, i.e., a raw-rectified voltage superimposed upon a DC potential of the opposite polarity as described with reference to graph (a) of FIG. 7; with gate 31 open, a pulse generator 33 discharges the integrator 19' through a switch 34 with a succession of positive pulses P or negative pulses P" whose polarity is opposite that of the output voltage of integrator 19'. A comparator 22', similar to threshold device 22 of FIG. 1, determines positive or negative deviations of the integrator output from a reference potential, preferably zero, to generate a control voltage on either of two output leads 22, and 22,. Depending on the lead energized, a double gate 38 is unblocked to pass the output of pulse generator 33 to a corresponding lead 38, or 38 in the form of stepping pulses P fed to a respective counter input F or R (FIG. 1).

Gate control 29 is triggered by gating pulses gp on an output lead 27, of zero detector 27 occurring at the beginning of each half-cycle of the line voltage, in contradistinction to the transfer pulses cp delivered once per cycle over lead 27 to the buffer register 26 of FIG. 1. Device 29 may include a flip-flop alternately energizing its output leads 29,, 29 in response to any such gating pulse. On a further output lead 29 energized for example concurrently with lead 29,, device 29 enables the comparator 22 to start a discharge interval during which the gate 38 is unblocked for stepping the counter 24 (FIG. 1) either in a forward or in a backward sense, depending on the polarity of the integrator output; when this output decays substantially to zero in response to the progressive discharge of the integrator 19' by the pulses P or P", the discharge interval is terminated by a signal transmitted from device 22' via a lead 22, to device 29. The appearance of the zero signal on lead 22 causes or coincides with the blocking of the transmission of discharging pulses at switch 34 and/or gate 31 so that the integrator 19' retains its charge until gate 30 is reopened at the beginning of the next cycle. The number of such discharging pulses, and therefore the number of stepping pulses P concurrently emitted over lead 38 or 38 is thus proportional to the voltage output fed to comparator 22' at the end of the first half-cycle.

If the pulse cadence of generator 33 is sufficiently high, the integrator 19' can be completely cleared within the second half of each cycle. With a lower generator frequency, the discharge interval may be intermittently spread over a succession of cycles.

The system of FIG. 3 is broadly similar to that of FIG. 2, corresponding elements having been designated by the same reference numeral preceded by a 1" in the position of the hundreds digit. In contradistinction to the arrangement shown in FIG. 1, however, voltage transformer 116 is connected across line terminals 101 (in series with the primary of transformer 103) rather than line terminals 102, thus on the input side rather than the load side of the corrective network represented in FIG. 3 by a rectangle 75. In order to compensa'te for the voltage drop across that network, I provide a voltage generator 61 which is bridged across the secondary of transformer 103 in parallel with zero detector 127. The compensating voltage delivered by device 61 is proportional to the line current and, therefore, to the variable voltage drop across the load. Thus, gate 130 receives the sum of three voltages delivered via a resistor 60 in the output of compensator 61 and the resistors 118, 120 in the outputs of rectifier 117 and reference source 121.

Comparator 122, when triggered by an output from integrator 119, activates a constant'current source 69 which, during the discharge interval initiated by the switchover of control device 129 in response to a clock pulse from detector 127, delivers to the integrator via gate 131 a discharging current of a polarity opposite that of the integrator output. During the time required for this current to restore the integrator output to zero, gate 138 is unblocked by the comparator 122 to pass a train of equispaced stepping pulses to one of the two inputs of counter 124, depending on the setting of switch 134 which operates like switch 34 in FIG. 2 under the control of the comparator. Switch 134 may also incorporate the equivalent of the device 23 (FIG. 1) serving to reverse the connections to the counter inputs under the control of a coincidence gate not shown in FIG. 3. interval ,The cadence of the stepping pulses produced by generator 133 is preferably very high, compared with the frequency of the line voltage, so that the number of pulses required to discharge integrator 119 can be generated within a short fraction of a half-cycle. When the comparator 122 senses the clearing of the integrator, it transmits to the gate control 129 a signal terminating the discharge interval as described above. Thus, the number of stepping pulses is again proportional to the magnitude of the integrator output at the end of the first half of any cycle.

FIG. 4 shows a corrective network 75 which may be substituted for the network 75 of FIG. 3, or for corresponding circuitry in other embodiments, and which is designed to increase the number of numerical combinations of corrective voltage increments available with a given number of line transformers. In this arrangement, the primary of each line transformer 104a,...104n is selectively energizable with four different voltage levels (including zero voltage) from the secondary winding of an ancillary transformer 85, energized by voltage source 210, via four bus bars 80, 81, 82, 83. Bus bar is directly connected to one terminal of one primary of each line transformer and is connected to the other terminal of that primary through a respective triac 70a,...70n. The remaining bus bars are connected to the last-mentioned terminals via respective triacs designated 71a,...71n in the case of bus bar 81, 72a,...72n in the case of bus bar 82, and 73a,...73n in the case of bus bar 83. The triacs can be selectively fired by trigger circuits a,...90n 9la,...91n, 920,...92n and 93a,...93n. These trigger circuits are under the control of a coder 95 receiving the output of buffer register 126 (FIG. 3).

With the voltage differences between bus bar 80 and bus bars 81, 82 and 83 having the ratio of, say l:2:3, the first line transformer 104a may introduce voltage increments of relative magnitudes 0, i1, i2, :3. The second line transfon'ner, not shown, would have outputs of relative magnitudes O, :4, i8, :12. Similarly, the third line transformer would selectively produce voltages of relative magnitudes 0, il 6, :32, 148; and so forth.

According to FIG. 5, in which elements corresponding to those previously described have been designated by the same reference numbers preceded by a 2 in the position of the hundreds digit, the source of driving voltage has been reduced to a pair of bus bars 208, 209 and connected directly across line L, L". Bus bar 208 is tied to the midpoint of the primaries of all line transformer 204a,...204n whereas bus bar 209 is connected to the extremities of these primaries via respective triacs 206a,...206n and 212a,...2l2n. As before, the triacs are selectively fired by trigger circuits 214a,...2l4n under the control of counter 224 and register 226, except that in this embodiment each transformer primary is always energized from bus bars 208, 209 via one of the associated triacs in either aiding of opposing relationship with the line voltage.

When the load voltage of this system substantially matches its rated value, transformer 204n is energized in phase opposition to all the other line transformers, e.g., by conduction of triac 212n with simultaneous conduction of the triacs 2060 etc. of all the lower stages. The resulting overall voltage increment, of additive or substractive sign, is equal in the magnitude to the unit increment introduced by transformer 204a.

FIG. 6 shows a corrective network 275' replacing the network 275 of FIG. 5. In this modification, each line transformer 204a,...204n is energized from bus bars 208, 209 over a bridge circuit whose four arms include respective triacs 206a, 206a", 212a, 2120",...20611, 206n, 2l2n, 212m". These triacs are again selectively fired, one pair at a time,by associated trigger circuits 214a,...214n' responsive to the setting of corresponding stages of register 226.

It is to be understood that comparable features from different embodiments may be combined with or substituted for part of the circuitry of other embodiments; thus, for example, the voltage-drop compensator 61 of FIG. 3 could also be used in systems where the sensing transformer 16 etc. is connected, as in FIG. 1, on the output side of the corrective network (e.g., for the purpose of monitoring the voltage drop across a variable load separated from the output terminals of the stabilizer by other impedances). It will also be apparent that the invention, in its broader aspects, is applicable to systems including any conventional voltage-measuring means and that integration of the line voltage, as hereinabove described, may be carried out between recurrent points of a cycle other than the zero-transition points specifically disclosed.

I claim:

l. A system for stabilizing the output voltage of a transmission line connected across a source of alternating current, comprising:

sensing means connected to said line for determining any deviation of the line voltage from a predetermined level;

pulse-generating means controlled by said sensing means for producing, within each cycle of said line voltage, a train of stepping pulses varying in length with the magnitude of such deviation;

reversible counter means coupled to said pulse-generating means for stepping by said pulse train with a sense of counting determined by the sign of said deviation, said counter means having a plurality of stages selectively settable according to a binary code by the pulses of said train; I

a voltage generator having a sinusoidal output voltage synchronized with said line voltage;

transformer means connected across said voltage generator, said transformer means including a plurality of secondary windings inserted in said line with graded transformation ratios for impressing different voltage increments upon said line, said secondary windings being proportioned to introduce voltage increments bearing a binary relationship, said counter means being provided with switchover means for reversing said sense of counting upon arrival of said counter means in a zero position, said voltage generator being of reversible phase and being coupled to said switchover means for simultaneous reversal of said phase and said sense of counting;

and enabling means for said secondary windings responsive to the setting of respective stages of said counter means for introducing said voltage increments to compensate for said deviation.

2. A system as defined in claim 1 wherein said transformer means includes a plurality of primary windings individually coupled to said secondary windings, said enabling means comprising at least two semiconductive devices in circuit with each primary winding, and trigger means for alternately rendering said devices conductive.

3. A system as defined in claim 2 wherein said devices are triacs.

4. A system as defined in claim 2 wherein said devices are respectively connected in series and in parallel with the associated primary winding.

5. A system as defined in claim 2 wherein said counter means is provided with register means for storing the setting of said stages over at least a major part of a half-cycle of said line voltage, further comprising transfer means connected to said line for initiating the transmission of the contents of said registcr means to said trigger means at a predetermined point in each cycle of said line voltage.

6. A system for stabilizing the output voltage of a transmis sion line connected across a source of alternating current, comprising:

sensing means connected to said line for determining any deviation of the line voltage from a predetermined level;

pulse-generating means controlled by said sensing means for producing, within each cycle of said line voltage, a train of stepping pulses varying in length with the magnitude of such deviation;

reversible counter means coupled to said pulse-generating means for stepping by said pulse train with a sense of counting determined by the sign of said deviation, said counter means having a plurality of stages selectively settable according to a binary code by the pulses of said train;

a voltage generator having a sinusoidal output voltage synchronized with said line voltage;

transformer means connected across said voltage generator, said transformer means including a plurality of secondary windings inserted in said line with graded transformation ratios for impressing different voltage increments upon said line, said secondary windings being proportioned to introduce voltage increments bearing a binary relationship, the number of said stages being a multiple of the number of said secondary windings, said stages being divided into groups assigned to respective secondary windings;

and enabling means for said secondary windings responsive to the setting of respective stages of said counter means for introducing said voltage increments to compensate for said deviation, said enabling means including coding means responsive to individual stages of each group for multiplying said output voltage by difierent constants. 7. A system as defined in claim 6 wherein said counter means is provided with switchover means for reversing said sense of counting upon arrival of said counter means in a zero position, said voltage generator being of reversible phase and being coupled to said switchover means for simultaneous reversal of said phase and said sense of counting.

8. A system for stabilizing the output voltage of a transmission line connected across a source of alternating current, comprising:

sensing means connected to said line for determining any deviation of the line voltage from a predetermined level;

pulse-generating means controlled by said sensing means for producing, within each cycle of said line voltage, a train of stepping pulses varying in length with the magnitude of such deviation;

reversible counter means coupled to said pulse-generating means for stepping by said pulse train with a sense of counting determined by the sign of said deviation, said counter means having a plurality of stages selectively settable by the pulses of said train, said counter means being provided with register means for storing the setting of said stages over at least a major part of a half-cycle of said line voltage;

a voltage generator having a sinusoidal output voltage synchronized with said line voltage;

transformer means connected across said voltage generator,

said transformer means including a plurality of secondary windings inserted in said line with graded transformation ratios for impressing different voltage increments upon said line, said transformer means including a plurality of primary windings individually coupled to said secondary windings, said enabling means comprising at least two semiconductive devices in circuit with each primary winding;

enabling means for said secondary windings responsive to the setting of respective stages of said counter means for introducing said voltage increments to compensate for said deviation;

trigger means for alternately rendering said devices conductive;

and transfer means connected to said line for initiating the transmission of the contents of said register means to said trigger means at a predetermined point in each cycle of said line voltage.

9. A system as defined in claim 8, wherein said transfer means includes a zero-transition detector.

10. A system for stabilizing the output voltage of a transmission line connected across a source of alternating current, comprising:

sensing means connected to said line for determining any deviation of the line voltage from a predetermined level, said sensing means comprising a rectifier, a source of reference voltage, integrator means receiving both said reference voltage and the output of said rectifier, and threshold means connected to the output of said integrator means;

pulse-generating means controlled by said sensing means for producing, within each cycle of said line voltage, a train of stepping pulses varying in length with the magnitude of such deviation;

reversible counter means coupled to said pulse-generating means for stepping by said pulse train with a sense of for introducing said voltage increments to compensate for said deviation.

11. A system as defined in claim 10 wherein said stages are settable according to a binary code, said secondary windings being proportioned to introduce voltage increments bearing a binary relationship.

12. A system as defined in claim 10, further comprising a supplemental voltage generator working into said integrator means, said supplemental generator being coupled to said line for developing an output voltage proportional to line current.

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