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Publication numberUS3611296 A
Publication typeGrant
Publication dateOct 5, 1971
Filing dateDec 29, 1969
Priority dateDec 29, 1969
Also published asCA930447A1, DE2064299A1, DE2064299B2, DE2064299C3
Publication numberUS 3611296 A, US 3611296A, US-A-3611296, US3611296 A, US3611296A
InventorsJohnson William E
Original AssigneeOwens Illinois Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Driving circuitry for gas discharge panel
US 3611296 A
Abstract  available in
Images(1)
Previous page
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Claims  available in
Description  (OCR text may contain errors)

United States Patent 3,381,144 4/1968 Thomas William E. Johnson Toledo, Ohio 888,743

Dec. 29, 1969 Oct. 5, 1971 Owens-Illinols, Inc.

Inventor Appl. No. Filed Patented Assignee DRIVING CIRCUI'IRY FOR GAS DISCHARGE PANEL 4 Claims, 3 Drawing Figs.

US. Cl 340/166, 315/169 Int. Cl ..ll0lj 17/48, l-l05b 41/44, HOlj 61/33 Field of Search 340/166; 315/169, 84.6; 307/303, 239, 241, 215, 235, 254

References Cited UNITED STATES PATENTS ac-N RA ROW 0m REGISTER (8 ans) 3,493,812 3/1970 Weimer 3,499,167 3/1970 Bakeretal OTHER REFERENCES IBM Publication, Solid State Electroluminescent Display and Scanning Apparatus R. J. Lynch Vol. 9 No. 12 May,

l967,pp. 1799- 1801 G. E. Electronics Publication, Monolithic Anohybrid In- 3 tegrated Circuits" May, 1966 pp. 25- 37.

Primary ExaminerDonald .1. Yusko Attorneys-13.1. Holler and Donald K. Wedding ABSTRACT: Solid-state low level to high-level interfacing pulser circuits for multiple discharge gas discharge devices capable of feeding through a high-level periodic sustaining voltage to the discharge device with minimum degradation. The output is the algebraic sum of the periodic sustaining voltage and a level converted logic signal. Logic circuitry is included which may be fabricated with or included in packages containing interfacing pulser circuits. There is no mixing of active elements (NPN vs. PNP) so many circuits may be incorporated on a single wafer or chip. Consult the specification for features and details.

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PATENTED um. 5|97l 3.611.296

RA ROW DATA REGISTER 0m (8 BITS) NPUT 1L PNP PULSERRZOLUMNS) 41w E J2| COLUMN SET---l 1 H6 2 A COLUMNDATA rocowmu LINE Y NPN PULSER a GATHROWS) :'R2 I D3 D2 1: E Q Row SH 4; [I K I, TO ROW LINE "x" Row WA 56 INVENTOR 4 2 (VLR) 5V R WILLIAMYE, JOHNSON Y souRcE 15) BY 6. H K. NW4

ATTORNEYS BACKGROUND OF THE INVENTION In Baker et al. U.S. Pat. No. 3,499,167, filed Nov. 24, 1967, and entitled Gas Discharge Display-Memory Device and Method there is disclosed a multiple discharge display and/or memory panel which may be characterized as being of the pulsing discharge type having a gaseous medium, usually a mixture of two gases at a relatively high gas pressure, in a thin gas chamber or space between opposed dielectric charge storage members which are'backed by conductor arrays, the conductor arrays backingeach dielectric member being transversely oriented to define or locate a plurality of discrete discharge volumes or sites and constitute a discrete discharge unit. lnflsome cases, the discharge units may be additionally defined by physical structure such as perforated glass plates and the like and in other cases capillary tubes and like structures may be used. In the above-identified patentapplication of Baker et'al., physical barriers and isolation members for discrete discharge sites have been eliminated. 'In such devices charges (electronsand ions) produced upon ionization of the gas at a selected discharge site or conductor cross-point, when proper operating potentials are applied to selected conductors thereof, are stored upon the surfaces of the dielectric at the selected locations or sites and constitute an electrical field opposing the electrical field which created them. After a firing potential has been applied to initiate a discharge, the electrical field created by the charges stored upon the dielectric members aid in initiating subsequent momentary or pulsing discharges on succeeding half cycles of an applied sustaining potential so that the applied potential, and hence the stored charges indicate the previous discharge condition of a discharge unit or site and constitute an electrical memory. However, because the conductor arrays utilized in creating such discharges are isolated from the gas medium by the dielectric means and because of the relatively high gas pressures, the potentials required for operating'such panels are relatively high.

A significant improvement in operating voltage requirements has been achieved by utilization of an argon-neon gas mixture as disclosed in the application of James F. Nolan, Ser. No. 764,577 filed Oct. 2, 1968 and assigned to the assignee of the present invention. The gas. discharge panel disclosed in the Nolan patent application is filled with a gas mixture composed of about 99.9 atoms of neon and about 0.1 atoms of argon at an absolute pressure of 24.62 inches of mercury (hg). In a gas discharge panel constructed in accordance with the teachings of the Nolan application, a sinusoidal or periodic sustaining voltage is continually applied to all conductors of the panel at a measured frequency of about 50 kHz. to sustain discharges at selected discharge sites after they have been turned on at a higher voltage, a typical periodic sustaining voltage for the panel was in the range of 335 to 350 volts peak-to-peak. In dynamic operation, in addition to the sustaining voltages, a 2 microsecond pulse, superimposed and algebraically added to the sine wave applied to selected transverse conductor pairs in V the conductor arrays to manipulate discharge conditions of discharge sites. Such pulse voltages were applied by means of pulse transformers and like devices in the manner disclosed in Johnson et al. application Ser. No. 699,170, filed Jan. 19,

Integrated pulser circuits in accordance with my application Ser. No. 821,306 are in two forms: one form utilizes PNP-type semiconductor and .the second form utilizes NPN-type semiconductor, each form producing a high-voltage pulse output in response to a low-level logic signal input. For gas discharge panels of the type disclosed in the aforementioned Baker et al. patent application, both forms are necessary to drive the transversely related conductor arrays. The PNP-type semiconductor circuit is used to produce positive output pulses and the NPN-type semiconductor circuit produces negative output pulses. In a 4X4 inch display area, with conductor arrays having conductors on mil centers, there will be approximately 33 conductors or lines per inch resulting in 132 conductors per array or 264 lines to be driven requiring 264 pulser circuits. Functionally, the pulser circuits operate 5 lowlevel to high-level interfacing devices feeding through a highlevel periodic sustaining voltage with minimal degradation.

Objects of this invention include the provision of solid state logic circuits for supplying address signals to interfacing pulser circuits for gas discharge devices and reduce the necessary driving logic and overall cost of driving circuitry for gas discharge display/memory panels.

The above and other objects, advantages and features of the invention will become apparent from the following specification when considered with the accompanying drawings wherein:

FIG. 1 is a diagrammatic illustration of a gas display panel and electrical driving system incorporating the invention,

FIG. 2A is a circuit diagram illustrating an NPN .pulser and gate and FIG. 2B is a circuit diagram illustrating a PNP pulser and gate.

The invention will be described as it is employed in a system supplying operating potentials to gas discharge display/me mory device of the type described earlier herein. Such a device 10 is diagrammatically illustrated in FIG. 1 of the drawing as having a horizontal or row conductor array 11 and vertical or column conductor array 12. (Alternate conductors in an array may brought out at the opposite sides, respectively, of the panel to facilitate making electrical connections thereto. For simplicity of illustration, the row and column conductors are shown as being served from one side of the panel 10). Normally, oppositely phased periodic potentials l3 and 14 are applied to conductor arrays 11 and 12, respectively, so that approximately half the potential necessary to manipulate a discharge unit in a manner described later herein is applied per conductor. Thus, if the periodic potential across the gas in the discharge panel necessary to operate the device is 350 volts peak-to-peak, then one-half this voltage is applied to the conductors of conductor array 11 and the other half (oppositely phased) is applied to conductors in conductor array 12 and such potentials. are delivered from periodic voltage generator portions 15 and 16, respectively, (which may be of the type disclosed in Murley application Ser. No. 755,930 filed Aug. 28, 1968) having a common ground 17 so that panel 10 floats with respect to ground '17. It may be noted at this point, and as will be shown more fully hereinafter, sustaining potentials 13 and 14 pass through interfacing circuitry 20-1 20-N and 21-1 21-N with minimum degradation. As shown, sustaining potentials for all row conductors 11-1, 11-2 ll-N of conductor array 11, are supplied from sustaining generator portion 15 and all vertical or column conductors l2-1, 12-2 12-N in conductor array 12 are supplied from sustaining voltage generator portion 16; and these potentials are continually applied to the conductor arrays on panel 10 during normal operation thereof. Individual discharge sites located by the crossing of selected conductors of conductor arrays 11 and 12 are manipulated by adding high-voltage unidirectional voltage pulses to the sustaining voltages on selected conductors of arrays 11 and I2, respectively, which, when combined, are sufiicicnt to initiate a sequence of discharges, one for each half cycle of applied sustaining potential at any selected discharge site and by properly timing such pulses the sequence of discharges may be terminated so hat any individual discharge site may be manipulated, ON" and OFF, by manipulation of the times of occurrences of the unidirectional voltage pulses.

As noted above in a 4by4 inch display area on a panel, with 30 mil spacing between conductors there may be 132 row conductors and 132 column conductors, each conductor of which, while having a common sustaining voltage applied thereto, must have the manipulating voltage pulses applied at selected times in accordance with the information to be displayed andlor stored upon the panel. Such large numbers of driving circuits per panel requires that the size and cost thereof be reduced as much as possible, and, at the same time, maintain the uniformity of potentials supplied to the conductors of the respective arrays. While such panels as the present invention is concerned with have been driven by pulse transformers and the like devices fairly successfully, it is desirable that use of large numbers of pulse transformers in commercial applications of such panels be eliminated.

In accordance with the present invention, each of the circuits and 21 is formed as a circuit on an integrated circuit wafer or chip and while all similar or like circuits may be formed on a single wafer or chip (indicated by the dashed lines in FIG. 1), commercially, at the present time for yield purposes it is only feasible to place four such circuits on a single chip or wafer. Further, transistors used in the row conductor circuits 20-l 20-N are of the NPN type to produce a negative output pulse whereas transistors in the circuits 21-1 2l-N are PNP-type to produce a positive output pulse. As explained more fully hereinafter, obviously, NPN types may be used to drive column conductors and PNP types each be used to drive row conductors. At selected times, each of circuits 20-1 20-N and 21-1 ...21-N receive a low-level logic pulse from row logic circuits 40-1, 40-2 40-N and column logic circuits 41-1, 41-2 41-N, respectively which receive row data inputs from row data bus 42 and column data inputs from column data bus 43. Data on row bus 42 and column bus 43 are received on registers 44 and 46 from a computer or other digital data input device for display and/or storage on the panel.

In the illustrated configuration, the data input lines are paralleled to gates of all pulser packages whereas a separate section input line (RA, RB RN for row conductors and CA, CB CN for column conductors) goes to all pulsers within a package. Each package can be considered as a section address to eight panel lines, two chips of four pulsers and gates per package (it being understood eight lines is not restrictive but just an example and that more or less gates and pulsers may be incorporated per chip). FIG. 1 indicates how a combination of sections are combined to drive a panel. As an example of logic, savings consider a 1,000 line panel. If single input pulsers were used and driven from a binary tree logic circuit it would require approximately 2,000 AND" gates to form the binary tree. In the disclosed configuration with eight lines to a section, there would be 125 sections requiring a binary tree composed of 250 AND" gates. The addition of data registers 44 and 46 as shown would only add approximately 50 AND" gates for a total of 300 AND gates compared to the previous 2,000 AND" gates. The additional input logic to control the flow of data is greatly reduced. In this configuration any section can be arbitrary addressed in the section address register while data for that section is put in the data register. On a strobe signal for timing purposes all eight lines in a section receive data inputs. Repeating this operation six times with new data each time and stepping the vertical address on position each time results in a 6X8 section address such as writing an alphanumeric character. In this way a point at a time or a complete section (for instance in erasing a section of the horizontal and vertical data registers are filled with ones and an erase strobe is put on both horizontal and vertical binary trees a complete section) is erased in one operation.

As illustrated, logic circuits 40 supply row conductor interface circuits 20-1 with a positive logic pulse signal whereas the logic circuits 41 supply a negative logic pulse signal to column interface circuits 21 and in the normal operation, such positive and negative logic pulses are applied simultaneously to selected conductors to selectively initiate discharges and to terminate discharges at selected discharge sites within the panel 10.

LOGIC AND INTERFACING CIRCUITS FIG. 2A shows one of a plurality of logic 40 and interfacing pulser circuit 20 for driving individual row conductors 11-1 lI-N, respectively, of array 11 and FIG. 2B shows one of a plurality of logic 41 interfacing circuits 21 for driving column conductors 12A 123 respectively in array 12. It will be noted that the circuit configuration shown in FIG. 2A includes NPN-type transistors and the circuit configuration in FIG. 28 includes PNP-type transistors; the difference between the circuits being for purposes of supplying opposite polarity and phase signals for driving associated conductors in the arrays.

The circuit configuration of FIG. 2A will be described in detail, it being understood that except for reversal of direct current supply potentials and the conductivity type of the transistors involved, the operations are the same for circuit configuration of FIG. 2B. A low-impedance, high-voltage level direct-current source 50 (FIG. 1) supplies a operating voltage to the pulser circuit 20 per se, and a similar, opposite polarity source supplies operating potential to the column pulser circuits 21. Interface pulser circuit 20 includes a first NPN transistor Q1 having its emitter E connected to a terminal 54 of the high-voltage source 5 QR. Collector C of transistor O1 is connected through a collector resistor R3 to terminal 53. Resistor R3 is about 15,000 ohm, and is a compromise of rise time and power dissipation for bias current from the direct current coupled to transistor Q1 and transistor Q2. The base of transistor O1 is connected to logic signal input terminal 56 on which is applied a low-level positive logic signal pulse 57 from logic circuit 40. Resistor R2 is connected between the base B of transistor Q1 and tenninal 54 and is used with resistor R1 to match interface circuit 20 to the logic circuit 40. Resistors R1 and R2 may be eliminated if the interface circuit 20 is matched to the logic circuit 40.

A second NPN transistor Q2 has its base B connected directly to collector C of transistor Q1 and its collector C connected directly to terminal 53. Emitter E of transister Q2 is connected directly to output terminal 60 which is connected directly to a conductor in row conductor array 11. The collector C of transistor O1 is connected through sensing diode D1 to the output terminal 60; diode D1 sensing the direction of current flow and aids in turning transistor Q2 ON and OFF as described more fully hereinafter.

Sustaining voltage generator portion 15 has its output terminal connected directly to input terminal 53 and to terminal 51 (FIG. 1) of the low-impedance high-voltage level directcurrent voltage source 50R, so the periodic sustaining voltage appears at both the collector C of transistor Q2 and the emitter E of transistor 01 in the latter case via the low-impedance source 50. The low impedance may be constituted by the filter capacitor means (not shown) at the output of power supply 50R.

Logic circuit 40 is a conventional two input AND gate constituted by diodes D; and D Resistor R and source of logic potential VLR, diode D serving couple the output of the circuit to the base B of transistor Q1, thus the coincidence of an input row section signal to the cathode of diode D, and a row data signal on the cathode of diode D (e.g. both higher than the potential on the anodes thereof) will enable (e.g. a high output) the gate since all the diodes will conduct.

OPERATION OF SYSTEM Normally, transistor 02 is conducting and transistor O1 is nonconducting so that the periodic voltage (approximately volts peak-to-peak) from sustaining voltage generator portion 15 is applied through collector C of transistor Q2. On negative half cycles of the sustaining voltage current flows through collector C, base B of transistor Q2 and diode D1 to terminal 60 whereas on positive half-cycles of sustaining voltage current fiows through the collector-emitter circuit of transistor Q2 to the output terminal 60 so that there appears on output terminal 60 a periodic voltage corresponding to the waveform of the voltage from sustaining voltage generator portion 15. This sustaining voltage appears on all row conductors of conductor array 11 via the interfacing circuits 20 corresponding to the row conductor. In a similar fashion, the oppositely phased sustaining voltage from generator portion 16 appears on the column conductors of conductor array 12 via interfacing circuits 21.

Whenever one or more selective gate circuits 40 (for the row conductors) and one or more gate circuits 41 (for the column conductors) are enabled, e.g. have applied in coincidence row section and row data pulses, a trigger voltage pulse applied to logic input terminal 56, and base B of transistor 01 causes transistor O1 to rapidly be made conductive or turned ON so that the collector C thereof, which prior to switching of transistor Q1 had been at essentially zero direct-current potential, rapidly falls (relatively) to the potential (-l75 volts) of the high-voltage level direct-current source 50 for the time period that transistor O1 is in a switched or 0N state. When O1 is turned on, O2 is biased off by current thru R3. This high direct-current voltage is passed through diode D1 to output terminal 60 to constitute one component of the output voltage during the time interval when the transistor 01 is in its switched state. As noted earlier, the periodic sustaining voltage from generator portion 15 passes through the low-impedance high-voltage level directcurrent voltage source 50 and also appears at the emitter E of transistor Q1 so that when transistor Q1 is switched ON, for the period of time that transistor 01 is switched ON, this voltage is likewise passed through to collector C of transistor 01 and thus, through diode D1 to appears as a second component of the output voltage appearing on output terminals 60. Thus the high direct-current potential and the sustaining voltage are algebraically added to constituted a pulse voltage for manipulating the discharge condition of a selected discharge site. In a similar fashion, a negative column section and column data signals applied to one or more logic circuits 41 connected to a column conductor high-voltage pulser 21 of conductor array 2 is translated to a high-level discharge-manipulating pulse on the selected column conductor. By properly timing the occurrence of logic pulse 57, the high-voltage direct-current pulse produced as a result of the switching action of transistor O1 is algebraically added to a negative going half-cycle of the sustaining voltage to constitute a firing voltage pulse applied to a selected discharge site simultaneously with the application of a similar pulse to a selected column conductor to thereby initiate a sequence of discharges in a selected gas volume or discharge site and thereafter, the sustaining voltage augmented by the potential due to stored charges, will sustain such sequence of discharges as described earlier. When it is desired to terminate a discharge, logic pulse at terminal 56 may be timed to occur at that part of the sustaining signal such that a controlled discharge of the addressed site is initiated resulting in extinction of the discharge process (e.g., terminating the sequence of discharges) on succeeding sustaining signal cycles, as more fully explained in Johnson et al. application Ser. No. 699,170, filed Jan. 19, 1968.

Although most forms of integrated circuit fabrication may be used to structure the circuit, the dielectric isolation technique is preferred since at the present state of the art, this technique appears to provide the necessary isolation tor the relatively high voltages which presently available gas discharge panels require. In some cases, it may be necessary to provide one or more stages of amplification between the logic circuit 40, 41 and the high-voltage pulses circuits and 21. Such states of amplification may be incorporated within the same chip as the logic circuit and the high-voltage pulser circuits.

The circuit affords a reduction in size, cost and power consumption and enables the output pulses to be equal to the DC power supply voltage which is common to all circuits of the same type to assure constancy and uniformity of voltage pulses. The two circuits (NPN and PNP) operate from two different floating high direct-current voltage sources 50 and, when used with the sustaining generator portions 15 and 16, (HO. 2), are connected to the outputs thereof at contact areas or terminals 53 and 54. Logic voltage pulse inputs to the circuits consist of low-level logic signals, referenced to the highlevel direct-current sources 50 (+V and V, respectively), so the logic circuitry essentially will also float on the sustaining generator and the outputs are voltage pulses equal in amplitude to the voltage from sources 50 algebraically added to the sustaining voltage. By properly timing the times of occurrence of the low-level logic pulse inputs, selected discharge sites may be turned "ON" or tired as by the voltages at the selected site.

Parasitic capacitance between the sustaining signal input line and each panel line aids in reducing the overall impedance of integrated circuit pulsers and is a natural result of the printed circuit line routing. By special routing the capacitance can be maximized for best results.

The number of horizontal (row) and vertical (column) conductors in the sections need not necessarily be the same number of lines but are set for a particular panel operation such as arbitrarily dividing the panel into 10 line by 10 line sections or six line by eight line sections, etc.

The primary purpose of this invention is to reduce the necessary driving logic and therefore the overall cost of driving circuitry to a panel. lf metal-oxide-silicon- (mos) type pulser circuits are used instead of the present bipolar circuits it would be desirable to optimize the parasitic capacitance due to the higher mos impedance levels by utilizing the line capacitance between the sustaining signal and panel lines through maximum area overlapping the printed circuit board mounting the integrated circuits.

It will be appreciated that the logic circuits 40 may be formed as separate integrated circuit components (as by large scale integration techniques) and connected to the interface circuits by circuitry on printed circuit boards and the like.

What is claimed is:

1. In a system for driving a multiple discharge gas discharge device wherein a pair of transversely oriented conductor arrays are dielectrically isolated from a thin gas discharge medium between said pair of conductor arrays comprising, a first monolithic semiconductor body processed to provide a plurality of resistive and PNP transistor circuit components connected by conductors to form a plurality of identical circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made, a second monolithic semiconductor body processed to provide a plurality of resistive and NPN transistor circuit components connected by conductors to form a plurality of identical circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made,

each said circuit configuration including a pair of like conductivity-type transistors switches connected such that one of said transistor switches is normally ON and the other of said transistor switches is normally OFF, a lowlevel pulse voltage input terminal connected to the base of said normally OFF transistor to render said normally OFF transistor ON and said normally ON transistor OFF on appearance of a low-level pulse voltage at said lowlevel pulse voltage input terminal, a pair of said contact areas for applying a high-level periodic voltage to the collector of said normally ON transistor and to the emitter of said normally OFF transistor, and a high-level unidirectional voltage to the emitter of said normally OFF transistor, and a final contact area constituting the the output terminal from said circuit configuration, means individually connecting each final contact are of circuit configurations having PNP transistor components to conductors in a first of said conductor arrays, respectively,

means individually connecting each final contact area of circuit configurations having NPN transistor components to conductors in the second of said conductor arrays, respectively, a first source of high-level periodic voltage and means commonly connecting said first source of high-level periodic voltage to all of said pairs of contact areas on said first monolithic semiconductor body, a second source of high-level periodic opposite in phase to said first source of voltage high-level periodic voltage and means commonly connecting said second source of highlevel periodic voltage to all of said pairs of contact areas on said second monolithic body, a first source of highlevel unidirectional voltage, means connecting said first source of high-level unidirectional voltage to all of said pairs of contact areas on said first monolithic body, and a second source of high-level unidirectional voltage, and means for connecting said second source of high-level unidirectional voltage to all of said pairs of contact areas on said second monolithic body, the improvements comprising,

each said circuit configuration including a multiple input AND gate with the output of said gate connected to said low-level pulse voltage input terminal whereby the conduction condition of said transistors is controlled in accordance with the logical sum of input voltages to said gate.

2. The invention defined in claim 1 wherein said gate is a two input gate and one of the inputs to said gate circuit is common to a selected number thereof, a register for storing input data constituting the information to be entered to said gas discharge device at the conductors connected to said selected number of gate circuits.

3. In an electrical system for supplying sustaining voltages and discharge manipulating pulse voltages to one conductor in a gas discharge device in which transversely oriented conductors effecting discharges in the gas have dielectric charge storage means for storing charges produced on a discharge interposed between said conductors and the gas, a monolithic semiconductor body processed to include a plurality of resistive and transistor circuit components connected by conductors in the circuit configuration as described hereinafter including a plurality of terminals through which connections to said circuit configuration are made, said circuit configuration including a pair of transistor switches connected such that one of said transistor switches is nonnally ON and the other of said transistor switches is normally OFF and to reverse the conductive states of said transistor switches, a pair of said terminals for applying a high-level periodic voltage to the collector of said normally OFF transistor, respectively, and a highlevel unidirectional voltage to the emitters of said normally OFF transistor, and a final contact area constituting the output terminal from said integrated circuit, said final contact area being connected to said one conductor, the improvement comprising,

said circuit configuration including an AND gate having at least a pair of signal input terminals and an output terminal connected to the base of said normally OFF transister to render said normally OFF transistor ON and said normally ON transistor OFF on the simultaneous appearance of signals on said pair of signal input terminals, and

wherein said AND gate is a two input gate and one of the inputs is connected in parallel with a selected number of other AND gate input terminals,

a register for storing input data for said selected number of gate circuits, and means connecting the output of said register to the other input terminals of said selected number of gate circuits, respectively.

4. An electrical circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge device in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge storage means, for charges produced on discharge interposed between said row and column conductors and t e gas, including at least a pair of monolithic semiconductor bodies, each processed to include a plurality of individual electrically isolated transistor switching circuits connected by conductors in circuit configurations described hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration including means for translating a low level input pulse signal voltage to a high-level pulse signal voltage and feeding through a high-level periodic signal voltage as said sustaining voltage, the output voltages from each said means for translating being of opposite polarity, respectively, the improvements comprising,

each said circuit configuration further including a two input gate circuit for controlling the application of said lowlevel input pulse voltage to said means for translating and wherein one of said inputs is constituted by said low-level input pulse voltage, register means for storing input data constituting the information to be entered to said gas discharge device, means connecting the output of said register to groups of said gate circuits as one input said gate circuit, and means for applying as the second input to said gate circuits selection pulses.

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Non-Patent Citations
Reference
1 *G. E. Electronics Publication, Monolithic Anohybrid Integrated Circuits May, 1966 pp. 25 37.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3673431 *May 28, 1971Jun 27, 1972Owens Illinois IncLow voltage pulser circuit for driving row-column conductor arrays of a gas discharge display capable of being made in integrated circuit form
US3706892 *May 28, 1971Dec 19, 1972Owens Illinois IncHigh voltage pulser circuit for driving row-column conductor arrays of a gas discharge display capable of being made in integrated circuit form
US3793628 *Sep 1, 1972Feb 19, 1974NcrElectroluminescent display device
US3793629 *Jan 5, 1973Feb 19, 1974Philips CorpElectrical display devices
US3803585 *Mar 7, 1973Apr 9, 1974Fujitsu LtdPlasma display panel driving system
US3839713 *Dec 29, 1972Oct 1, 1974Fujitsu LtdDisplay system for plasma display panels
US4001636 *Oct 15, 1974Jan 4, 1977Mitsubishi Denki Kabushiki KaishaAc drive discharge type display apparatus
US4570159 *Aug 9, 1982Feb 11, 1986International Business Machines Corporation"Selstain" integrated circuitry
DE2537527A1 *Aug 22, 1975Mar 4, 1976Nippon Electric CoSchaltungsanordnung zur umschaltung von spannungen
DE2725985A1 *Jun 8, 1977Jan 5, 1978Owens Illinois IncSteuer- und adressierschaltung fuer anzeigende/speichernde gasentladungstafeln
WO2003027996A1 *Apr 4, 2002Apr 3, 2003Steven KimMethod of driving capillary discharge plasma display panel for improving power efficiency
Classifications
U.S. Classification345/60, 315/169.4, 348/E03.14, 345/204
International ClassificationH04N3/10, H04N5/66, G09G3/28, H04N3/12, G09G3/288
Cooperative ClassificationH04N3/125, G09G3/296, G09G3/297
European ClassificationG09G3/296, G09G3/297, H04N3/12G
Legal Events
DateCodeEventDescription
Jun 9, 1987ASAssignment
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC., SEAGATE,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648
Effective date: 19870323
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC.,OHIO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648