US 3612041 A
Description (OCR text may contain errors)
United States Patent  Inventor Charles W. Ragsdale Primary Examiner-William E. Kamm Takoma Park, Md. Attorneys Harry M. Saragovitz, Edward J. Kelly, Herbert  Appl. No. 844,996 Berl and J. D. Edgerton  Filed July 25, 1969  Patented Oct. 12, 1971  Assignee The United St te f Am i 35 ABSTRACT: An electronic sensing scheme for the automatic represented by the Secreta of th A detection and indication of ventricular fibrillation from the 'j HQ I "in" myocardial waveforms of a human heart. The circuitry is an A," j M M improvement upon and is specifically designed to be incorporated into a li htwei ht, batter erated heart monitor of a [541 APPARATUS FOR DETECTING VENTRICULAR g g y P F 'fi I prior United States application cited herein. The additional 1 f iijflf g Figs circuitry provides increased reliability and sensitivityto the 2 S I heart monitor for distinguishing ventricular fibrillation  U. C l28/2.06 A waveforms f closely related waveforms that f l gave [5 1 Cl 5/04 false indications of ventricular fibrillation. The latter group of Field of Search 128/206 A, waveforms include those that exhibited pulse rates fl than F, R 150 pulses per minute and/or were unipolar in nature while at  References Cited the same time had large duty cycles. A preferred embodiment of the new circuitry requires that at least two positive-going UNITED STATES PATENTS and two negative-going signals, exceeding +4.0-volt and 4.0- 3,138,151 6/1964 Chapman et a1 128/206 A volt levels, respectively, and occurring at a 200 to 500 beats- 3,144,019 8/1964 Haber 128/206 A per-minute rate, must be produced at least every 8 seconds in 3,352,300 1 1/1967 Rose 128/206 A order for fibrillation to be indicated by the monitor.
r 4I Za w J; cumees LOWERS DUTY CYCLE SCHMlTT TlZlP l OlMT 39 WHEN FtBRlLLbMON 1S morcaneo lgafimgs 38 C: SESIQOSN SUTY CYCLE ,46 (36 1 ,64 \5 SENSED W EASURlNC: HARM DELkY W FlBlZlLLNl'mN cwzcun OUW ClfZCUlT I FlLTElZ SENSlNG ScHMlrr F j comrzot VOLTS i is T m r IFULLWAVEI 4 MC I ElZlZATlClTY rzssers mum new CKT. 'li \F 5mm NOT Ermmc .1 SlNG x DlSkBLES oQwER METE Aec \nmcmo rz DUMP 3 it; r 1 glimmer term 31 Tb maven Msigu mue 50 V UlZCUlT I47. $CHM1TT 13 9'1. ll'l DIGITAL one m g DISABLES l-ll-LOW 351130125 835;; FuIEIt sum F on). 5st WHEN 53-1 ENkBLED BE [2 V n4 ENABLES ss-1 PE (mm m 7 WHEN SS-l (NE 144 STANDSllLL ENABLED CKT-t ss-l r N am m 17.0 gns m g TONE A 0 o. BEE-PER one 3 b c o 1? Br B1 Mm ensue 012 ems n5 u gygg GENEYZMQR \\34 J J corner 10 l L a aga? 'L$EC. on METER mmcnoz APPARATUS FOR DETECTING VENTRICULAR FIBRILLATION RIGHTS OF GOVERNMENT BACKGROUND OF THE INVENTION This invention relates to improvements in an electronic device for monitoring a human heart and more particularly to a sensing device for the automatic detection and indication of a cardiac state known as ventricular fibrillation. More particularly, the device of the present invention senses a patients ECG. (electrocardiogram) and and gives an alarm if ventricular fibrillation occurs. It also has the important feature of being able to distinguish ventricular fibrillation from other ECG. waveforms to a more accurate degree than heretofore possible.
The instant invention is an improvement upon the ventricular-fibrillation-sensing scheme of the heart monitor disclosed in US. application Ser. No. 789,694, filed Jan. 8, 1969 by Charles W. Ragsdale and possesses all of the advantages of that scheme, as well as other and additional advantages apparent from the disclosures hereinafter. Embodiments of the present invention may readily be constructed to be easily incorporated into the aforementioned heart monitor, that device being portable, battery powered and well adaptable to field use and other situations in which oscilloscopes and paper recorders are not available or their use is not feasible.
Ventricular fibrillation is a cardiac state in which the heart is not pumping adequately to maintain life though a myocardial signal is being produced. The patient is in a state of cardiac arrest, and death is imminent. Hence, proper resuscitative measures must be quickly begun.
Ventricular fibrillation is characterized by an electrocardiograph waveform that is somewhat sinusoidal but very erratic. However, other nonarrest waveforms produced when the heart may be contracting adequately to maintain life may be very similar to those of fibrillation. The basic signal-recognition problem is distinguishing ventricular fibrillation from the other ECG. waveforms.
The applicant is not aware of any sensing scheme incorporated in a heart monitor, other than that disclosed in his aforementioned application, that provides automatic indication when ventricular fibrillation is present.
The sensing scheme disclosed as a part of the heart monitor in the aforementioned application provides a four-parameter system for the automatic detection and indication of ventricular fibrillation. In that system, certain nonfibrillation ECG. waveforms caused the monitor to give false indications of fibrillation. The nature of these bizarre waveforms, and of other possible waveforms that might contribute to false readings, will be more fully described below.
The device of the present invention eliminates false indications of fibrillation by incorporating a fifth parameter into the fibrillation detection scheme, thus placing additional requirements that the ECG. signal being monitored must meet before it can be indicated as ventricular fibrillation. Another important feature of the present invention is that it provides considerable leeway between fibrillation conditions and very bizarre nonarrest conditions previously recorded on tape. This new improvement in the fibrillation-sensing scheme is an important part of the previously disclosed heart monitor in that it is necessary to indicate if fibrillation is present with as high a degree of accuracy as possible.
It is therefore an object of the present invention to provide an improved electronic monitor for sensing the electrocardiogram of a human heart.
Another object of the present invention is to provide within a heart monitor an improved electronic sensing scheme to indicate the presence of ventricular fibrillation with a high degree of reliability.
It is an additional object of the present invention to provide a heart monitor more sensitive circuitry for differentiating between waveforms produced by ventricular fibrillation and closely similar waveforms that bear a close relationship to ventricular fibrillation waveforms.
Still another object of this invention is to provide a fibrillation detection scheme easily incorporated in, and highly compatible with, an existing heart monitor.
SUMMARY OF THE INVENTION Briefly, in accordance with this invention, an improved electronic sensing scheme is provided to afford accurate and reliable automatic detection and indication of ventricular fibrillation. The improvement is manifested in the form of a fifth parameter detection circuit which when incorporated with the other four parameters of the system acts to make the overall detection scheme considerably more selective and sensitive with regard to those ECG. waveforms that can be sensed as ventricular fibrillation. The fifth parameter circuitry requires that the ECG. waveform be characterized by at least two pulses each in the positive and negative polarities exceeding a predetermined amplitude and occuring within a predetermined time interval and by a pulse rate of 200 to 500 pulses per minute. Increased reliability and consistency of ventricular fibrillation detection is achieved without and modification to the existing circuitry other than the attachment to the aforementioned fifth parameter.
BRIEF DESCRIPTION OF THE DRAWINGS The specific nature of the invention as well as other objects, aspects, uses, advantages thereof will clearly appear from the following description and from the accompanying drawings, in which:
FIG. 1 is an overall block diagram of an electronic heart monitor which includes an improved ventricular-fibrillationsensing scheme in accordance with the present invention;
FIG. 2 is a waveform diagram showing the operation of the digital filter forming a part of the monitor;
FIG. 3 is a diagram illustrating the operation of the filter under noise conditions;
FIG. 4 is a diagram showing a filtered nonarrest electrocardiogram;
FIG. 5 is a diagram showing a typical electrocardiogram for ventricular fibrillation;
FIG. 6 is a diagram showing an electrocardiogram of a child which gave a false ventricular fibrillation indication;
FIG. 7 is a diagram showing an electrocardiogram accompanied by large baseline shifts;
FIG. 8 is a diagram showing an electrocardiogram illustrating a run of ventricular tachycardia;
FIG. 9 is a diagram showing an electrocardiogram judged a borderline case by the prior sensing scheme;
FIG. 10 is a block diagram of the fibrillation filter;
FIG. I I is a block diagram of the T-Schmitt trigger;
FIG. 12 is a block diagram of the duty-cycle-measuring circuit;
FIG. 13 is a block diagram of a duty-cycle-sensing Schmitt trigger;
FIG. I4 is a block diagram of the alarm delay circuit;
FIG. I5 is a block diagram of the erraticity circuit;
FIG. 16 is a block diagram of the fifth parameter circuitry;
FIG. 17 is a block diagram of the positive and negative Schmitt triggers of FIG. 16;
FIG. 18 is a block diagram of the I20-millisecond timers of FIG. 16;
FIG. 19 is a block diagram of the l-millisecond timers of FIG, 16;
FIG. 20 is a block diagram of the AND gates of FIG. 16;
FIG. 21 is a block diagram of the 8-second timers of FIG. 16; and
FIG. 22 is a block diagram of the output AND gate of FIG. 16.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the drawings, the improved ventricularfibrillationsensing scheme of the present invention is generally indicated within the dotted lines at 110 in FIG. 11. The portion of the block diagram of FIG. 1 that lies outside the dotted lines, indicated generally at lll, comprises the remaining circuitry of the heart monitor to which the fibrillation-sensing scheme is connected. That portion of the monitor indicated at 11 is a duplicate of that disclosed in aforesaid U.S. application Ser. No. 789,694 filed Jan. 8, 1969 by the present applicant. A brief description of that portion is included herein for completeness in disclosure.
FIG. 1, an input to the monitor is derived from three conventional electrocardiogram electrodes and applied to the monitor input terminals 12, M, and 16, one of which may be connected to a ground as indicated in the drawing. The input terminals 12 and M are applied to a battery-electrode test circuit H8. The test circuit feeds a signal by way of lead 20 to a meter indicator 22, which senses the voltage across the elec trode pair. If the electrodes are unplugged, the meter reading corresponds to the battery voltage.
The ECG. signal, acquired by electrodes attached to the patient in any one of many possible conventional configurations, is routed through the test circuit 18 to a preamplifier 2d. Preamplifier 24 provides a voltage gain form 1,000 to 50,000 adjustable by a control voltage to a field effect transistor. it also provides band-pass filtering with one-half power points at 3.6 Hz. and 76 Hz. and approximately 60 db./decade rolloff above and below those points. It has a differential input with greater than 10,000 common mode rejection ratio and an input impedance greater than 50,000 ohms. Input projection is provided for each input of:t3,000 volts as protection against a defibrillator pulse. The output impedance of the preamplifier is 24,000 ohms.
The preamplifier 24 passes the important frequencies of the ECG. (ORS complex, fibrillation) while offering some rejection of high-frequency noise (muscle potentials at I Hz. or greater, 120 Hz. etc.) and low-frequency ECG. components (DC electrode voltage, S-T segment shifts, etc.). The differential input rejects much of the in-phase signals (such as 60 Hz. generated external to the body) and provides a high enough input impedance for use with most electrodes.
The output of the preamplifier 24- is applied to a fullwavc rectifier 26 so that the circuitry following the rectifier output will not be affected by monitor signal polarity changes.
From rectifier 26 the signal is applied to an automatic gain control circuit 28 which feeds back a gain control signal by way of lead 30 to preamplifier 24. AGC circuit 28 initially applies a control voltage to the preamplifier 24 that gives a maximum preamplifier gain. When the rectifier 26 output is greater than the AGC control point (6.0 volts), the AGC output voltage linearly decreases with time, to decrease preamp gain, until the rectifier output is below the 6.0-volt level. The maximum gain decrease time is 0.5 second. The AGC output voltage then linearly increases with time (increasing preamp gain) until the rectifier output is above the 6.0-volt level again. The maximum gain increase time is seconds.
The AGC 28 output acts with the rectifier 26 to keep the peak preamp signal amplitude at 6.0 volts. Because of the capacitive coupling of the full-wave rectifier, the AGC and the rectifier act to DC shift the signal and effect its amplitude, giving equal positive and negative peaks at the preamp outlet, after equilibrium is reached. Because of the slow reaction time of the AGC, only long-term amplitude changes are completely adjusted for.
Preamplifier 24 feeds a signal to an AGC dump 32 having its output coupled by way ofline 341 to AGC circuit 28. The AGC dump circuit senses the ECG. (before AGC control) in the preamplifier 2 8 and resets the AGC to give preamp maximum gain 2 seconds after a preamp input signal of more than 5 mil livolt peak (either polarity) is removed. The latter condition would exist during defibrillation, during cauterization (as in the operating room) or because of 60 Hz. pickup due to an open ECG. lead (or leads).
The output of rectifier 26 is supplied by lead 72 to a 5.0-volt Schmitt 74 and a 3.0 -volt Schmitt 76. These, in turn, feed the two inputs of a digital filter 78. The digital filter is actually a pulsewidth discriminator and performs the following three functions.
First, the digital filter does not provide an output if the 5.0- volt Schmitt output is zero or the 3.0-volt Schmitt output pulse width is less than 10 milliseconds. if either of the latter condi tions are met, the circuit is also reset. The latter conditions are met with excess muscle potentials, 60 Hz. and 120 Hz.
Secondly, the digital filter does provide an output if there is a 5.0-volt Schmitt output along with a l0 to 30 millisecond 3.0-volt Schmitt pulse width. lf these conditions exist, for 400 milliseconds (refractory period) after the l0-30 millisecond pulse, 3.0-volt Schmitt pulses greater than 30 milliseconds are rejected.
Thirdly, digital filter 78 provides an output if there is a 5.0- volt Schmitt output along with a greater-than-30-millisecond 3.0-volt Schmitt pulse width. No refractory period then exists.
The first condition or case 1 above applies when either pure 60 Hz., or 120 Hz. is received (as with an open lead) or when excessive noise is riding on the ECG. (such as 60 Hz., 120 Hz., and muscle potentials). These noise artifacts have widths less than 10 milliseconds, while ECG. signals have wider widths.
Condition or case 2 above applies and is useful when a narrow-width QRS complex accompanied with a large-amplitude, long-latency T-wave occurs. Such a waveform is illustrated at 80 in FIG. 2. The ORS complex is indicated at 82 and the long-latency T wave at 84. The refractory period or 400 millisecond period is indicated at 86. in waveform 80 the T-wavc 84 is rejected by the digital filter 78.
Condition or case 3 above applies when most other QRS complex are received. in both cases 2 and 3 a considerable amount of noise is tolerated riding upon the signal. FIG. 3 shows a full-wave-rectified ECG. at 88 with noise superimposed on it as indicated at 90.
In the signal shown in FIG. 3 the noise spikes 90 are rejected when case or condition 1 above is met. Noise riding on the signal itself still allows the meeting of condition 2 or 3 with the proper pulse width. Only when the signal is so completely obscured by noise that the ECG. signal peak is driven too far below the 3.0-volt Schmitt threshold does a zero digital filter output exist.
Again referring to FIG. ll, digital filter 78 feeds a one shot 92. That is, the digital filter triggers the one shot which emits constant width pulses. in addition, during the one-shot pulse, additional filter outputs will have no effect. Hence, signals (such as the typical T-wave) that are not rejected by the filter are blanked out by the one shot. The one-shot width is the maximum to still allow a 225 heats-per-minute maximum rate. The output from one shot triggers an erraticity circuit 68; a driver 94 and a beeper gate 96. if a disable signal is not present from the alarm delay circuit 64 more fully described below, the one-shot pulse is applied to a rate-measuring circuit 98. During fibrillation, no pulses are applied to the rate-measuring circuit 98 so that the pointer on the cardiotachometer 100 connected to the output of ratemeasuring circuit 98 falls toward zero. The output of the rate-measuring circuit is a DC level linearly dependent upon the rate of occurrence of the one-shot pulse. The cardiotachometer 100 indicates the rate, and the rate signal is applied to a high-rate sensor 102 and a low-rate sensor H04. The high-rate sensor and the low-rate sensor outputs change state when their input voltage falls above or below the threshold set by the high-rate limit 106 and the low-rate limit 108 respectively. These limits may be reference voltage sources which are set to previously determined values and by way of example only when it may take the form of variable resistors to establish the highand low-limit comparison voltages which are compared with the output of the rate-measuring circuit 98.
Driver 94 also has its output coupled by way of lead 110 to a second standstill circuit 112 labeled SS-2. When fibrillation is not present, the pulses from the driver triggers standstill circuit 112. The circuit remains disabled as long as the one-shot pulses occur more frequently than once every 3 seconds (20 beats per minute). If the digital filter output is zero, 88-2 is enabled. A first standstill circuit 114 is connected by a lead 116 to the output of a 5.0-volt Schmitt 74. Standstill circuit 114, labeled 88-], remains disabled as long as the 5.0-volt Schmitt output pulses occur more frequently than once every 3 seconds (20 per minute). If the rate is below 20 per minute, SS-l enables and also enables SS-2. Hence if SS-l remains disabled indicating a signal present at a rate greater than 20 beats per minute (and 88-2 is enabled and indicating a zero digital filter output), a noise indication is made. If the ECG. repetition rate is below 20 beats per minute, both 85-1 and 58-2 are enabled, indicating that cardiac arrest has occured.
Outputs from 85-1 88-2, the high-rate sensor 102, the lowrate sensor 104, and the alarm delay circuit 64 of the fibrillation circuitry which is more fully described below, are routed to alarm gating 118. The signal to the gating from 88-1 is by way of lead 120, from 88-2 by way of lead 122, from the lowrate sensor 104 by way of lead 124, from high-rate sensor 102 by way of lead 126, and from the fibrillation circuitry by way of lead 1.28. Gating 1118 supplies a level depending on the state existing by way of lead 130 to the indicator meter 22 through the battery-electrode test circuit 18. If any of the alarm-gating inputs are enabled, an output from gating 118 is applied by way of lead 132 to alarm generator 134 and by way of lead 136 to beeper gate 96. If an alarm-gating output is present on lead 132, alarm generator 134 produces a 2-second pulse every seconds. The generator output is supplied to the alarm OR gate 138 to pulse an alarm 140 at full volume. If a disable signal is not present from the alarm gating 118, one shot 92 pulses the alarm by way of lead 142 through beeper gate 96 at a volume set by the beeper volume control potentiometer 144. When any alarm condition exists, beeper gate 96 is disabled.
Connected to the alarm OR gate 138 is a low battery circuit I46. If either of the monitor power supplies drops below 9.1 volts, the low battery circuit output changes state to operate the alarm OR gate B8 and sound a continuous tone alarm in alarm 140.
The ventricular-fibrillation-sensing scheme of the present invention indicated generally at 10 in FIG. 1 requires two inputs. One input 36 is the amplified, amplitude-controlled, and filtered ECG. signal, while the other input 93 is a pulse each time an ECG. waveform with the proper characteristics occurs. Input 36 is derived from the automatic gain-controlled preamplifier 24 with band-pass filtering. The second input 93 is derived from the heart monitor one-shot 92 which emits 266-millisecond pulses and is triggered by the digital filter 78 output. The digital filter 78 emits a pulse when the full-wave rectified preamp output which is applied to the digital filter input has the proper pulse width characteristics, as previously explained. I
The output from preamplifier 24 is applied by way of lead 36 to a four-section low-pass fibrillation filter 38 in the improved fibrillation-scnsing circuitry. Fibrillation produces a very erratic somewhat sinusoidal signal with a repetition rate varying between 200 and 500 pulses per minute. Filter 38 has a one-half power point at Hz. and approximately 80db./decade rolloff. The filter passes the fibrillation frequencies of interest while greatly attenuating high-frequency signals (such as 60 Hz, 120 H2., and muscle potentials). In addition, the rapid rolling allows the selection of a higher onehalf power point (while still having good noise attenuation) so that fibrillation signals will be attenuated less.
The signal from filter 38 is applied through a coupling capacitor 40 to a T-schmitt trigger 42. The capacitor coupling shifts the filter output according to the average value of the signal. The time constant is 1.0 second. The T-Schmitt triggers on either input signal polarity when the filter output exceeds +1.5 or -l.5 volts. Hence, the filtered and shifted ECG. is converted to a train of pulses.
The output from the filter 38 is also applied to my new fifth parameter sensing circuit 41 by way of lead 39. This added circuit requires that the output of the fibrillation filter 38 meets certain requirements before the T-schmitt trigger 42 clamp will be released by way of lead 43. At least two positive-going and two negative-going fibrillation filter signals, exceeding +4.0-volt and 4.0-volt levels, respectively, and occuring at a 200 to 500 beats-per-minute rate must be produced at least every 8.0 seconds.'lt is not necessary that the positive pulses bear any time relationships to the negative pulses. If the aforesaid criteria are met, the train of pulses from T-Schmitt trigger 42 are released to an average-duty-cycle-measuring circuit 44 which gives a level output depending on the average duty cycle of the T-Schmitt pulses.
From the duty-cycle-measuring circuit 44, the signal is applied to a duty-cycle-sensing Schmitt 46 which changes state when a duty-cycle-measuring circuit output from the circuit 44 exceeds a value equivalent to approximately 52 percent duty cycle.
The fibrillation-sensing scheme of the present invention can be described as follows: The fibrillation filter 38 acts with the preamp filter of preamplifier 24 to limit the T-Schmitt input to a 3.6 Hz. to 15 Hz. frequency band. A window is established by the T-Schmitt. Average duty cycle is defined as the time related to the period that the signal is outside the window. Much of the nonarrest waveforms are attenuated by the filter so that unusually, most of the T-Schmitt input signal is inside the window giving a low-dutycycle indication providing fifth parameter circuit releases the T-Schmitt clamp. Even if a large nonarrest signal appears at the filter output, nonarrest signals usually have large average DC values. Hence, the signal would be shifted so that more of the signal is within the window, thereby decreasing the average duty cycle. This is illustrated in FIG. 4 which shows a typical filtered nonarrest electrocardiogram indicated by the waveform 48 in FIG. 4. The window is indicated by the plus 1.5 v. line 50 and the minus 1.5 v. line 52. That portion of the electrocardiogram outside the window is indicated as T at 54 whereas the period of the repetitive signal is indicated as 1' at 56. The duty cycle is defined as T l'r.
FIG. 5 shows an electrocardiogram waveform at 58 which is representative of a typical fibrillation signal. Plus 6.0 volts is indicated by the dash line 60 and minus 6.0volts is indicated by the T-wave dash line 62 in FIG. 5. These fibrillation signals are passed by the filter and are not shifted because the average value is essentially zero. Since the waveform has required two positive-going and two negative-going pulses which exceed the pulse 4.0-volt level indicated by line 59 and the minus 4.0-volt level indicated by line 61 in FIG. 5, and since the additional frequency criteria of the fifth parameter circuit are assumed met by this typical fibrillation waveform, the T-Schmitt clamp is released which allows the duty cycle of the signal to be measured. Since the fibrillation waveform 58 is outside the window defined by lines 50 and S2 in FIG. 5 for a long period of time, a large duty cycle is sensed.
When the dutycycle-sensing Schmitt 46 changes state, an alarm delay circuit 64 is enabled. A signal from the output of alarm delay circuit 64 is fed back by way of lead 66 to sensing Schmitt 46. That is, the alarm delay output changes state providing the duty cycle Schmitt 46 remains triggered for at least 5.0 seconds. The delay allows for circuit adjustment to signal changes and prevents an indication of fibrillation when short runs of fibrillationlike nonarrest signals occur. After the output of alarm delay circuit 64 changes state, a 6.5-second relay exists after fibrillation conditions cease to exist before fibrillation is no longer indicated. The latter allows for erratic fibrillation signals which can sometimes disappear for short periods of time.
When the alarm delay circuit 64 changes to a fibrillation indication, the feedback signal on 66 causes the duty cycle trip point of sensing Schmitt 46 to be lowered to a 46 percent duty cycle. This adds controlled hysteresis so that a more erratic fibrillation waveform (as usually occurs with time) resulting in a decreased duty cycle will still be properly indicated.
An erraticity circuit 68 has its outputs connected by way of lead 70 to alarm delay circuit. Circuit 68 acts to reset the alarm delay circuit if the one-shot 92 output is not erratic enough An erratic one-shot output is one for which the distance between pulses is greater than 400 milliseconds.
The latter applies to fibrillation waveforms that have been observed, and also to nonarrest rates below 150 pulses per minute. Rates above 150 pulses per minute for longer than 4.0 seconds from the one-shot 92 will activate circuit 68 which in turn will reset the alarm delay circuit 64. The reason for these criteria is that the amplitude of a fibrillation waveform waxes and vanes as depicted in FIG. 5, causing the present threshold detectors in the circuitry preceding the one-shot 92 to miss pulses in the fibrillation waveform. Thus a high pulse rate fibrillation input to the one-shot 92 will appear at erraticity circuit 68 as a low-rate, constant width pulse train output from the one-shot 92, and will thus be interpreted at 68 as an erratic signal. Any high-rate waveform that does not have waxing and waning fibrillation characteristics will be entirely detected by the said threshold detectors, producing at the one-shot 92 output a train of pulses at the same high rate, thus causing circuit 66 to deem those signals not erratic and to in turn reset the alarm delay circuit. These conditions reduce the chance that high rate, sinusoidal, nonerratic signals such as a ventricular tachycardia (a waveform very similar to ventricular fibrillation) will be indicated as fibrillation.
The improved ventricular-fibrillation-sensing scheme shown generally at of FIG. 1 consists of five basic parameters:
a. the four-section fibrillation filter 38 and associated T- Schmitt trigger 42; b. the duty-cycle-measuring circuit 44, capacitor 40, and associated sensing Schmitt trigger 42;
c. the alarm delay circuit 64;
d. the erraticity circuit 68;
e. the fifth parameter sensing circuitry 41.
The basic function of the above circuitry is to distinguish ventricular fibrillation waveforms from other types of ECG. waveforms and report it as such. The improvement in the scheme over the presented as part of the heart monitor in US. application Ser. No. 789,694 is manifested in the form of the fifth'parameter sensing circuitry 41. Some examples follow of those atypical waveforms which illustrate either those waveforms that would have given a false fibrillation indication or would have been a borderline case in the sensing circuitry of the aforesaid earlier scheme.
During surgery to repair a special defect in a child, the ECG. measured with the one lead configuration on the monitor of the aforesaid application produced waveform 45 depicted in FIG. 6. The heart rate was higher than would usually be seen in an adult and approached 150 beats per minute. Due to the presence of the large P-wave 47 and T-wave 49 in FIG. 6, which would be passes by the fibrillation filter, the measured duty cycle would be large. In addition, the heart rate was not high enough to operate the erraticity circuit 68. Hence, a false indication of fibrillation was made. When the fifth parameter sensing circuitry 41 was added, the false alarm was eliminated. The QRS coupled 51 in FIG. 6 would be attenuated and even if the P-wave QRS complex T-wave pulses occurred at the 200 to 500 beats-per-minute rate, they would still operate only the positive half of the fifth parameter circuit, as explained more fully in the detailed description below. Hence, the T-Schmitt 42 would be disabled.
In one test, because of an open lead, a large amount of the noise was superimposed on the ECG. signal. Much of the noise was in the form of a low-frequency baseline shifts, as shown by waveform 53 in FIG. 7. However, the AGC 28 adjusted to the peak value of the signal, which included the fast rise-time QRS complex. Hence, much of the signal would be attenuated by the fibrillation filter 38, and again, even if pulses occurred at the right rate, only the polarity would be sensed by the fifth parameter circuit. Hence, the T-Schmitt would again be clamped.
At 55 in FIG. 8 is shown a sketch of a ventricular tachycardialike signal produced following defibrillation. The rate was below 150 beats per minute, thus the erraticity circuit could not be of help. However, pulses would not occur rapidly enough, even if both of the fifth parameter Schmitts (which sense opposite polarities) were triggered, to be sensed as fibrillation signals. Therefore, the duty cycle would again be measured.
The waveform shown at 57 in FIG. 9 was on the borderline of being indicated as ventricular fibrillation without the fifth parameter. Its duty cycle is large and the rate seen by the erraticity circuit was just below 150 pulses per minute because the second full-wave rectified pulse was skipped. The fifth parameter circuit senses that the waveform lacks the proper rate characteristics and rejects it as a nonfibrillation waveform. Hence, a large leeway is afforded by the fifth parameter circuit for distinguishing fibrillation from closely similar waveforms.
It is clearly seen therefore that the fifth parameter circuitry 41 senses additional important parameters inherent in the nature of ventricular fibrillation waveforms, namely, pulses of opposite polarities exceeding a specific voltage level, particular frequency range of pulses, and sustained indication of such characteristics. The means for accomplishing this is explained more fully in the detailed description of the fifth parameter circuitry below.
DETAILED DESCRIPTION OF BLOCKS 38, 42, 44, 46, 64, AND 68 OF FIG. 1
FIGS. 10 through 15 are more detailed block diagrams of preferred forms of the blocks 38, 42, 44, 46, 64 and 68 respectively, of the ventricular-fibrillation-sensing circuitry 10 in FIG. 1.
FIG, 10 is a block diagram of the fibrillation filter 38 of FIG. I. It comprises a Darlington emitter follower 208 labeled D1 a two-section low-pass filter 210 labeled F-l, a pair of additional Darlington emitter followers 212 and 214 labeled D-2 and D-3, respectively, a second two-section low-pass filter 216 labeled F-2, and a fourth Darlington emitter follower 218 labeled D-4. Emitter follower 208 is complementary to emitter follower 212 and similarly emitter follower 214 is complementary to emitter follower 218. This arrangement compensates for transistor input temperature changes. Filters 210 and 216 act to give a half power point at 15 Hz. and db./decade rolloff. The output is fed to T-Schmitt 42 of FIG. 1 by way of lead 217 and to fifth parameter circuit 41 by way of lead 39.
FIG. 11 is a block diagram of the T-Schmitt trigger 42 of FIG. 1. This Schmitt trigger is coupled to input capacitor 40 by way of an input attenuator 220. The attenuator feeds a pair of parallel or twin paths 222 and 224, the first comprising an emitter follower 226 and positive-going Schmitt trigger 228. The second path comprises an emitter follower 230 and negative-going Schmitt trigger 232. The output of negative-going Schmitt trigger 232 feeds the positive-going Schmitt trigger 228 by way of lead 234. Capacitor 40 and attenuator resistor 220 give level shifting with a l-second time constant. Whenever the signal is outside the window established by Schmitt triggers 228 and 232 of plus 1.5 volt and minus 1.5 volt around zero, the output then changes state, provided a release signal is received by way of line 43 from the fifth parameter sensing circuit 41 of FIG. 1. Emitter follower 226 compensates for emitter to base voltage changes of the input transistor to Schmitt trigger 228 and emitter follower 230 likewise compensates for emitter-base voltage changes in the input transistor of negative'going Schmitt trigger 232.
FIG. 12 is a block diagram of the duty-cycle-measuring circuit 44 of FIG. 1. The duty-cycle-measuring circuit comprises a driver 236 feeding a capacitor 238 by way of lead 240. The driver also feeds an emitter follower 242, the output of which is connected to a constant current driver 244 by way of a current-determining resistor 246. A compensating and biasing source (not shown) is connected to a second emitter follower 248 by way of lead 250 and the source also feeds capacitor 238 over lead 252. A third emitter follower 254 connects the second emitter follower 248 to the other input of the constantcurrent driver 244 by way of lead 256. The driver output is then connected through attenuator resistance 258. Driver 236 provides an output of constant amplitude pulses except for compensation for power supply changes. Capacitor 238 applies essentially the same transient to emitter followers 242 and 248 and charges up to a voltage corresponding to the average duty cycle of the input pulses. Emitter follower 254 compensates for emitter-base voltage changes of the transistor of constant current driver 244. The voltage across capacitor 238 is essentially applied across current determining resistor 246, producing a corresponding current output from driver 244. The driver current flowing in attenuator resistance 258 produces an output voltage proportional to the average duty cycle of the circuit of the circuit input pulses.
FIG. 13 is a detailed block diagram of the duty-cyclesensing Schmitt 46 of FIG. 1. It comprises an emitter follower 260 feeding a voltage-controlled Schmitt trigger 262. The output from the alarm delay 64 of FIG. 1 is fed to the duty-cyclesensing Schmitt 46 over lead 66 and passes into element 264 which is a Schmitt trigger trigger point modification driver. The output of driver 264 is fed to control-voltage-biasing network 266 which feeds voltage-controlled Schmitt trigger 262 through a second emitter follower 268. Emitter follower 268 and the control-voltage-biasing network 266 act to set the trigger threshold of Schmitt trigger 262. Emitter follower 260 compensates for voltage changes of the input transistor of the Schmitt trigger. Emitter follower 268 compensates for temperature-related forward voltage drop changes in a diode used in the Schmitt trigger control input. When the Schmitt input rises above the threshold value, the output changes state. The trigger point modification driver 264 acts to reduce the Schmitt trigger threshold when the alarm delay circuit is enabled.
FIG. 14 is a diagram of the alarm delay circuit 64 of FIG. 1. It comprises an input-timing network 270 receiving a reset signal over lead 70 from erraticity circuit 68 of FIG. 1. The output of timing network 270 is connected through an emitter follower 272 to a Schmitt trigger 274. The Schmitt trigger feeds a driver inverter 276 from which the output for lead 128 is derived. The input to divert 94 of FIG. 1 is taken by way of lead 95 from the output driver inverter 276. The output to trigger point modification driver 264 of FIG. 13 is taken by way of lead 66 from the output of Schmitt trigger 274. When the input to timing network 270 changes states, the output of the timing network exponentially rises with a set time constant. When the input to the timing network resets, an exponential fall in the timing network output likewise occurs, but with a longer time constant. The timing network, emitter follower 272, and Schmitt trigger 274 act to provide a 5.0 second delay between the time the input to timing network 270 changes state and the output of the Schmitt trigger 274 changes state. After the Schmitt trigger changes state, approximately a 6.5-second delay exists before the Schmitt trigger can reset.
FIG. 15 is a block diagram of the erraticity circuit 68 of FIG. 1. It comprises a 400-millisecond timer 278, a 4.0-second timer 280, and a driver 282. Timer 278 is reset when a positive pulse is received and it changes state (enables) 400 milliseconds later. When timer 278 changes state, timer 280 is reset. Timer 280 changes state 4.0 seconds after timer 278 is reset, providing timer 278 continues to be reset. Therefore, if
DETAILED DESCRIPTION OF BLOCK 41 OF FIG. 1
FIG. 16 is a detailed block diagram showing a preferred form of the fifth parameter circuitry 41 of FIG. 1. The input 39 is fed by way ofinput attenuator 101 to a pair of parallel or twin paths 103 and 105, the first of which feeds positive Schmitt trigger 107 and the second of which feeds negative Schmitt trigger 109. The input attenuator acts with the positive and negative Schmitt triggers to set :4.0-volt thresholds, outside of which the corresponding Schmitt changes state. When the positive Schmitt 107 is triggered, the lO-millisecond one show 111 emits a pulse. During the time of the pulse one AND gate 131 input fed from one shot 111 by line 115 is in the ON state, while the other input fed by 127 is in the OFF state. Hence, the 8.0-second timer 135 remains disabled. Also, during the IO-millisecond pulse, the l20-millisecond timer 119 is held released. At the end of the one-shot pulse the l20- millisecond timer 119 begins to run. If timer 119 input pulses occur more rapidly than every 120 milliseconds (500 beats per minute), the timer 119 will not produce a trigger pulse for the l80-millisecond timer 123. If the time between pulses is greater than 120 milliseconds the ISO-millisecond timer 123 will be triggered and the AND gate 131 input fed by line 127 will be opened. Hence, a 180-millisecond window exists during which an AND gate 131 output will be produced ifa pulse is received by way of line 115. Ifa pulse occurs during the window time, the 8.0-second timer 135 will be reset. Such pulses would therefore be occuring at a 200 to 500 beats-per-minute rate. As long as the 8.0-second timer 135 is reset at least once during an 8.0-second period, the timer 135 output will remain enabled. The lower half of FIG. 16 operates the same time as the upper half except that negative-going fibrillation filter output pulses are sensed. If both 8.0-second timers 135 and 137 are enabled, the output AND gate 143 fed by lines 139 and 141 changes state, and the output releases the T-Schmitt 42 clamp of FIG. 1 corresponding to fibrillation conditions. If either 8.0-second timer becomes disabled the AND gate 143 will not release the T-Schmitt 42 clamp, and ECG duty cycle will not be measured.
FIGS. 17 through 22 show the blocks of FIG. 16 in greater detail Note that the circuitry in the upper half of FIG. 16 is the same as that in the lower half, but the opposite transistor and power supply polarities are used.
FIG. 17 is a block diagram of the positive and negative Schmitt triggers 107 and 109 of FIG. 16. The circuit comprises an emitter follower 15] labeled E-l which feeds a Schmitt trigger 153 labeled S-l. E1 compensates for emitter to base voltage changes of the input transistor in S1. The threshold of the Schmitt 153 is set by the input attenuator 101 of FIG. 16.
The lO-millisecond one shot 111 of FIG. 16 is the same type as used in the QRS sensing circuitry of the heart monitor labeled 92 in FIG. 1. Details of its operation are outlined in aforesaid US. application Ser. No. 789,894. The one shot 111 of FIG. 16 emits a IO-millisecond pulse which is fed to timer 119 and to AND gate 131.
FIG. 18 is a block diagram of the l20-millisecond timers 119 and 121 of FIG. 16. The circuit is comprised of an input driver 155 labeled D-] which feeds a l20-millisecond timing circuit 157 labeled T-l. D-1 clamps T-1 during the time the IO-millisecond one shot, from which the input to D-1 is derived, is triggered. When the latter resets, T-I starts to run, and, if after 120 milliseconds D-1 is not enabled, an output trigger pulse is produced.
FIG. 19 is a block diagram of the ISO-millisecond timers 123 and 125 of FIG. 16. The input which is derived from the l20-millisecond timer feeds circuit 159 which differentiates and DC restores the input pulses, assuring that the timer 163 reset signal will be applied only as long as necessary and in the proper polarity. The input driver 161 clamps the ISO-millisecond timer 163 when an input pulse is received. Afterthe differentiated input pulse has been removed, the l80-millisecond timer 163 begins to run. Ifa second input pulse is not received which would act to reset the timer 163 during the millisecond interval, an output pulse will be produced.
FIG. 20 is a block diagram of the and gates 131 and 133 of FIG. 16. The two inputs 127 and 115 are derived from the iii! l80-millisecond timer and the lO-millisecond one shot, respectively. The first input 127 is inverted by circuit 165 and the clamp R67 is removed upon receiving such a signal. llnput 115 releases the clamp 16? when a signal is present. An output is produced at ll7l only when signals exist concurrently at B27 and 115.
FlGv 21 is a block diagram of the 8.0-second timers i135 and 137 of FIG. R6. The circuit is comprised of a Darlington driver E73 labeled DDE which feeds an 8.0-second timing circuit 175 labeled 'lll.DD-l clamps T-l when an input signal from the AND gate is received. As long as Tl remains clamped, and for l. seconds after the clamp is removed, a reset or enabled output condition exists. At the end of the 8.0-second period, T-Il disables.
FIG. 22 is a block diagram of the output AND gates M3 of FIG. to. The two inputs i139 and 141 are derived from the 8.0- second timers i135 and 137 of FIG. to. When an ON signal is received at input Mil, inverter i181 inverts the pulse which is fed to driver 1183 which in turn releases clamp H85. Thus, if an ON signal is received at input 139 and is released by clamp 185 by way of line 187, the pulse will be inverted by circuit 1177 and thus operate driver 1179 to produce an output which released the clamp on T-Schmitt 42 of FIG. 1. As long as cir cuit 185 clamps input K39, the T-Schmitt 42 remains clamped, and the ECGs duty cycle will not be measured.
I wish it to be understood that I do not desire to be limited to the exact details of construction shown and described, for obvious modifications will occur to a person skilled in the art.
I claim as my invention:
R. In a heart monitor having means to sense electrocardiogram waveforms including means to provide an indication of ventricular fibrillation, an improved fibrillation-sensing circuit comprising: input terminals for coupling said circuit to a source of electrocardiogram waves, output terminals for coupling said circuit to an alarm, and means within said circuit for preventing a false indication of ventricular fibrillation in response to an electrocardiogram waveform which is characterized by at least two pulses each in the positive and negative polarities of the required amplitude occuring within a predetermined time interval and by a pulse rate of 200 to 500 pulses per minute from said input.
2. A fibrillation-sensing circuit according to claim 2 wherein said means for preventing a false indication of ventricular fibrillation comprises means for establishing threshold levels, means for detecting the presence of at least two positive-going and two negative-going pulses within a predetermined time interval, means for detecting a 200 to 500 pulse-per-minute rate, and means for providing an output should all aforesaid conditions be met.
3. A fibrillation-sensing circuit according to claim 2 wherein said means for establishing threshold levels comprises an input attenuator and two Schmitt triggers which act on said input waveform to detect all pulses that exceed the i4.0-volt level.
4. A fibrillation-sensing circuit according to claim 2 wherein said means for detecting a 200 to 500 pulse-per'minute rate comprises a l-millisecond timer combined with a ISO-millisecond timer and an AND gate which interact to allow passage of any signal that presents the proper distance between pulses.
5. A fibrillation-sensing circuit according to claim 2 wherein said means for detecting at least two positive-going and two ncgative'going pulses within a predetermined time interval comprises two parallel-connected detection circuits, one of which senses positive-going pulses and one which senses negative-going pulses, each of said detection circuits comprising a Schmitt trigger, a one shot circuit connected to receive the said means for establishing said time interval comprises an 8- second timer which remains ON as long as the required two input pulses occur within the minimum 8-second interval.
7. A fibrillationsensing circuit according to claim I wherein said circuit includes a low-pass filter connected to said input terminals, a trigger circuit that receives the output from said low-pass filter, a fifth parameter sensing circuit connected in parallel with said trigger circuit and including said means for preventing a false indication of ventricular fibrillation, a dutycycle-measuring circuit connected to receive the output from said trigger circuit when said output is released by said fifth parameter sensing circuit, and an alarm delay circuit con nccted to receive the output from said duty-cycle-measuring circuit.
8. ln apparatus for monitoring a myocardial waveform, a circuit for providing an alarm-actuating signal in response to a waveform produced by ventricular fibrillation, said circuit comprising:
a. first means responsive to said waveform for sensing whether said waveform includes at least two peaks exceeding a predetermined abnormally high amplitude within a predetermined time interval;
b. second means responsive to said waveform for sensing whether the heart pulse rate is within a predetermined abnormally high range;
c. third means, responsive to the outputs of said first and second means, for providing an ON signal only when the conditions sensed by said first and second means are both present; and
d. fourth means, responsive to at least the output of said third means, for providing said alarm actuating signal in response to the presence of at least said ON signal.
9. The invention according to claim 8 wherein said first means senses whether said waveform includes at least two positive-going and at least two negative-going peaks exceeding said predetermined abnormally high amplitude within said predetermined time interval.
H0. The invention according to claim 9 wherein said time interval is approximately 8 seconds.
111. The invention according to claim 8 comprising:
a. an input attenuator;
b. first and second parallel circuits having their inputs both connected to the output of said input attenuator, each of said parallel circuits comprising 1. a Schmitt trigger,
2. a one-shot circuit connected to the output of said Schmitt trigger,
3. a first timer connected to the output of said one-shot circuit,
4. a second timer connected to the output of said first timer,
5. an AND gate connected to receive the outputs of said one shot and said second timer,
6. a third timer corresponding to said time interval connected to output of said AND gate; and
c. an output AND gate connected to receive the outputs of said first and second parallel circuits and producing an ON signal when the conditions sensed by said first and second means are both present.