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Publication numberUS3614739 A
Publication typeGrant
Publication dateOct 19, 1971
Filing dateMay 2, 1969
Priority dateMay 2, 1969
Also published asCA929640A1, DE2021302A1, DE2021302B2, DE2021302C3
Publication numberUS 3614739 A, US 3614739A, US-A-3614739, US3614739 A, US3614739A
InventorsWilliam E Johnson
Original AssigneeOwens Illinois Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated driving circuitry for gas discharge panel
US 3614739 A
Abstract  available in
Images(3)
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Claims  available in
Description  (OCR text may contain errors)

iUiiite Mates Patent [72] Inventor William E. Johnson OTHER REFERENCES Solid State Electroluminescent Di splay and Scanning Apparatus" R. S. Lynch IBM Publication Vol. 9 N0. 12 May l967,ppv 1799-1801 (copy in 340/166) Primary Examiner-Donald J. Yusko [73 1 Assignee Qwens-Illinois, Inc.

All0rneysE. J. Holler and Donald K. Wedding [54] INTEGRATED DRIVING CIRCUITIRY IFOR GAS ABSTRACT: Solid-state low-level to high-level interfacing circuits for multiple discharge gas discharge devices capable of feeding through a high-level periodic sustaining voltage to the discharge device with minimum de adation. The output is the algebraic sum of the periodic sustaining voltage and a level 3 F L m mm Amw Pr E W G4" Ham cm. w s DIU M 307/246, 315/169 Int.

- j 17/38, converted logic signal. NPN circuits are used to drive one set H051) 37/00 of conductors in an array and PNP circuits are used for drivin Field flfseallfchmm transversely related conductor arrays in the gas discharge 340/166, 174 rication of the integrated y device. Dielectric isolation in the fab circuits is utilized and the circuits a re such as to not require any inductance or capacitance elements, thus reducing cost and size of the circuits. The circuit appears as a low im- [5 6] References Cited UNITED STATES PATENTS re is no mixing of active elements it wafer or chip. Consult the specification for features and details.

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3,522,471 8/1970 Somlyody..................... 315/846 PATENTEUucr 19 19H 3 v 6 l 4 7 3 9 SHEET 1 [1F 3 LOGIC INVENTOR WILLIAM E. JOHNSON ATTORNEYS FIG. 1

PATENTEDBET 19 l97| 3,6 1-4J39 SHEET 2 BF 3 FIGZ INTEGRATED lillllilliVllNG ClllitCUll'llRY EUlit GAS DllSQliliAmGlE lPANlElL The present invention relates generally to driving circuitry for transversely oriented conductor arrays and matrices in display and/or memory panels and devices and more particularly to driving circuits for high-voltage devices such as gas discharge panels, which are capable of being produced in integrated circuit form.

BACKGROUND OF THE INVENTION In Baker et al. application Ser. No. 686,384, filed Nov. 24, 1967 (now U.S. Pat. No. 3,499,167), and entitled Gas Discharge Display-Memory Device and Method" there is dis closed a multiple discharge display and/or memory panel which may be characterized as being of the pulsing discharge type having a gaseous medium, usually a mixture of two gasses at a relatively high gas pressure, in a thin gas chamber or space between opposed dielectric charge storage members which are backed by conductor arrays, the conductor arrays backing each dielectric member being transversely oriented to define or locate a plurality of discrete discharge volumes or sites and constitute a discrete discharge unit. in some cases, the discharge units may be additionally defined by physical structure such as perforated glass plates and the like and in other cases capillary tubes and like structures may be used. In the above-identified U.S. Pat. application of Baker et al., physical barriers and isolation members for discrete discharge sites have been eliminated. In such devices charges (electrons and ions) produced upon ionization of the gas at a selected discharge site or conductor cross-point, when proper operating potentials are applied to selected conductors thereof, are stored upon the surfaces of the dielectric at the selected locations or sites and constitute an electrical field opposing the electrical field which created them. After a firing potential has been applied to initiate a discharge, the electrical field created by the charges stored upon the dielectric members aid in initiating subsequent momentary or pulsing discharges on succeeding half cycles of an applied sustaining potential so that the applied potential, and hence the stored charges indicate the previous discharge condition of a discharge unit or site and constitute an electrical memory. However, because the conductor arrays utilized in creating such discharges are isolated from the gas medium by the dielectric means and because of the relatively high gas pressures, the potentials required for operating such panels are relatively high.

A significant improvement in operating voltage requirements has been achieved by utilization of an argon-neon gas mixture as disclosed in the application of James F. Nolan Ser. No. 764,577 filed Oct. 2, 1968 and assigned to the assignee of the present invention. The gas discharge panel disclosed in the Nolan U.S. lP'at. application is filled with a gas mixture composed of about 99.9 atoms of neon and about 0.1 atoms of argon at an absolute pressure of 24.62 inches of mercury (Hg). in a gas discharge panel constructed in accordance with the teachings of the Nolan application, a sinusoidal or periodic sustaining voltage is continually applied to all conductors of the panel at a measured frequency of about 50 kHz. to sustain discharges at selected discharge sites after they have been turned on at a higher voltage, a typical periodic sustaining voltage for the panel was in the range of 335 to 350 volts peak to peak. in dynamic operation, in addition to the sustaining voltage, a 2 microsecond pulse, is superimposed on and algebraically added to the sine wave applied to selected transverse conductor pairs in the conductor arrays to manipulate discharge conditions of discharge sites. Such pulse voltages were applied by means of pulse transformers and like devices in the manner disclosed in Johnson et al. application Ser. No. 699,170 filed Jan. 19,1968 now U.S. Pat. No. 3,513,327.

The present invention is directed to a solid-state circuit useful as an interfacing circuit for a gas discharge panel, such solid-state circuit being capable of being made as an integrated circuit not requiring the use of a pulse transformer. This results in a reduction in size and cost and enables the discharge condition manipulating pulses to be equal to a direct current power supply voltage which is common to all circuits of the same conductivity type. This commonality insures uniform pulse height not economically attainable when transformers are used.

Integrated circuits in accordance with the present invention are in two fonns: one form utilizes PNP-type semiconductor and the second form utilizes NlPN-typc semiconductor. For gas discharge panels of the type disclosed in the aforementioned Baker et al. U.S. Pat. application, both forms are necessary to drive the transversely related conductor arrays. The lPNP-type semiconductor circuit is used to produce positive output pulses and the NPN-typc semiconductor circuit produces negative output pulses while in each circuit there is low power dissipation during quiescent conditions. Low power dissipation is a desirable feature since in a 4' 'X4" display area, with conductor arrays having conductors on 30 mil centers, there will be approximately 33 conductors or lines per inch resulting in 132 conductors per array or 264 lines to be driven. Functionally, the circuits operate as low-level to high-level interfacing devices feeding through a high-level periodic signal with minimal degradation. in effect, each individual circuit serves as a two input, one output device where one input is a high-level periodic signal (the sustaining voltage) and the other input is a lowlevel logic signal. The output is the algebraic sum of the high-level periodic signal and the level converted logic signal and appears as a low impedance to the panel.

Objects of the invention include the provision of a solidstate interfacing circuit for gas discharge devices capable of being produced in integrated circuit form with an attendant reduction in size and cost; improvement in uniformity of operating potentials applied to the panel; the elimination of transformers or other inductive devices as well as the elimina' tion of capacitance elements in the circuits; low-impedance circuits for driving gas discharge devices in which there is low power dissipation during quiescent condition; and circuits for converting low-level logic signal to a high-level operating voltage and algebraically adding the high operating voltage to a high-level periodic sustaining voltage continuously applied to conductors of conductor arrays in the device.

The above and other objects, advantages and features of the invention will become apparent from the following specification when considered with the accompanying drawings wherein:

FIG. 1 is a diagrammatic illustration of a gas display panel and electrical driving system incorporating the invention,

FIG. 2 is a partial circuit schematic diagram illustrating the invention as applied to driving a gas discharge panel,

FIG. 3 is an enlarged view of an integrated circuit chip carrying one set of four of the interfacing circuits 2t) and 21 of IF 1G. 2, and

FIG. 3A is a cross-sectional view of the integrated circuit chip taken on lines 3A-3A of FIG. 3.

The invention will be described as it is employed in a system supplying operating potentials to a gas discharge display memory device of the type described. earlier herein. Such a device is diagrammatically illustrated in FIG. 1 of the drawings as having a horizontal or row conductor array 111 and vertical or column conductor array 12. Alternate conductors in an array are brought out at the sides, respectively, of the panel to facilitate making electrical connections thereto. Normally, oppositely phased periodic potentials l3 and 141 are applied to conductor arrays 11 and 12, respectively, so that approximately half the potential necessary to manipulate a discharge unit in a manner described later herein is applied per conductor. Thus, if the periodic potential across the gas in the discharge panel necessary to operate the device is 350 volts peak to peak, then one-half this voltage is applied to the conductors of conductor array 11 and the other half (oppositely phased) is applied to conductors in conductor array 12 and such potentials are delivered from periodic voltage generator portions 115 and 16, respectively, (which may be of 20-1...20N and 21-1...2l-N with minimum degradation. As shown, sustaining potentials for all row conductors 11-1, 11-2...11-N of conductor array 11, are supplied from sustaining generator portion 15 and all vertical or column conductors 12-1, 12-2 ..12-N in conductor array 12 are supplied from sustaining voltage generator portion 16; and these potentials are continually applied to the conductor arrays on panel 10 during normal operation thereof. Individual discharge sites located by the crossing of selected conductors of conductor arrays 11 and 12 are manipulated by adding high-voltage unidirectional voltage pulses to the sustaining voltages on selected conductors of arrays 11 and 12, respectively, which, when combined, are sufficient to initiate a sequence of discharges, one for each half cycle of applied sustaining potential at any selected discharge site. By properly timing such pulses the sequence of discharges may be terminated so that any individual discharge site may be manipulated, ON and OFF, by manipulation of the times of occurrences of the unidirectional voltage pulses.

As noted above in a 4" 4" display area on a panel, with 30 mil spacing between conductors there may be 132 row conductors and 132 column conductors, each conductor of which, while having a common sustaining voltage applied thereto; must have the manipulating voltage pulses applied at selected times in accordance with the information to be displayed and/or stored upon the panel. Such large numbers of driving circuits per panel requires that the size and cost thereof be reduced as much as possible, and, at the same time, maintain the uniformity of potentials supplied to the conductors of the respective arrays. While such panels as the present invention is concerned with have been driven by pulse transformers and the like devices fairly successfully, it is desireable that use of large numbers of pulse transformers in commercial applications of such panels be eliminated.

In accordance with the present invention, each of the circuits 20 and 21 is formed as a circuit on an integrated circuit wafer or chip and while all similar or like circuits may be formed on a single wafer or chip, commercially, at the present time for yield purposes it is only feasible to place 4 such circuits on a single chip or wafer. Further, transistors used in the row conductor circuits 201...20N are of the NPN types to produce a negative output pulse whereas transistors in the circuits 211...21N are PNP type to produce a positive output pulse. As explained more fully hereinafter, obviously, NPN types may be used to drive column conductors and PNP types may be used to drive row conductors. At selected times, each of circuits 20-1...20-N and 211...21N receive a low-level logic pulse (approximately 4 volts) from logic circuit 40 which may receive an input 41 from a computer or other digital data input device for display and/or storage on the panel. For example, the upper half 40-A of logic circuit 40 supplies row conductor interface circuits 20-1 with a positive logic pulse signal whereas the lower half 40A of logic circuits 40 supplies a negative logic pulse signal to column interface circuits 21 and in the normal operation, such positive and negative logic pulses are applied simultaneously to selected conductors to selectively initiate discharges and to terminate discharges at selected discharge sites within the panel 10. Such logic addressing circuitry or system may be relatively inexpensive line scan systems or the somewhat more expensive high speed random access system.

INTERFACING CIRCUITS F IG. 2 shows a plurality of interfacing circuit 20A... 203 for driving individual row conductors 11A...11B, respectively, of array 11 and a plurality of interfacing circuits 21 for driving column conductors 12A...12B respectively in array 12. It will be noted that the circuit configuration 20A...20B shown in FIG. 2 includes NPN-type transistors and the circuit configuration 21A...20B shown includes PNP-type transistors; the difference between the circuits being for purposes of supplying opposite polarity and phase signals for driving associated conductors in the arrays.

Circuit configuration 20 will be described in detail, it being understood that except for reversal of direct current supply potentials and the conductivity type of the transistors involved, the operations are the same for circuit configuration 21. A low impedance, high-voltage level direct current source 50 having a pair of output terminals 51 and 52 are connected to operating potential terminals 53 and 54 of interface circuit 20. Interface circuit 20 includes a first NPN transistor Q1 having its emitter E connected through diode D1 to input terminal 54. Collector C of transistor O1 is connected through a collector resistor R3 to terminal 53. Resistor R3 is about 15,000 ohm, and is a compromise of rise time and power dissipation for bias current from the direct current coupled to transistor 01 and transistor Q2. The base of transistor Q1 is connected through resistor R1 to logic signal input terminal 56 on which is applied a low-level positive logic signal pulse 57 from logic circuit 40. There are a plurality of output conductors from logic circuit 40, one for each conductor interface circuit. Resistor R2 is connected between the base B of transistor Q1 and terminal 54 and is used with resistor R1 to match interface circuit 20 to the logic circuit 40. Resistors R1 and R2 may be eliminated if the interface circuit 20 is matched to the logic circuit 40. Diode D3 is connected between input logic terminal 56 and collector C of transistor Q1 and serves the same purpose as diode D1 in speeding up the response of transistor Q1 to an input logic signal. Diodes D1 and D3 are not essential to operation of the circuit and may be eliminated if desired. However, the circuit may incorporate diode AND gates (coincidence circuits) to thus reduce the necessary logic circuitry external the circuit, that is to say that the circuit may be fabricated to include a portion of the addressing logic circuits 41. A second NPN transistor Q2 has its base B connected directly to collector C of transistor 01 and its collector C connected directly to terminal 53. Emitter E of transistor Q2 is connected directly to output terminal 60 which is connected directly to a conductor in conductor array 12. The collector C of transistor Q1 is connected through sensing diode D2 to the output terminal 60; diode D2 sensing the direction of current flow and aids in turning transistor Q2 ON and OFF as described more fully hereinafter.

Sustaining voltage generator portion 15 has its output terminal connected directly to input terminal 53 and to terminal 51 of the low impedance high-voltage level direct current voltage source 50. It should be noted that a capacitor 61 and a battery 50B are shown as constituting the low-impedance high-voltage level direct current source 50 so that the periodic sustaining voltage appears at both the collector C of transistor Q2 and the emitter E of transistor Q1, in the latter case via the bridging capacitor 61. Such capacitor 61 may be constituted by the filter capacitor means at the output of power supply 50.

OPERATION OF SYSTEM Normally, transistor O2 is conducting and transistor O1 is nonconducting so that the periodic voltage (approximately volts peak to peak) from sustaining voltage generator portion 15 is applied through collector C of transistor Q2. On negative half cycles of the sustaining voltage current flows through collector C, base B of transistor Q2 and diode D2 to terminal 60 whereas on negative half cycles of sustaining voltage current fiows through the collector-emitter circuit of transistor Q2 to the output terminal 60 so that there appears on output terminal 60 a sinusoidal voltage corresponding to the waveform of the voltage from sustaining voltage generator portion 15. This sustaining voltage appears on all row conductors of conductor array 11 via the interfacing circuit 20 corresponding to the row conductor. In a similar fashion, the oppositely phased sustaining voltage from generator portion 16 appears on the column conductors of conductor array 112 via interfacing circuits Ell.

Whenever a low-level positive voltage pulse 57 from logic circuit d ll is applied to logic input terminal 56, and base B of transistor Qll, transistor Oil is rapidly made conductive or turned 0N so that the collector C thereof, which prior to switching of transistor Qll had been at essentially zero direct current potential, rapidly falls (relatively) to the potential (-175 volts) of the high-voltage level direct current source 50 for the time period that transistor Qll is in a switched or ON state. This high direct current voltage is passed through diode D2 to output terminal hill to constitute one component of the output voltage during the time interval when the transistor Qll is in its switched state. As noted earlier, the periodic sustaining voltage from generator portion passes through the low-impedance high-voltage level direct current voltage source fill (via diagrammatically illustrated capacitor 611) and also appears at the emitter E of transistor Qll so that when transistor (M is switched UN, for the period of time that transistor Qll is switched ON, this voltage is likewise passed through to collector C of transistor Qll and thus, through diode D2 to appear as a second component of the output voltage appearing on output terminals dill. Thus the high direct current potential and the sustaining voltage are algebraically added to constitute a pulse voltage l/H t for manipulating the discharge condition of a selected discharge site. in a similar fashion, a negative logic pulse 57' applied to one of interface circuits 2i (ZllA for example) connected to a column conductor (TEA for example) of conductor array i2; is translated to a high level discharge manipulating pulse VFC on the selected column conductor. By properly timing the occurrence of logic pulse 57, the highvoltage direct current pulse produced as a result of the switching action of transistor Qll is algebraically added to a negative going half cycle of the sustaining voltage to constitute a firing voltage pulse VlF applied to a selected discharge site simultaneously with the application of a similar pulse to a selected column conductor to thereby initiate a sequence of discharges in a selected gas volume or discharge site and thereafter, the sustaining voltage augmented by the potential due to stored charges, will sustain such sequence of discharges as described earlier. When it is desired to terminate a discharge, logic pulse 5'7 may be timed to occur at that part of the sustaining signal such that a controlled discharge of the addressed site is initiated resulting in extinction of the discharge process (e.g., terminating the sequence of discharges) on succeeding sustaining signal cycles, as more fully explained in Johnson et al. application Ser. No. 699,170, filed Jan. 19,

lhlTlEGllATlED ClllRCUlT FABRICATION MG. 3 illustrates a top plan view of the integrated circuit device carrying four interface circuits on a single chip which may be contained within a hermetic enclosure or package (not shown) or otherwise protected from ambient environment. individual contact terminals may have wires connected thereto and extending through the exterior of the package for connection to external circuitry.

The integrated circuit shown in H6. Si is preferably formed by the well-known dielectric isolation technique or process which, in general, is as follows: a device wafer and a handle water (not shown) are thermally oxidized and the oxidized surfaces are fused under pressure at high temperature. The device wafer is then chemically etched to a selected uniform thickness across the wafer and then the wafer assembly is thermally reoxidized. Using photolithographic techniques, the silicon dioxide on the wafer is photoengraved to form a mask which is used to etch device islands l,...lll in the device wafer; N+ collector diffusion is made into the surface of the device islands to lower the collector saturation resistance and then the device islands are thermally oxidized. A layer of polycrystalline silicon is deposited over the oxidized device islands to a selected thickness and then the handle wafer is removed by chemical etching. The remaining single crystal device islands, insulated by silicon dioxide and embedded in the polycrystalline silicon matrix are thermally reoxidized to form an oxide coating which is used to mask against boron diffusion for the base geometry of the integrated transistor and diode components. Such device islands are identified by Roman numerals IA, lB, IC, lD, ll and Hi; device islands lA, lB.. containing transistors Q11 and diodes D2 and D3; device island ll containing diodes D11; and device island lll containing transistors Q2. it will be appreciated that a large number of integrated circuit chips may be formed simultaneously in a wafer. A boron dilfusion is made into the silicon through the openings in the silicon dioxide. The diffused area is reoxidized. The emitters and collectors of the PNP transistors Q and Q2 are photoengraved and a P+ diffusion is made through the openings and the openings are reoxidized. The emitter is engraved for the NPN transistors and high concentration phosphorous is diffused to obtain the specified Beta for the NlPN transistors. Cathode regions for the diodes are formed during emitter formation. The contacts for NPN and PNP transistors are photoengraved.

An oxide is deposited over the surface of the wafer by cracking Sill-l in an oxidizing atmosphere, to form an insular ing base for the deposition of tantalum nitride resistor components R11, R2 and R3. The tantalum nitride is sputtered in a vacuum to the proper thickness to obtain the required sheet resistivity. immediately after sputtering tantalum nitride, alu minum is evaporated over the wafer surface. The aluminum is photoengraved to form the ohmic contacts for the tantalum nitride resistors and the tantalum nitride is photoengraved to form the actual resistors. Using the same contact mask, windows in the deposited oxide are opened and aluminum is evaporated over the surface of the wafer. This aluminum is photoengraved to form the interconnections of the components in the integrated circuit.

In FIG. 3, the active component areas are identified by Roman numerals lA, lB, lC, lD, ll and ill. Since collector of transistor Oil is of the same conductivity type as the cathodes of diodes D2 and D3 and are commonly connected together electrically (see FIG. 2), they are formed in device islands IA, TB, IC, and ID. Since the high direct current potential commonly applied via contact area 54 to the anodes of Dll all of these diodes may be made in common island ll. Similarly, all transistors Q2 of the same conductivity type are formed in common island ill, and contact areas 53 apply the periodic voltage from generator portion 15 and terminal 511 of the direct current source 50 (FIG. 2) to the collectors C of all of these transistors.

Although other forms of integrated circuit fabrication may be used to structure the circuit, the dielectric isolation technique is preferred since at the present state of the art, this technique appears to provide the necessary isolation for the relatively high voltages which presently available gas discharge panels require.

The circuit affords a reduction in size, cost and power consumption and enables the output pulses to be equal to the DC power supply voltage which is common to all circuits of the same type to assure constancy and uniformity of voltage pulses. The two circuits (NPN and PNP) operate from two different floating high direct current voltage sources 50 and, when used with the sustaining generator portions l5 and 16, (FIG. 2), are connected to the outputs thereof at contact areas or terminals 53 and 54. Logic voltage pulse inputs to the circuits consist of low-level logic signals (2 volts in amplitude for example), referenced to the high-level direct current sources 50 (+V and -V, respectively), so the logic circuitry essentially will also float on the sustaining generator and the outputs are voltage pulses equal in amplitude to the voltage from sources S'll algebraically added to the sustaining voltage. By properly timing the times of occurrence of the low level logic pulse inputs, selected discharge sits may be turned ON or fired as by the voltages V at the selected site.

While the circuit is uniquely adapted for monolithic or integrated circuit fabrication, the circuit may be structured from individual components. Exemplary components are as follows: transistors Q1 and Q2; MM4002 (MOTOROLA) for PNP; transistors Q1 and Q2 MM3009 (MOTOROLA) for NPN; other components for both circuit R. 470 ohm, R2 1,000 ohm, R3 15,000 ohm, diodes D and D2 IN 3731 and diode D3 IN 643.

While the invention was made primarily for use with gas discharge devices it is apparent that the invention is applicable to other devices where low-level pulses are to be transformed to high-level pulses and algebraically added to a high-level periodic voltage. In addition, other forms of sustaining voltage (square wave, gated sine waves, etc.) may be applied to the panel via the circuit disclosed herein.

Although a preferred embodiment of the invention has been described in detail, it is to be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope thereof.

What is claimed is:

l. A system for driving a multiple discharge gas discharge device wherein a pair of transversely oriented conductor arrays are dielectrically isolated from a gas discharge medium between said pair of conductor arrays comprising, in combination,

at least a first monolithic semiconductor body processed to provide a plurality of resistive and PNP transistor circuit components connected by conductors to form a plurality of identical circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made,

at least a second monolithic semiconductor body processed to provide a plurality of resistive and NPN transistor circuit components connected by conductors to form a plurality of identical circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made,

each said circuit configuration including,

a pair of like conductivity type transistors switches connected such that one of said transistor switches is normally ON and the other said transistor switches is normally OFF,

one of said contact areas comprising a low-level pulse voltage input terrninal connected to the base of said normally OFF transistor to render said normally OFF transistor ON and said normally ON transistor OFF on appearance of a low-level pulse voltage at said one contact area,

a pair of said contact areas for applying a high-level periodic voltage to the collector of said normally ON transistor and to the emitter of said normally OFF transistor, and a high-level unidirectional voltage to the emitter of said normally OFF transistor, and

a final contact area constituting the output terminal from said circuit configuration,

means individually connecting each final contact area of circuit configurations having PNP transistor components to conductors in a first of said conductor arrays, respectively,

means individually connecting each final contact area of circuit configurations having N PN transistor components to conductors in the second of said conductor arrays, respectively,

a first source of high-level periodic voltage and means commonly connecting said first source of high-level periodic voltage to all of said pairs of contact areas on said first monolithic semiconductor body,

a second source of high-level periodic voltage opposite in phase to said first source of voltage high-level periodic voltage and means commonly connecting said second source of high-level periodic voltage to all of said pairs of contact areas on said second monolithic body,

a first source of high-level unidirectional voltage connected to all of said pairs of contact areas on said first monolithic body, and

a second source of high-level unidirectional voltage, and means for connecting said second source of high-level unidirectional voltage to all of said pairs of contact areas on said second monolithic body.

2. The invention defined in claim 1 wherein each said circuit configuration includes diode means formed in each said monolithic body and connected between said final contact area and a point in said circuit which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.

3. The invention defined in claim 1 wherein a resistive circuit component in each said circuit configuration is connected between the collector of said normally ON transistor and a point which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.

4. The invention defined in claim 2 wherein a resistive circuit component in each said circuit configuration is connected between the collector of said normally ON transistor and said point which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.

5. The invention defined in claim 1 wherein the transistor circuit components in each said monolithic semiconductor body are formed in dielectrically isolated device islands in the semiconductor body.

6. The invention defined in claim 4 wherein the transistors and diode means of said circuit configuration are formed in dielectrically isolated device islands in the semiconductor body.

7. The invention defined in claim 4 wherein each said circuit configuration includes further diode means for speeding the switching response of said transistors to a low-level input pulse voltage on said input terminal.

8. The invention defined in claim 7 wherein a resistive voltage divider is in each said circuit configuration is connected at one end to said low-level pulse voltage input terminal, at the intermediate point to the base electrode of said normally OFF transistor and at the opposite end to one of said pair of control areas for applying a high-level periodic voltage to said circuit.

9. An integrated circuit element for supplying sustaining voltages and discharge manipulating pulse voltages to one conductor in a gas discharge device in which transversely oriented conductor effecting discharges in the gas have dielectric charge-storage means for charges produced on discharge interposed between said conductors and the gas, comprising,

a monolithic semiconductor body processed to include a plurality of resistive and transistor circuit components connected by conductors in the circuit configuration described hereinafter including a plurality of contact areas through which connections to said circuit configuration are made,

said circuit configuration including a pair of like conductivi ty type transistor switches connected such that one of said transistor switches is normally ON and the other of said transistor switches is normally OFF and to reverse the conductive states of said transistor switches,

one of said contact areas comprising a low-level pulse voltage input terminal connected to the base of said normally OFF transistor to render said normally OFF transistor ON and said normally ON transistor OFF, on appearance of a low-level pulse voltage on said one contact area,

a pair of said contact areas for applying a high-level periodic voltage to the collector of said normally OFF transistor, respectively, and a highlevel unidirectional voltage to the emitter of said normally off transistor,

and a final contact area constituting the output terminal from said integrated circuit said final contact area being connected to said one conductor.

10. An integrated circuit element as defined in claim 9 wherein the transistor circuit components in said monolithic semiconductor body are formed in dielectrically isolated device islands in the semiconductor body.

ll. A circuit for convening a low-level pulse voltage to a high-level pulse voltage and algebraically combining said highlevel pulse voltage with a high-level periodic voltage comprising, in combination,

a pair of input terminals for connection to a low-impedance high-voltage level direct current voltage source,

an output terminal,

a normally nonconductive first transistor,

means connecting the emitter of said first transistor to one input terminal of said high-voltage level current voltage source,

diode means connecting the collector of said first transistor to said output terminal,

a resistance element connecting the other input terminal of said high-level direct current source to the collector of said first transistor,

means for applying said low-level pulse voltage to said first transistor to render said first transistor conductive and apply the high-voltage level direct current voltage from said source to said output terminal through said diode means,

a normally conductive second transistor,

means connecting the emitter of said second transistor to said output terminal,

means connecting the collector to said second transistor to the other input terminal for said high-voltage level direct current voltage source,

means connecting the base of said second transistor to the emitter of said first transistor whereby said normally conductive second transistor is rendered nonconductive on said first transistor being rendered conductive voltage to the base thereof,

a source of high-level periodic voltage, and

means for applying said high-level periodic voltage to the collector of said second transistor, whereby said highlevel periodic voltage is applied to said output terminal through said second transistor during the conduction times thereof and to said output terminal through said low-impedance high-voltage level direct current voltage source and said first transistor during conduction times of said first transistor.

l2. The invention defined in claim i ll wherein said circuit is one of a plurality of similar circuits on an integrated circuit chip.

113. The invention defined in claim 112 wherein said in tegratcd circuit chip contains a plurality of device islands dielectrically isolated from each other and in a common matrix.

lid. The invention defined in claim l3 wherein each normally conductive second transistor of each circuit is in its own device island and all of said normally nonconductive first transistors are in a common device island.

lid. An interface system for coupling low-voltage level information signals from an information source to traversely oriented insulated conductor arrays in a gas discharge display panel requiring oppositely phased high-voltage level pulse in formation signals and oppositely phased periodic sustaining voltages applied to and transversely oriented conductors for displaying the information comprising, in combination,

first integrated circuit means for translating low-voltage level information signals from said source to unidirectional high-voltage information signals and applying same to conductors of one conductor array, and

second integrated circuit means for translating low-voltage level information signals from said source to unidirectional, high-voltage level information signals and applying same to conductors of the conductor array transversely oriented with respect to said one conductor array,

a generator for generating a pair of oppositely phased periodic voltages,

means for applying one phase of said pair of periodic voltages to said first integrated circuit means and the other phase of said pair to said second integrated circuit means,

ill

each said integrated circuit means algebraically adding one of said oppositely phased unidirectional high-voltage levels produced thereby to the periodic voltage applied thereto, respectively, to thereby display information on said panel.

lid. The invention defined in claim 15 including a generator for generating a pair of oppositely phased periodic voltages,

means for applying one phase of said pair of periodic voltages to said first integrated circuit means and the other phase of said pair to said second integrated circuit means, each said integrated circuit means algebraically adding unidirectional high-voltage levels produced thereby to the periodic voltage applied thereto, respectively.

l7. A system for driving a multiple discharge gas discharge device wherein a pair of transversely oriented conductor arrays are dielectrically isolated from a thin gas discharge medium between said pair of conductor arrays comprising, in combination,

at least a first monolithic semiconductor body processed to provide a plurality of first resistive and transistor circuit components connected by conductors to form a plurality of identical but electrically isolated switching circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made,

at least a second monolithic semiconductor body processed to provide a plurality of second resistive and transistor circuit components connected by conductors to form a second plurality of identical but electrically isolated switching circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made,

each said circuit configuration including,

a pair of transistor switches connected such that one of said transistor switches is normally ON and the other said transistor switches is normally OFF,

one of said contact areas comprising a low-level pulse voltage input terminal connected to the base of said normally OFF transistor to render said normally OFF transistor 0N and said normally ON transistor OFF on appearance of a low-level pulse voltage at said one contact area,

a pair of said contact for applying a high-level periodic voltage to the collector of said normally ON transistor and to the emitter of said normally OFF transistor, and a highlevel unidirectional voltage to the emitter of said normally OFF transistor, and,

a final contact area constituting the output terminal from said circuit configuration,

means individually connecting each final contact area of said first circuit configuration on said first monolithic body to conductors in a first of said conductor arrays, respectively,

means individually connecting each final contact area of said second circuit configurations on said second monolithic body to conductors in the second of said conductor arrays, respectively,

a first source of high-level periodic voltage and means com monly connecting said first source of high-level periodic voltage to all of said pairs of contact areas on said first monolithic semiconductor body,

a second source of high-level periodic voltage opposite in phase to said first source of voltage high-level periodic voltage and means commonly connecting said second source of high-level periodic voltage to all of said pairs of contact areas on said second monolithic body,

a first source of high-level unidirectional voltage connected to all of said pairs of contact areas on said first monolithic body, and

a second source of high-level unidirectional voltage, and means for connecting said second source of highlevel unidirectional voltage to all of said pairs of contact areas on said second monolithic body.

ductors in circuit configurations described hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made,

each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low-level input pulse signal voltage to a high-level pulse signal voltage as said sustaining voltage, the output voltages from each circuit configuration being of opposite polarity, respectively.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3343128 *Jun 27, 1963Sep 19, 1967Gen Dynamics CorpElectroluminescent panel driver circuits
US3493812 *Apr 26, 1967Feb 3, 1970Rca CorpIntegrated thin film translators
US3522471 *Mar 19, 1968Aug 4, 1970Burroughs CorpTransistor driver circuits for cathode glow display tubes
Non-Patent Citations
Reference
1 *Solid State Electroluminescent Display and Scanning Apparatus R. S. Lynch IBM Publication Vol. 9 No. 12 May 1967, pp. 1799-1801 (copy in 340/166)
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3793628 *Sep 1, 1972Feb 19, 1974NcrElectroluminescent display device
US3851327 *Mar 29, 1973Nov 26, 1974Bell Telephone Labor IncLight pen detection for plasma display system using specially-timed erase pulse
US3869644 *Aug 16, 1973Mar 4, 1975Nippon Electric CoPulses of the same or an opposite polarity to electrodes of a plasma display panel
US3973253 *Jan 10, 1974Aug 3, 1976International Business Machines CorporationFloating addressing system for gas panel
US4570159 *Aug 9, 1982Feb 11, 1986International Business Machines Corporation"Selstain" integrated circuitry
US4591847 *Jun 21, 1973May 27, 1986International Business Machines CorporationMethod and apparatus for gas display panel
WO2004015666A1 *Jun 26, 2003Feb 19, 2004Koninkl Philips Electronics NvDriving a plasma display panel
Classifications
U.S. Classification345/60, 257/539, 315/169.4, 257/536, 327/484, 257/E27.13, 327/565, 345/204, 257/526, 257/E27.2
International ClassificationH01L27/06, H01L23/535, G09G3/28, G09G3/288
Cooperative ClassificationH01L27/0611, G09G3/296, H01L2924/3011, G09G3/297, H01L27/0652, H01L23/535
European ClassificationH01L23/535, G09G3/296, G09G3/297, H01L27/06D, H01L27/06D6T2
Legal Events
DateCodeEventDescription
Jun 9, 1987ASAssignment
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC., SEAGATE,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648
Effective date: 19870323
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC.,OHIO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648