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Publication numberUS3614766 A
Publication typeGrant
Publication dateOct 19, 1971
Filing dateJun 9, 1969
Priority dateJun 9, 1969
Also published asCA928823A1, DE2028344A1, DE2028344B2
Publication numberUS 3614766 A, US 3614766A, US-A-3614766, US3614766 A, US3614766A
InventorsKievit James M
Original AssigneeDick Co Ab
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Display device including roll and crawl capabilities
US 3614766 A
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Description  (OCR text may contain errors)

IJIIII States Inventor Appl. No. Filed Patented Assignee aterII DISPLAY DEVICE INCLUDING ROLL AND CIRAWL CAPABILITIES 27 Claims, 21 Drawing Figs.

US. Cl 340/324 A, 3 15/22 [56] References Cited UNITED STATES PATENTS 3,406,387 10/1968 Werme 340/324 A 3,422,420 1/1969 Clark 340/324 A Primary ExaminerJohn W. Caldwell Assistant Examiner-David L. Traftom Attorneys-Samuel Lindenberg and Arthur Freilich COMP $YNC, HOTZ1Z SYNC, EXTERNAL syNc I SYNC. COMP $PARATOR VERT svNc. 57

SIGNAL vm O VIDEO 2.2 56 I 5OMRCE BIANK 1 lcuRsoR t e0 cuRgoR ON/OFF GLN. I



ATTORNEYS PATENTEBum 19ml 3,81 41,766


KEY TO 250 We 9 B FASTQRAWL KEY 260 z a smvv ROLL RANGE I=r W V ,zoo

ROLL KEY 320 QRAWL KEY mung. CMR 35o UNE eTED w" mm VR V SYNC, 526 WIROM Wfi we 5 35g 9?; PRW H6 2&4

6 2&6: I J 5 FF W 05 W 2&8 TO 294 M HG QB H SYNC, 290 p---- R P. I m/y A/rw? CLOCK CLAMD 292 JAMES 44. May/77 tROM T36 33 J;

DISPLAY DEVICE INCLUDING ROlLlL AND CRAWIL CAPABILITIES BACKGROUND OF THE INVENTION functions at frequencies such as those used in home television 1 receivers, and displays data, which is entered into this system, either by means of a keyboard or tape, which are received over a wire. The display system has a storage facility into which the incoming data is entered. The data is thereafter read out, decoded, converted into signals which can be displayed and thereafter displayed.

This invention relates to display apparatus which functions to produce the appearance of lines of data being displayed moving upward from the bottom towards the top of a display tube. Apparatus is also provided for producing the effect of characters of being displayed, the data moving in lines from the right to the left across the face of the display tube.

A feature of this invention is the provision of a display system which operates at frequencies used in home television receivers and affords the ability to display information moving in lines vertically across the face of the display tube, or characters moving in lines from right to left across the face of the display tube.

Another feature of this invention is the ability to effectuate such motion of the data, smoothly and at different rates.

In accordance with this invention, data is called out of a memory to be displayed from an address which is provided by a line display counter and a character display counter. Means are provided, when it is desired to roll the data upward, to increase the count of the line counter by one, at the end of a predetermined time whereby the data appears to be moving upwardly.

Where it is desired that the data perform a character crawl operation, then at the end of a line of data which is displayed, the character counter has its residual count incremented by one rather than being reset to zero, whereby a character which, ordinarily for example is at the end of the line which is displayed, successively is displayed in positions from the right side to the left side of the line.

Other features are provided for ensuring the proper blanking, avoiding a jumping" of the data, and also providing for the display of new or incoming information while in the roll or crawl mode of operation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram illustrating the general layout of a display system wherein this invention is employed.

FIG. 2 is a detailed block diagram of a display control unit which is employed herein.

FIG. 3 is a block schematic diagram of the display counter control circuit 32.

FIG. 4 is a block schematic drawing of the X and Y-matrix counters.

FIG. 5 illustrates a character constructed at selected dots in a dot matrix in accordance with this invention.

FIG. 6 is a block schematic of the display line and character counters.

FIG. 7 is a block schematic diagram of the cursor generator and line character counters.

FIG. d is a block schematic diagram of the memory address generator.

FIGS. 9A, 9B and 9C and 9D constitute block schematic diagram of the roll and crawl circuits in accordance with this invention.

FIGS. 10 and II are schematic diagrams of logic circuits used in the invention.

FIG. 12 is a block schematic diagram of roll and crawl loading logic.

FIG. 13 is a block schematic diagram of another arrangement for achieving roll and crawl.

FIG. M is a waveform diagram shown to assist in an understanding of this invention.

FIG. 15 is a block schematic diagram of a circuit used for generating logic signals used in the invention.

FIG. 16 is a block schematic of logic circuits used to generate the address-incrementing pulse.

FIG. 17 is a block schematic diagram of a circuit used to generate extra pulses for smoothing the roll operator.

FIG. 18 is a block schematic circuit of a blanking signal generator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The descriptions of FIGS. 1 through 8 are substantially identical with the descriptions of FIGS. 11 through 8 found in the previously indicated application for the display system by Martin Kite et al. This description is. being repeated here in order to afford a better understanding of the invention.

Referring now to FIG. 1, a general arrangement in accordance with this invention would comprise a standard TV monitor 10, (more than one may be used if required,) which displays human readable data. Digital data may be entered into the system from any data source, illustrative of which there is shown a tape reader 112 and/or a typewriter keyboard M. This data is fed into a display control unit 16 whose function it is to store the data in a manner so that it may be properly read out for display on the TV monitor or sent to some other utilization device 18, such as keypunch, a printout device, etc. The display control unit also includes a novel character generator which, in response to the data representative code produces the video signals which are displayed as readable data on the TV monitor 10.

FIG. 2 is a block schematic diagram illustrating details of the display control unit. A tape reader 12 or a typewriter keyboard M are well known, and commercially available pieces of hardware. For the purposes of this invention, and in the manner that they function normally, the tape reader produces as an output eight binary signals together with a strobe pulse, each time a character is read out. Seven of the eight bits represent an alphanumeric character. The eighth bit is parity. The keyboard M, which can be a facsimile typewriter, also produces at its output sevenbit character signals with an eighth bit having parity significance, together with strobe pulse. In each of these cases, the signals are produced in parallel on eight data lines and a strobe pulse is produced on a ninth line. The signals are applied to interface circuits 60.

Basic operating synchronization signals for the display control unit may be obtained from an external source of sync signals 16. This external sync signal source may comprise either a television station sync generator, or a composite video signal such as may be obtained from a videotape device. Signals from either of these may be processed to provide horizontal sync signals and vertical sync signals. If composite video is provided, this is applied directly to an OR-gate 18 the output of which goes to a sync separator circuit 22. This functions in well-known manner to separate the horizontal sync from the vertical sync. If composite video is provided by the external video signal source, then this is applied to a video blanking circuit 20, which constitutes well-known circuitry for applying a blanking pulse to the composite video during the video interval. This leaves composite sync signals. These are applied to the OR-gate l8 and thereafter to the sync separator circuit to be separated into horizontal and vertical sync signals.

The composite sync signals, which are the output of the OR- gate 18 are supplied, at the output of the display control unit, to the TV monitor which is used to reproduce the video signals. The vertical sync or vertical drive pulse which is the output of the sync separator 22 is used to reset a display character counter 24, and a display line counter 26, to assure that each field which is to be displayed starts properly. The display character counter has its count advanced by one for each character being displayed on a line of characters. The

display line counter 26 has its count advanced by one for each line of characters which is displayed. Thus, the address of the last character being displayed is always available from the output of these counters. Actual video display commences after the first 24 horizontal sync pulses which follow the vertical sync pulse and continues until 16 rows of character video are displayed.

There are 24 characters on each line. The first horizontal sync pulse initiates the operation of a display counter control circuit 32. The counter control circuit can start a gated clock circuit 28 where frequency equals the picture element rate of 8 megacycles. The start of the operation of the gated clock is delayed, following the horizontal drive pulse, by approximately l2 microseconds until the first character position in a line of characters is reached. The clock turns on and then continues to operate until the final character in a line is completed. Each character position is defined by a dot matrix in which only those dots are illuminated which form a desired character. Each character uses nine dot positions along a line for the actual character display plus five guard band positions. The total number of clock pulses generated per line is therefore 14 times 24 (24 characters per line) or 336 pulses. The clock is turned off by a clock clamp pulse at the end of a line and is turned on again at the beginning of the next line.

The display counter control also receives vertical sync pulses which are used for reset purposes. The gated clock output is used to drive an X-matrix counter 34, causing it to count through 14 counts, nine counts of which correspond to nine horizontal positions in a character dot matrix starting from left to right, and the three further counts provide for the guard band or character spacing. The X-matrix counter 34 therefore goes through a full cycle of operation for each character. Count output signals from fi to )4'1'2' are derived therefrom. Each time the X-matrix counter completes a cycle of 12 counts, it overflows. lts overflow is applied to the display character counter 24 to cause it to advance one count. The display character counter has a count capacity totaling 24, corresponding to the number of characters displayed in each row. Each time the display character counter overflows, it sends the overflow pulse back to the display counter control 32 which in turn uses this overflow pulse, also termed a clock clamp pulse, to turn off the gated clock 28. The gated clock then waits for the next horizontal sync pulse before commencing operation again. The overflow output pulse of the display counter control also enables a Y-matrix counter 36 to be advanced one count in response to the next horizontal sync pulse.

The Y-matrix counter has a total count capacity of 14 counts. Eleven of these are used to count the vertical dot matrix locations of a character. Three of these are for a guard band space between lines of characters. Count outputs designated from W to Y l4 are derived therefrom. The overflow output of the Y-matrix counter 36 is applied to the display line counter 26 to cause it to advance one count. The display line counter has a total count capacity of 16 corresponding to the 16 lines of characters which are displayed in one field of this invention.

A character generator 38 is provided which has applied thereto the count outputs of the X- and Y-matrix counters. In response to these, the character generator generates video signals representing each one of the alphanumeric characters which the system is capable of displaying. In an embodiment of the invention which has been built and successfully operated, the character generated created 64 alphanumeric characters. The output of the character generator is applied to the video selector 30. This functions to select, in response to a seven-bit alphanumeric code derived from the core memory 40 of the system, a specific character from all of those being applied to the video selector, which character is represented by that alphanumeric code. More specifically, the core memory 40 supplies coded signals, one character at a time to an output register 42, which in turn applies them to a data decoder 44 which decodes them successively and enables the video selector to select the proper video character signals. In addition, the video selector 30 is capable of being modulated by a flash control circuit 46. The flash control circuit contains an oscillating circuit that may be turned on by a flash code which is stored in the memory and which is a nonviewable" character. The flash control 46 remains on until either the next following horizontal drive pulse appears or a space code which separates the following word appears. Operation of the flash control 46 causes all characters of a word that are displayed thereafter to flicker and thus call attention to itself.

After each character is displayed, an unload cycle of the core memory 40 is made to occur to place the alphanumeric signals corresponding to the next character of a row in the output register 42. The address from which the character in core memory is read is provided by the count conditions of the display character counter and display line counter. A specific core memory address is provided for each of the 384 counts which these counters provide. The display character counter 64 and display line counter 66 have their outputs connected to a memory address generator 67, which produces the address information for the core memory 40.

The output of the video selector 30, which comprises the character video signals, is applied to a mixer circuit 50 and to an output terminal 52. The mixer circuit combines character video signals with a cursor signal which is provided from a cursor generator 54. The cursor video signal has approximately one-half of the intensity of the character signals. The cursor video signal indicates, on the pattern displayed on the face of the television monitor, the corresponding character signal address in the memory into which the next input character digital signals will be placed when the system is in the write mode. The mixer output is applied to an output terminal 55. In addition, composite sync signals from the output of the OR- gate 18 are made available at a terminal 56. These three signals, namely composite sync, character video with cursor, and character video without cursor, are thus available at the three output terminals for being applied to a television monitor for display.

The tape reader 12 and the keyboard 14 have their outputs connected to the interface circuitry 60, The interface circuitry serves to check the incoming data lines from either of the two inputs upon receipt of its associated data strobe presented on the strobe lines. If the data is alphanumeric data to be displayed, the input strobe signal triggers a single load cycle of the core memory. This function is provided by the data input control circuit 62. In the load cycle operation, the input character is loaded into the core memory at an address which is determined by the count outputs of the cursor character counter 64 and the cursor line counter 66. The cursor generator 54 detects coincidence between the cursor counters and the display counters and causes the load operation to occur when these counters have the same count. As previously indicated, this occurs at an address in memory corresponding to the position visually indicated by the cursor on the output monitor. Thus, the load operation into the core memory occurs at a location which corresponds to the location of the cursor. From the foregoing it will be appreciated that the memory should provide storage for 512 alphanumeric characters of eight bits per character.

Other signals from the interface circuit are provided in response to the incoming control codes. These specific control codes do not result in a memory load cycle but rather generate signals on appropriate lines out of the interface circuit. These lines perform such functions as cursor on-off, cursor right, cursor left, cursor new line, cursor home, cursor up, cursor down, etc. This will become more clear as this explanation progresses.

During the write mode, as each character is loaded into the core memory, a single pulse advances the cursor character counter by one count. When the cursor character counter overflows, its output advances the cursor line counter. lnput load operations therefore, cause the cursor to be advanced character by character and line by line in a manner similar to the typing operation of a typewriter.

The output register 42 may also be used if desired to transmit data which is within the memory to an external utilization device 19 such as tape or a transmitter or an external printer. An end of line" or end of message" circuit 69 driven by the cursor counters, may be used in conjunction with external transmission of data to signal their occurrences to external equipment.

DlSlPlLAY COUNTER CONTROL ClRCUlT 32 H6. 3 is a bloclt schematic diagram of the display counter control circuit. This circuit arrangement functions to initiate operation of the gated clock oscillator at the proper time so that the subsequent matrix and display counters may commence to operate at the proper time and in the proper time sequence. In a television-type display both a top margin as well as a left side margin must be provided for. Essentially the display counter control circuit provides for these delays. The first vertical sync pulse which is delivered by the output of the sync separator 22 is applied to a flip-flop 102 to drive it to its set state. This causes the Q output of the flip-flop to become high. The Q output of the flip-flop enables an AND-gate lltMl whereby it can pass horizontal sync pulses which are received from the sync separator. These are applied to drive a 24-count counter 166. This counter provides a top margin delay. The 24th count of the counter is used to reset the flip-flop 1102 and sets a flip-flop 1166. The next vertical sync pulse enables flipflop W2 again and simultaneously resets the 24-count counter so it can begin counting again.

The Q output of flip-flop 106 enables an AND-gate 110 to pass horizontal sync pulses. The output of the AND-gate 11116 is applied to a delay circuit M2. The delay circuit provides a delay whose duration is determined by the size of the desired left-hand margin on the display tube. The output of delay cir cuit 1112 sets a flip-flop 1114. The Q output of the flip-flop 11114, which is high in response to its set input being enabled, is applied to the gated clock oscillator to cause it to commence to produce clock pulses.

Flip-flop 11114 is reset by a B16 output, also called a clock clamp pulse, which is received from the display character counter which counts the number of characters displayed on a line. After the last character has been displayed flip-flop 1114 is reset so that at the commencement of the next line, signaled by the appearance of another horizontal sync pulse, a delay is provided on the left-hand side of the display tube. The flipflop 108 is reset by a W signal which is provided by the display line counter. This signal occurs after the last character on the last line has been displayed. Accordingly, flip-flop 1108 cannot be set again until the counter W6 counted through its next 24 counts to provide the top margin delay.

X- AND Y-MATRIX COUNTERS (Mr-36) FIG. 6 is a block schematic diagram of the X- and Y-dot matrix counters. A character, in accordance with this invention, is made by illuminating selected dots in a dot matrix that extends nine dots in a horizontal direction and eleven dots in a vertical direction. There are five dot spaces allowed between characters on a line to serve as a guard band, and three dot spaces between lines of characters, also to serve as a guard band. Thus, the counter that counts for the horizontal dot placement will have a count capacity of i4 and the counter that counts for the vertical dot placement will have a count capacity of 14.

In FIG. 4, there is shown a horizontal counter 1116 which is made up of six flip-flops, respectively 1116A through llll6F. Each one of these flip-flops is of the type known as Jli flipflop. it is well known and commercially purchasable.

Each flip-flop has J, K and C inputs, and Q and Q outputs. When a clock pulse is applied to its C input the flip-flop will transfer to its outputs the state of its J and ii inputs. Thus, if the J input is high and the K input is low when a C or clock pulse is applied to the C input, the Q output will be high and the Q output will be low. The J and it inputs are applied to the respective flip-flops from the Q and Q outputs of the respective flip-flops through NAND gates. A NAND gate behaves like an AND gate followed by an inverter. Accordingly, when the two inputs to the NAND gate are high, its output is low and when the inputs to the NAND gate are low, its output is high. When one of the inputs is high and the other is low, the NAND gate output is high.

The counter llll6 has the Q and Q outputs of the respective flip-flops 116A through 1116B respectively connected to the J and K inputs of the immediately following flip-flops through the respective NAND-gates 117A and 117A through 1111715 and H713. NAND-gates 1116A and 116A are connected to the respective J and K inputs of flip-flop 1116A. The NAND- gate 1 WA has one input connected to the 6 output of flip-flop l1l6F which is designated as H 6. The NAND-gate 1116 has its inputs respectively connected to the Q outputs of respective flip-flops M612 and lll6F. These Q outputs are respectively designated as H5 and H6.

It should be noted that whenever a designation is shown for only one NAND gate input, the other input of the NAND gate is connected to a bias source 1120. As the result, a one-input NAND gate acts as an inverter to invert the input.

The respective Q and Q outputs of flip-flops llll6A through lll6F are respectively designated as Hll through H6 and FF through H6. These are collected by the 112 NAND gates, respectively 1121 through 1135, to provide 14 output count indications in their not form. These are designated by X ll through m. Thus, upon the occurrence of an HR and m input to NAND-gate 1211, it will produce an output designated as m, which is the first output count of the counter. H6 and H7 occurring at the input of NAND-gate 126 produce an Y6 output, m and H6 occurring simultaneously at the input of NAND- gate 132 produces an Yf'output or a not 12 count output.

The manner in which the counter H6 functions is for each one of the flip-flops to successively assume its one state or state with its Q output high and thereafter each flip-flop successively returns to the state with its 6 output high. The counter is cyclic and will repeat this operation in response to successive applications or clock pulses from the gated clock oscillator 134. This oscillator comprises a circuit which, in the presence of an enabling input from flip-flop lid in FIG. 3, provides successive clock pulses to the: counter H6.

To illustrate how the counter works, assume initially that all the flip-flop stages are in their zero state. The Q output of flipfiop llll6F is high. Upon the occurrence of the first clock pulse from the gated clock oscillator 1M, flip-flop 116A will be driven to its one state with its Q output high, since itsJ input is now high and its l( input is low. Upon the occurrence of the next clock pulse, flip-flop 116B assumes a one state. This progresses with successive clock pulses until flip-flop ll6F assumes its one state. Since, the K input to flip-flop lll6A is driven to its high state in response to H6 and H5 which are connected to the NAND-gate 118A being high, flip-flop ll6A is driven to its zero state with its 6 output high. This zero state of the counter lllfiA is successively passed with the occurrence of each clock pulse to all of the flip-flops in the counter. From an understanding of the operation of this counter, it should now be understood how the inputs to the NAND-gates 1211 through 132 operate to produce the indicated count outputs.

Counter M0 is identical in construction with counter 116. Accordingly, it can produce 14 count outputs. It advances in respect to pulses obtained from the output of gate in FIG. 3. These are essentially horizontal sync pulses. The NAND- gates Mil through 1 .50 are connected to the flip-flop outputs for the purpose of deriving the respective counts one through 14 which are in their not" form. The Q and Q outputs of the respective flip-flops of the counter M6 are respectively designated from V11 through V7 and from VT to W. The counter Hill, which counts for the vertical dot positions, is given a count capacity of 14 counts. Since it is customary to reference the bottom line of a character as a first position and the top of a character as the last position, assuming each location or position ofa line were given a number, the bottom ofa character would be considered in the Y1 location and the top would be considered in the Yll location. Therefore, while the present invention displays a character .in television raster form, where the top of the character appears first and the bottom last, the count output of the Y-matrix counter is given a reverse count designation. That is, the first count of the counter is designated as W, the 1 l-count of the counter is designated as H, W and W, which are generated when all of the stages of the counter are in their zero state, are combined to produce a Yl4 count. The reasoning for this arrangement will become more clear with a description of FIG. 5.

FIG. 4 shows how pulse signals Y1 through W and Ti through W and W are generated. In addition to these signals, other logic signals are required for the operation of this invention. Thus, in FIG. 4, a NAND-gate 152 is used to collect m, W, m, m and W together with the Q output of a flip-flop 154. The Q output of the flip-flop 154 is enabled when a W signal is applied to its clock input. The flipflop remains set until the occurrence of a m signal (Y5 and Y6). This is produced when counter 140 provides a W and W output to a NAND-gate 156. Thus, flip-flop 154 is set at the end of a counting cycle of counter 140 and is reset upon the occurrence of the l2th count output of the flip-flop 140. The output of NAND-gate 152 is inverted by NAND-gate 158 to produce a signal designated as PPl. The E of not 12 count of the counter 116 is inverted by a NAND-gate 160 to produce an X12 count.

EXAMPLE OF A DOT MATRIX CHARACTER FIG. 5 shows the appearance of a character, A, constructed to selected dots in a dot matrix in accordance with this invention, with the appropriate designations applied to the possible dot locations which may be used for representing a character. There may be as many as 32 of these characters displayed in a line across the face of the display tube. There may be as many as l6 of these lines displayed vertically. These values are given by way of illustration of an operative embodiment of the invention which has been built, and are not to be construed as a limitation upon the invention.

DISPLAY LINE COUNTER AND DISPLAY CHARACTER COUNTER The display line counter and the display character counter (FIG. 6) respectively 26 and 24 are each the usual binary counters with respective count capacities of 16 and 32. Each time an 766 signal is generated by the X-matrix counter 34, the display character counter is advanced one count. Each time a W signal is generated by the Y-matrix counter 36, the display line counter is advanced one count. The display character counter has its respective outputs designated Bl, El, B2, E, through B16, 8 16. The display line counter has its outputs designated as Wl, WT, W2, 72, W8, W 8. The character counter is the one which keeps track of the number of characters on a line, for which 24 are allowed. The E16 output of the character counter, referring back to FIG. 3, is the output which turns off the gated clock oscillator. This occurs when the last character in a line has been displayed. The last output of the display line counter, which is designated as W, is the one which turns off flip-flop 108 in FIG. 3. This occurs at the end of the last line which is displayed.


The cursor Xcounter 64, as shown in FIG. 7, is a reversible counter having any of the well-known reversible counter constructions. Its 32 outputs are respectively designated at A1, A1, through A16, KY6. This counter is advanced by receiving a signal from whatever external data input device is employed. A signal for advancing the counter is supplied with each character when the display control'is is in its write mode. Such a signal is supplied from the typewriter to the cursor right" input of the counter. The counter may be made to count in reverse by receiving an input signal on its "cursor left" terminal, from the typewriter keyboard. The cursor signal, which by way of example has been indicated as a background display of half intensity for a character, will occur at the proper time, at a location along a line determined by the count output or by the address represented by the count output of counter 64.

A cursor Y-counter, which is similar in construction and operation to the cursor X-counter, has a l'6-count capacity and is also reversible. This counter is advanced by signals from the keyboard applied to its cursor down terminal and is caused to count backwards in response to pulses received which are applied to its cursor up terminal. This counter establishes, by its output, the line address on which the cursor signal is displayed. The output of this counter is designated by Z1, ii to 28,3, with the Z8 signal being the l6th or highest count output of the counter.

The cursor is displayed only when there is a concurrence in the address indicated by the cursor counters and the display counters. To achieve this operation, a comparator circuit 162 compares the address outputs of the counter 64 and the counter 24, shown in FIG. 6, and when there is an identity it provides an output signal to a NAND-gate 164. Another input to this NAND gate is the PPl signal which is generated by the logic shown in FIG. 4. This PPl signal, in view of the presence of the inverter 158, (in FIG. 4), is present from in through X 9 time. From m through W time, the PPI signal is not present and no output is obtained from NAND-gate I64. Upon the occurrence of a comparator signal and a PP] signal, a JK flip-flop 166 is driven so that its Q ou tp ut is high. This flip-flop is reset upon the occurrence of an X10 signal.

The occurrence of the cursor on a particular line is determined by the output of a comparator 170. This comparator compares the address provided by the output counts of the cursor counter 66 and the display line counter 26. The output of the Y-comparator is applied to the NAND-gate 168. The typewriter keyboard 14 will have a key which can be operated to actuate a circuit which can provide a voltage to a third input to the NAND-gate 168 designated as the cursor on-off" input. When this voltage is not present, no cursor is provided. This circuit is shown subsequently herein in FIG. 18.

Therefore, NAND-gate 168 functions to provide a cursor signal output when there is a concurrence in the addresses at the outputs of the cursor X- and Y-counters and the display character and line counters. Since the display counters are sequenced continuously through their count states, there will be concurrence of cursor and character counters only at one location over the entire face of the display tube. Accordingly, the cursor will be displayed at one character location only.

The memory storage device which is employed with this embodiment of the invention should be able to store, for readout onto the face of a display tube, as many characters as will be displayed across the face of the tube. The example given by way of illustration herein is 24x16 or 384 characters, or more correctly the code bits to represent 384 characters. Thus a total of at least 8X384 or 3,072 bits is required. There should be a character location in the memory which corresponds to the location on the display tube face at which that character is to be displayed. The memory must be addressed successively for the purpose of successively reading out the characters for display. The successive addressing of the memory is a function of the display counters.

The address of a location in the memory into which data is to be entered is indicated by the address of the cursor. This address can be changed by applying signals to the cursor counters which establish the line and the location along the line desired for the cursor, and thereby the location in the memory into which data will be introduced. The cursor counters may be advanced by actuation of the typewriter keyboard in a normal manner for the purpose of writing character by character into the memory. Provision may also be made for advancing the cursor counters when input of characters is from a tape reader or any other source.

MEMORY ADDRESS GENERATOR 157 FIG. 9 is a schematic representation of a memory address generator. By way of illustration, and not to serve as a limitation, a magnetic core memory was employed with an embodiment of this invention which was built and operated.

The memory address generator addresses the memory for the purpose of reading out the data stored therein which is converted into video signals and then displayed. The address generator also provides the address of the locations into which incoming data is stored. The display character and line counters provide the address information for instructing the memory as to the location from which readout is to occur. The cursor X- and Y-counters provide the address information for instructing the memory as to the location at which data is to be entered.

As may be seen in FIG. 6, the memory address generator merely comprises a number of gates which are connected to the outputs of the respective display and cursor counters. The set of gates connected to the display counters are enabled during the process of readout whereby the address presented to the memory is that indicated by the display counters. Altematively, the gates connected to the cursor counter are enabled when write operation is desired. The outputs from the flipflops making up the display character counter 2 1 are respectively applied to each one of the NAND-gates 171 through 175. It should be remembered that the counter 24 is a binary counter and its output presents a pulse pattern in binary code representative of one of its 32 counts. The inputs to these NAND gates are designated by the terminology B1, B2, 1841, B9 and 1316, which corresponds to the outputs shown for the counter 241 in FIG. 6. Similarly, the W1, W2, W1 and W9 outputs of the line counter 26 are respectively applied to the NAND-gates 176, 177, 178 and 179.

The five outputs of the cursor character counter 64 are respectively applied to the respective NAND-gates 1110, 191, 1112, 183 and 1841. The outputs of the cursor line counter 66 are respectively applied to the respective NAND-gates 195, 1315, 187 and 198. NAND-gate 199 receives the output of NAND gates 171 and 1M). NAND-gate 191) receives the output of NAND-gates 172 and 191. NAND-gate 191 receives the output of NAND-gates 1113, 182. NAND-gate 192 receives the outputs of NAND-gates 174 and 1113. NAND-gate 193 receives the outputs of NAND-gates 175 and 1M. NAND- gate 194 has applied to it the outputs of NAND-gates 176 and 185. NAND-gate 195 receives the outputs of NAND-gates 177 and 1%. NAND-gate 196 receives the outputs of NAND- gates 179 and 187. NAND-gate 197 receives the outputs of NAND-gates 179 and 198.

An inverter 199 receives a signal from a read-write signal source 199 which is actuated by the typewriter keyboard or other input data source, when it is desired to write. Otherwise, and normally, a low signal is received from the read-write signal source. Accordingly, the output of inverter 199 is high when in the read mode and is low when in the write mode. The output of inverter 199 is applied to an inverter 201 as well as to all of the NAND-gates 171 through 179. The output of inverter 201 is applied to all of the NAND-gates 1911 through 1%.

In the read mode, the output of inverter 199 is high whereby the NAND-gates 171 through 179 are all enabled. The high input to inverter 201 results in a low output whereby NAND- gates 130 through 188 are not enabled. Thus, the outputs of NAND-gates 189 through 197 will be the outputs of NAND- gates 171 through 179 or the address data from the display counters. in the WRITE mode of operation, a high signal is applied to the input ofinverter 199. This is inverted, thus holding NAND-gates 171 through 179 disabled. However, the inverter 201 will provide a high or enabling input to the NAND-gates 181) through 198. As a result the NAND-gates 1119 through 197 will provide an address to the memory which constitutes the count outputs of the two cursor counters.

SUMMARY OF ROLL OPERATKON In the vertical roll operation the data displayed on the face of the cathode-ray tube appears to roll upward as new information is entered from the bottom. The top and bottom character row positions are blanked out giving the effect of rows of data appearing gradually from behind a mask at the bottom and gradually disappearing behind a mask at the top. New data is written into memory during the time the address of data would be displayed in the area that is blanked. Provision is made for several roll speeds. Choice of speed depends on capabilities of the data source which feeds new data to be displayed and visual effect desired.

The circuitry provided achieves the indicated effects by blanking the first and last line positions on the display tube, and by periodically incrementing the count of the display character counter by one before the commencement of the first line to be displayed in the succeeding field. In order to avoid the appearance of jumping, provision is also made for delaying the start of the first line to be displayed by intervals ranging for the interval of 14 horizontal sync pulses, down to one sync-pulse interval, and thereafter repeating the cycle from 14 to one again. The speed of display is handled by varying the rate of change of the amount that the first line of display is delayed.

HORIZONTAL CRAWL in horizontal crawl a single row of characters may be made to appear from the right side of the screen and crawl gradually across the screen from right to left, disappearing at the left. The extreme leftand right-hand character column position are blanked producing a curtain, from which characters appear from the right and into which they disappear on the left. New data is entered during a time a memory address would be displayed in the blanked area. Provision is made for three crawl speeds, choice depending on the capabilities of the data source and the visual effect desired.

The accomplishment of the crawl is done in a somewhat similar manner to the accomplishment of the roll. The character display counter which establishes the address in the memory from which a readout occurs has its starting count incremented by one periodically before the beginning of the display of the first line in a field. Provision is made for delaying the start of a line, first 14 clock pulses, then 13, etc. and down to one, and then starting back at 14 again. Crawl speed may be varied by changing the rate at which the delay is changed.

ROLL OPERATION Referring now to FIGS. 9A, 9B, 9C and 90, there may be seen block schematic diagrams of the apparatus for forming the roll and crawl operation.

In order to initiate operation, a roll key 200 is depressed at the typewriter keyboard. Also, either a slow roll key 202, a slow range key 203, or a fast roll key 204, may be depressed as determined by the speed of the roll desired. When none of these keys is depressed, the roll speed is between that of slow and fast roll. Depressing the roll key 200 causes a flip-flop 206 to be set, upon the occurrence of the next vertical sync pulse, (It E1), which is applied to its clock input terminal. When it is no longer desired to have the roll operation, the roll key is opened. An inverter 209, which is connected to the reset input of the flip-flop 206, applies an input such that flip-flop 206 will be reset at the next vertical sync pulse.

When flip-flop 206 is set, its output is applied first to an inverter 210, whose output provides a W DC level, then directly to an output terminal whose output provides a VR DC level, and then to a NAND-gate 214, which causes its output to go from low to high, indicative of either VR of HC (horizontal crawl).

In the vertical roll mode, as well as in the horizontal crawl mode, since the line and character display counters 26 and 24 will be operated in a manner so that they are not reset and at the beginning of each successive display field the counters will not have a beginning count, in order to provide the necessary we and W signals to the flip-flop 108 and 114, shown in FIG. 3, a substitute row and column counter 216 is employed. When in the roll mode, the output of this counter is provided when it attains the count of 16. When in the crawl mode, the output of this counter is used when it attains the count of 24.

When the VR signal goes high, then a NAND-gate 218 can apply pulses, designated as W, to drive the substitute Row 1 column counter 216. The W4 pulses are derived from a oneshot circuit 220 which is driven in response to W pulses. It will be recalled that the Y 14 pulses are derived from the output of the Y-character matrix counter.

The substitute row-column counter 216, when it reaches the count of 16, provides an output to an AND-gate 222. This AND gate has as its second required input the VR output of the flip-flop 206. It will be noted that another AND-gate 224 is blocked at this time, since one of its required inputs W is low. The other input to this AND-gate 224 is the regular W 8 output from the display line counter 26. Therefore, when the system is not in the roll mode, the W6 output causes an output from the AND gate which is connected to an OR-gate 226. The AND-gate 222 is also connected to this OR-gate 226. The output of the OR gate is a W signal. This is the signal which is applied to flip-flop 108 to cause it to reset whereby the gated clock oscillator, which drives the X-counter 1 16 is terminated, and horizontal sync pulses are no longer applied to advance the Y-counter 140.

From the foregoing, it should be appreciated why the counter 216 is designated as a substitute row-column counter. In the roll mode, or in the crawl mode, as will be seen later, its output is substituted for the line counter or the character counter for the purpose of keeping track of the number of lines or characters which have been displayed, but not for the purpose of addressing the memory for readout.

Referring back to the one-shot 220, it will be seen that its output Y l4* is also applied to an AND-gate 230. Another input to this gate is VR. The third required input to this gate, which enables it to apply a pulse to the display line counter, increasing its count by one, is an RS2 pulse. The output of gate 230 to the display line counter is in addition to the regular flow of Yl4 pulses which advance the counter count by 16. It occurs each time an RS2 signal occurs and causes the roll effect. How the RS2 signal is derived will be described subsequently. At this point it should suffice to state that an RS2 pulse is generated immediately upon going into a roll or a crawl mode of operation, and also after predetermined intervals as determined by the roll or crawl speed selected.

Aside from the time the RS2 pulse is provided, the display line counter advances in its normal manner in response to the W pulses. Accordingly, at the end of a predetermined number of display fields in the roll mode, the display line counter ends up with a one count. Another count is added by the application of a W" pulse. Thus, at the beginning of the next display field, the third line of data in the register will be displayed. After the next predetermined number of display fields have occurred, another WP pulse is applied to the counter and the fourth data line in the memory will be shown at the top of the display field.

The foregoing operation gives the displayed data the appearance of rolling upward across the face of the display tube. The substitute row-column counter 216 provides the necessary Wi" pulse at the end of the l6th display line which is applied to the clock control in FIG. 3, at the right time, despite the face that the regular display line counter provides the W8 pulses at the wrong time.

Blanking signals for blanking out the top and bottom lines is provided by structure which will be described subsequently herein.

From the structure described thus far, while the roll effect is provided, it is not very smooth and gives the appearance of jumping up the space by one line. The roll effect can be made much smoother by dividing up the increment of one line into smaller increments of motion. That is, by starting the top line being displayed down the distance of l4 scan lines with the rest of the display following thereafter, then displaying the next top line for the next display 13 scan lines, then 12, etc., returning again to 14 after there has been a one-scan-line delay, the roll mode of display is made smooth.

This operation is achieved by inhibiting a certain number of clock pulses from the Y-counter, and gradually decreasing the number of clock pulses withheld from the Y-counter for each field being displayed, in the manner previously described.

Now if the clock pulses are withheld from the Y-counter for the interval required for 14 scan lines to occur, the display that would follow would be displaced down by 14 scan lines or one row and the data that would be displayed at that time would be the line of data that would otherwise have been displayed in the preceding row. However, the W pulse adds a count to the counter to ensure that the line displayed is the proper one. The line that would have been displayed is now the bottom line and does not appear.

The indicated delay of clock pulses is produced simply by counting the I-ICP pulses (horizontal clock pulses) and after a certain number of them, which are counted by a counter, a flip-flop is reset which in turn allows the HCP pulses to be applied to the Y-counter. A delay counter 232 counts 14 HCP pulses and then resets a flip-flop 234 with its output. The set output of the flip-flop is applied to two NAND-gates respectively 236 and 238. NAND-gate 236 requires as its other input a VR signal. A following NAND-gate 240 is inhibited in the presence of an output from the NAND-gate 236. The other input to the NAND-gate 240 is an input from an inverter 242, which is driven in response to horizontal clock pulses which are received from the NAND-gate in FIG. 3. The output of the NAND-gate 240, when it is enabled, constitutes the clock pulses which drive the Y-counter shown in FIG. 4.

The delay counter 232 establishes the amount of delay until clock pulses are applied to the Y- (or X- counters. Control of the variation in such delay is achieved by changing the count of the delay counter so that it has a different value each time it starts counting to establish the amount of the delay. Establishment of the initial count of the counter is achieved by a delay reference counter 242. The delay reference counter count is transferred into the delay counter through transfer gates, which are enabled during the vertical retrace period. The count in the delay reference counter is established in response to a multivibrator 246 output. The multivibrator is under the control of a programmable counter 248 and associated logic 250, designated as counter control gates.

The variable delay interval provides an opportunity to obtain speed control since, the more rapidly the delay is decreased the more quickly the display appears to move. Accordingly, provision is made for counting through the delay interval at different rates in accordance with signals derived by depressing the slow roll key 202 or fast roll key 204.

The slow roll key 202 output is applied to a NOR-gate 252 to which the slow crawl key 254 output is also applied. The output of the NOR-gate 252 is applied, to an inverter 258 whose output is connected to the set input of the flip-flop 256, and also to the reset input of the flip-flop 256. The application of the W signal to the clock input terminal of the flip-flop 256 enables it to be reset whereby its output is an S signal. Otherwise its output is an signal. The fast roll key 204 and a fast crawl key 260 are connected to a NOR-gate 262. The output of the NOR-gate is connected directly to the reset input of a flip-flop 264 and also through an inverter 266 to the set input of the flip-flop. The application of the W signal to the clock terminal of the flip-flop, in the presence of a fast roll or

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U.S. Classification345/685
International ClassificationG09G5/34
Cooperative ClassificationG09G5/343
European ClassificationG09G5/34A