US 3622704 A
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United States Patent Gilbert M. Ferrieu 7, rue du Clos Sourdry, Bievres; Jean-Michel Person, rue du Parc Saint- Jacques, Perros-Guireo, both of France  Inventors  Appl. No. 884,813
22] Filed Dec. 15, 1969  Patented Nov. 23, 1971  Priority Dec. 16, 1968  France  VOCODER SPEECH TRANSMISSION SYSTEM 4 Claims, 7 Drawing Figs.
 U.S.Cl 179/1 SA [5 1] Int. Cl G101 1/00  Field of Search 179/15.55, 1 SA  References Cited UNITED STATES PATENTS 2,892,892 6/1959 Rack 179/l5.55 R
3,109,142 10/1963 McDona1d.. 179/15.55 R
3,124,654 3/1964 Raisbeck 179/15.55 R
Primary Examinerl(athleen H. Claffy Assistant Examiner-David L. Stewart Au0rneyAbraham A. Saffitz ABSTRACT: A channel vocoder speech transmission system including at the transmitter station a pitch detector circuit producing pitch marker pulses having a repetition period equal to the fundamental pitch period T of the speech to be transmitted, a pitch marker pulse sorter for eliminating spurious pitch marker pulses whose repetition period differs from said fundamental pitch period by a predetermined percentage of the fundamental pitch period and means for coding into PCM signals the pitch period and, at the receiver station, a
speech synthesizer and an excitation signal generator including two shift registers having unequal numbers M and N of stages with M N, two exclusive OR gates respectively associated with the shift registers, with inputs connected to the last and last but one stages of the shift registers and an output connected to the first stage thereof. These shift registers and OR gates form two generators of maximal length linear binary sequences. The shift registers are controlled by shifting pulses having a repetition period equal to T/(2l PAIENTEDuuv 23 l97l SHEET u or 5 Q 5 GE INVENTORS:
Gilbert M. FERR and Jean-Michel PE BY flnzam/ 0N Arming? PATENTEBuuv 23 m 3.622.704
- SHEET 5 BF 5 l POM/[P l f V V u W FPfOl/f/VC) Fig. 7
+ POM/4? INVENTORS:
Gilbert M. FERRIEU and Jean-Michel PER N I I BY fl a/km ATTO VOCODER SPEECH TRANSMISSION SYSTEM This invention relates to speech transmission systems and is particularly concerned with narrow-band systems such as the spectrum channel vocodertransmittingthe infonnation content of wide-band speech waves in the form of a number of narrow-band control signals.
The spectrum channel vocoder is a method for speech analysis-synthesis employing a parametric description of the shorttime speech spectrum. The spectral envelope of the signal is represented typically by 10 to 20 samples or channel control signals spaced along the frequency axis. The spectral fine structure is represented by one additional parameter which measures the fundamental pitch frequency characteristic of voiced sounds and is equal to zero for unvoiced sounds or silence.
Spectrum channel vocoders of the-prior art are disclosed in the article of M. R. Schroeder Vocoders: Analysis and Synthesis of Speech. issued in Proceedings of the IEEE," Vol. 54, No. 5, May 1966 pgs. 723-724. In these systems, at the synthesizer, the original channel signals are recoveredand utilized to control the frequency response of a time-varying filter, consisting of modulators and narrow band-pass filters to correspond to the spectral envelope measured at. the analyzer. The input of this time-varying filter is supplied with a fiatspectrum excitation signal of the proper spectral fine structure produced by an excitation source. This excitation source comprises a noise generator having a white-noise spectrum and a pulse generator controlled by the-pitch control signal, which is a variable frequency pulse generator generating one pulse per pitch period.
According to the invention, the excitation source is formed bya generator of maximal length linear binary sequencies, thatis by a shift register looped on-itself by an exclusive OR circuit. It is known that the maximal length linear binary sei uencies, although deterministic, have properties similar to those of white noise. The advantages of the use of generators of maximal length linear binary sequencies as an excitation source for a vocoder system are now explained.
The r-order harmonic of the output power spectrum of recurrent short pulses having azduration and a recurrence period Tis:
sin 2 p 0) volts =4V T where V is the amplitude of the-pulses.
The mean power density spectrum in the low frequencies is:
D,=40/T I voltsF/Hertz (2) The r-orde'r harmonic of the output power spectrum of a maximal length linear binary sequence of N bits is:
where L=2l is the number ofbits in one cycle of the pseudorandom binary sequence and W2 the amplitude of the positive and negative bits (total amplitude of the binary sequence V).
It results from formula (3) as compared to formula (1) that the output power spectrum is the same for recurrent short pulses and pseudorandom binary sequences if it is assumed that 8=8 and L8=Twhich gives: 2 8 being the duration of one bit.
0/T=8/L 8=l/L (4) The mean power density spectrum in the low frequencies is:
L+ 1 z T The ratio of the mean powerdensity spectra is:
D,/D,=(L+l) 87741.0 and, from (4):
if we take N=7, then L/4 =32 and the power available on a given ray of the spectrum is 32 times higher in the case of a pseudorandom binary sequence than in the case of recurrent short pulses.
It results from the foregoing that,- similarly as the period of the recurrent short pulses was maintained equal to the pitch period, the period L 8 of the shift register words is to be maintained equal to the pitch period.
The invention will be more fully understood from the following detailed descrlption of an illustrative embodiment thereof taken in connection with'the accompanying drawings, in which:
FIG. 1 is aschematic block diagram showing a complete channel vocoder system embodying the apparatus of this invention; I
FIG. 2 is a schematic block diagram showing apparatus for coding into PCM signals the channel control signals;
FIG. 3 is a schematicblock diagram showing apparatus for decoding into analog signals the PCM channel control signals;
FIG. 4 is a schematic block diagram showing the pitch detector and coder;
FIG. 5 is a schematic block diagram showing the channel vocoder synthesizer; and
FIGS. 6 and 7 are two spectrum diagrams useful for the explanation of the invention.
Referring now to FIG. l'the speech signal is produced by microphone Lisamplified by amplifier 2 and is separated into n (for example rt=l4) contiguous spectral bands with bandwidths between 'l'OO Hz. and 400 Hz. covering the frequencies from 200 to 3500 Hz. by means of band-pass filters 3, to 3,. This frequency range, typical of telephone sign'als, permits high intelligibilityand good quality. The output of each filter is connected to afull-wave rectifier, respectively 4 to 4, and low-pass filter,'respectively 5 to 5,. The outputs of the lowpass filters represent the time-varying average signal amplitudes-ofthe frequency-bands. Together these It channels control signals; represent the envelope of the short-time spectrum of the speech signal.
The channel control signals are coded into PCM signals of four bits by. coders 6,to 6,. controlled by clock pulse generator 7. Thedi'gital'signals are applied to multiplexer 8 also controlled by clock' pulse generator 7 and transmitted over a reduced capacity transmission channel 9 to receiver station R.
The incomingspeech signal from microphone l is also applied to pitchdetector and coder 10. A'detailed explanation of the operationand structure of pitch detector and coder 10 is given below in connection with FIG. 4.
At the receiver station R, conventional demultiplexer 11 passes the-coded channel control'signals' to decoders 12, to l2, which'may be of any well-known construction for convert- -ing four-bit signals into analog signals and passes the pitch and to passband-filters'lS, to 15,. Modulators 14, to 14,. are
supplied with an excitation signal produced by synthesizer 13. All the passband filters 15 to 15,, are connected in parallel to amplifier 16 and a loudspeaker I7 is connected to the output of this amplifier: This loudspeaker is fed by the remade speech.
A clock pulse-generator 18 synchronous with 7 controls the demultiplexer 11 and the'decoders 12 to 12,.
Referring now-to FIG. 4; the pitch detector and coder 10 comprises two pitch detectors 101 and 101' respectively connected directly and via inverter to the output of amplifier 2 and two pitch marker pulse sorters and coders 102 and 102'. The circuits '101' and 101' on the one hand and the circuits 102 and 102 on the other hand are identical and only circuits 101 and 102 will be described later on. The function of circuits 101 and 101' is to generate pitch marker pulses and the function of circuits l02 and 102' is to eliminate spurious marker pulses by'blocking the passage of those pitch marker pulses which follow a preceding pitch marker pulse within a predeterminedinhibition time interval.
IOIOIIJI Pitch detector 101 comprises two chains of circuits, a selector chain and a control chain. The selector chain comprises an amplifier 103 having a low output impedance, a capacitor 104, a resistor 105, a transistor 106, an amplifier 107 and a monostable flip-fiop 108. The capacitor 104 is serially connected at the output of amplifier 103 and the resistor 105 and the emitter-collector path of transistor 106 are connected in parallel on to the leads mutually connecting the two amplifiers 103 and 107. The output of flip-flop 108 is connected to the base of transistor 106.
The control chain of pitch detector 101 comprises a threshold and differentiating amplifier 109 and a monostable flip-flop 110. The output of monostable flip-flop 110 is connected to the automatic gain control (AGC) terminal of amplifier 107 of the selector chain.
The operation of the pitch detector is the following. Amplifier 107 is blocked when no signal is applied thereto and its gain is very large when AGC terminal receives a pulse from flip-flop 110. As the amplifier 109 phase-shifts by 11/2 and clamps the speech signal, it produces a rectangular signal whose leading and trailing edges substantially coincide with the positive and negative peaks of the speech signal. The edges which correspond to the positive peaks operate monostable flip-flop 110 which unblocks amplifier 107. In the absence of the selector chain, the pitch period would be determined by flip-flop 110 while disregarding the relative amplitude of the positive and negative peaks of the speech signal.
The function of the selector chain of the pitch detector is to control the operation of flip-flop 108 and to make it recopy or disregard the operation of flip-flop 110 according to whether the decay in the input signal amplitude since the last operation of the flip-flop 108 is larger or smaller than a given amount. In other words, flip-flop 110 generates proposed marking pulses and flip-flop 108 confirms some of these pulses and omits the others.
Capacitor 104 can charge through transistor 106 in its conducting state and discharge through resistor 105. Conduction of transistor 106 is controlled by flip-flop 108. Let us assume that flip-flop 110 has just operated marking the beginning of a pitch period and that flip-flop 108 has simultaneously operated. Flip-flop 108 brings transistor 106 to its one state and capacitor 104 charges with respect to ground. Then flipflop 108 is restored to its zero state and capacitor 104 discharges through resistor 105. If at the beginning of next pitch period as determined by the control chain along the speech signal amplitude as reduced by the discharge of capacitor 104 across resistor 105 is higher than a given threshold at the input of amplifier 107, flip-flop 108 will be operated. If the input signal to amplifier 107 is smaller than said given threshold flip-flop 108 will not be operated despite the operation of flip-flop 110. Hence, pitch detectors 101 and 101 produce pitch marker pulses corresponding to positive peaks as regards pitch detector 101 and negative peaks as regards pitch detector 101' regardless of whether these peaks are periodical or not.
The amplitude difference between the signal issuing from amplifier 103 and the signal applied to amplifier 107 depends on the time constant due to capacitor 104 and resistor 105 and on the duration of the discharge. The minimum of this duration is the lower limit of the pitch period, say 2 ms. in order not to have more than one significant peak per minimal period, the above time constant is selected in such a way that the attenuation of a peak issuing from 103 generates in 2 ms. a signal lower than the threshold of amplifier 107.
The pitch marker pulse sorter and coder comprises a counter 121 which is supplied at its input terminal with clock pulses generated by clock pulse generator 7 and at its reset terminal by pitch marker pulses generated by monostable flipflop 108 and is connected to nonlinear time base generator 122. Nonlinear time base generator 122 has four output terminals 122 to 122,. At terminal 122,, 122,, 122 there appear recurrent pulses corresponding to the three first clock pulses coming from clock pulse generator 7. At terminals 122 there appear successive nonperiodic pulses spaced apart from each other by increasing time-intervals T, such that:
i.e., the time separation between adjacent pulses increases according to a geometrical progression law. if T,=2 ms., which corresponds to a pitch frequency of 500 Hz. which is practically the upper limit of the shriller voices, K=63 and T-=16 ms. which corresponds to a pitch frequency of 62.5 Hz. which is practically the lower limit of the deeper voices, then A=1.033.
123 designates a counter which counts the pulses issuing from output terminal 122, of nonlinear decoder 122. The outputs of counter 123 are connected to the inputs of register 124 via AND-gate set 125 and to the inputs of comparator 126. The outputs 'zero and one of comparator 126 are connected to the inputs zero and one of flip-flop 127 via AND-gate 128 and 129. The zero output of flip-flop 127 is connected to AND- gate 140 together with a lead coming from 122 The output of AND-gate 140 controls a set of AND-gates 141 inserted between a register 144 and a buffer register not shown connected to multiplexer 8. Register 144 is connected to the outputs of counter 121 via AND-gates 145.
The operation of the pitch marker pulse sorter and coder is the following.
1- being the period of clock pulse generator 7, at time zero (beginning of the pitch period) the comparison signals, one or zero, are entered into flip-flop 127. At time 1', the contents of register 144 is transferred to the buffer register by opening of AND-gates 141 and the contents of counter 123 is transferred into register 124 by opening of AND-gates 125. At time 2? counter 123 is reset and the contents of counter 121 is transferred into register 144 by opening of AND-gates 145. In each pseudocycle between two pitch marker pulses, the duration of the preceding pitch period expressed in a nonlinear code which is written into 124 between the time 1 and the next time 1, the comparator is fed from counter 123 between the time 21 and the next time zero and the delivery of the pitch control signal to the multiplexer takes place, except for spurious marker pulses at time 1'.
Comparator 126 compares the bits of the coded pitch control signal of two successive pseudocycles except the lower weight bit. As the lower weight bit represents a time interval which increases when the coded pitch control signal increases due to the expansion in nonlinear decoder 122, it results that the predetermined inhibition time referred to in the introductory part increase with the pitch period.
Analog to PCM compression converters or coders are known in the art and such a coder is shown in FIG. 2.
The output signal of low-pass filter 5. 1 i S n) is applied to the input terminal 60,, of the coder 6. and is compared in comparator 61 to a series of predetermined voltages generated across resistor 601 by means of a matrix 610. When the signal to be coded with compression is higher than the predetermined voltages being compared, a comparison signal one is applied to flip-flop 602. The one output of flip-flop 602 opens the AND gate 603 and counter 604 counts clock pulses produced by time-base 605. Time-base 605 is synchronized by clock pulse generator 7. The signals produced by counter 604 comprise four bits which are respectively applied to four output gates 611-614 and are divided into two groups of two bits which are respectively applied to decoders 606 and 607.
The four outputs of decoders 606 are connected to the four lines of matrix 610 and the four outputs of decoder 607 are connected to the four columns of the said matrix. The crosspoints of the matrix are passing or blocked switches according to whether the line and column controlling a given cross-point are supplied with current or not. The cross-points comprise also resistors in which a current can flow or not according to whether the switch is open or closed. All the columns of matrix 610 are connected in parallel to resistor 601. The matrix resistors are given suitable values for complying with the compression law.
' plied, through tenninal 13 As soon as the signal to be coded with compression is lower than one of the predetermined voltages being compared, a comparison signal zero is applied to flip-flop 602. This flipflop closes AND-gate 603 which stops counter 604. The AND-gates 611-614 are then opened by time-base 605 and the code is transferred to multiplexer 8.
PCM to analog expansion converters or decoders are known in the art and such a decoder is shown in FIG. 3.
The coded channel control signals from demultiplexer 11 are applied respectively through terminals 120 to 120, to flipflops 1211 to 1214 of decoder 12, which control a digital attenuator 1200 supplied with direct current by current source 1201. The flip-flops are reset by clock pulse generator 18 through terminal 120, and the analog signals are applied to modulator 14, through terminals 120 The purpose of circuit 13 is to produce a flat spectrum excitation signal over all the voice bandwidth which is formed by the fundamental component of the voice and its harmonics in the case of voiced signals, and is a white noise signal in the case of unvoiced sounds.
Generator 13 comprises two shift registers 130 and 131 the first formed of seven flip -flops 1301 to 1307 and the second of 11 flip-flops 1311 to 1321. These shift registers are looped afterthe fashion of a ring counter through two exclusive OR- gates 1300 and 1310 respectively, which receive at the same time the bits respectively in the last and last but one flip-flops of the associated shift register. The outputs of exclusive OR- gates 1300 and 1310 are connected respectively to one input of AND-gates 1381 and 1382. Registers 130 and 131 are known in the art as maximal length linear binary sequence generators.
The advance of both shift registers 130 and 131 is achieved by advance flip-flop 132. At each step of the shift registers, the words written in the registers change and the same word is restored after L,=2l=1 27 advance pulses in the case of register 130 and L,=21=2047'advance pulses in the case of register 131. The coded eight-bit pitch control signal is applied through input terminals 1321-1328 to register 133 and AND-gate 134. From register 133, this signal is applied to counting-down counter 135 through AND-gates 1361 to 1368. Counting-down counter 135 comprises eight flip-flops 1351 to 1358 whose outputs are connected to AND-gate 137. The output of AND-gate 137 is connected to the one input of flip-flop 132 through inverter 1383. Counting-down counter 135 is driven by time base 138 which produces high-rate clock pulses, of 2 MHz. frequency for example.
The output of AND-gate 134 is connected through inverter 1384, to the one input of flip-flop 139 and to one of the inputs of AND-gate 1385. The one and zero outputs of flip-flops 139 are connected respectively to the second inputs of AND-gates 1381 and 1382. The clock pulses from generator 18 are apto AND-gate 1385 and to flip-flop 139 for resetting it.
The operation of excitation circuit 13 is the following. As assumed in the foregoing the maximal pitch period is T =l6 ms. and is expressed in an eight-bit pitch control number; it results that the lower weight bit of this number represents 1/256 of 16 ms., that is approximately 64 sec. Thus the decimal translation of the pitch control number represents T divided by 64 ,u. sec. for a pitch period of Tseconds, that is the number l T/64 wherein Tis expressed in seconds. The multiplex period is assumed to:be 25 ms. which corresponds to a frequency of 40 Hz.
The pitch control coded'signal or number is applied at an instant which will be defined later on to counter 135 which counts down to zero, the count zero being detected by gate 137. The output signal of gate 137 triggers flip-flop 132 which opens gates 1361 to 1368 and advances by one step shift registers 130 and 131. A new pitch control coded signal is entered into counter 135.
The time for counting down from l0T/64 sec. to zero at a rate of 2 MHz. which represents the period of the advancing pulses is:
AND-gate 1385 is to As L I 27 and L,=2047, the period L 8 of shift register is:
l.,,6=l27T/l28 -Tsec. and the period L 8 of shift register 131 is:
The spectrum of the maximal length linear binary sequence issuing from shift register 130 is represented in FIG. 6 and the spectrum of the maximal length linear binary sequence issuing from shift register 131 is represented in FIG. 7 It can be seen in FIG. 6 that the spectrum is quite flat up to 3,500 Hz. and comprises a harmonic every 62.5 112., that is 53 harmonics between 200 and 3,500 Hz. The spectrum of FIG. 7 comprises 16 times more harmonics than the spectrum of FIG. 6 and, due to low spacing between harmonics, it resembles a white noise.
The mean power density spectrum is the same in FIGS. 6 and 7 since fonnula (4) can be written:
D,,=(1+l/L)' V- 5V which shows that D, is practically independent of L.
In the case of an unvoiced sound the pitch frequency is zero and the eight bits of the pitch control signal are all equal to zero. AND-gate 134 is then passing and flip-flop 139 is brought to its one state and AND-gate 1385 will be opened at the riext pulse from terminal 13, Flip-flop 139 opens gate 138] and closes gate 1382, thus substituting the white noise signal for the pseudorandom binary'sequence. The purpose of prevent the entry of an eight zero number into register 133.
What 'we claim is:
1. A channel vocoder speech transmission system including at the transmitter station a pitch detector circuit producing pitch marker pulses, the majority of which have a repetition period equal'to the fundamental pitchperiod T of the speech to be transmitted, a pitch marker pulse sorter fed by said pitch marker pulses and adapted to eliminate therefrom spurious pitch marker pulses whose repetition period differs from said fundamental pitch period by a predeten'nined percentage of the fundamental pitch period and to retain normal pitch marker pulses whose repetition period is equal to said fundamental pitch period and means for coding into PCM signals the intervals between the normal pitch marker pulses and, at the receiver station means for receiving said PCM signals and deriving therefrom the pitch period T, two shift registers having unequal numbers M and N 'of stages with M N, two exclusive OR gates respectively associated with the shift registers, with inputs connected to the last and penultimate stages of the shift registers and an output connected to the first stage thereof, means for generating pulses of a given repetition period for synchronously advancing said shift registers and means for controlling said given repetition period and equalizing it to -T/(2"'-l 2. A'channel vocoder speech transmission system including at the transmitter station a pitch detector circuit producing pitch marker pulses the majority of which have a repetition period equal to the fundamental pitch period T of the speech to be transmitted, a pitch marker pulse sorter fed by said pitch marker pulses and adapted to eliminate therefrom spurious pitch marker pulses whose repetition period differs from said fundamental pitch period and to retain normal pitch marker pulses whose repetition period is equal to said'fundamental pitch period and means for coding into PCM signals the intervals between 'the normal pitch marker pulses and, at the receiver station means for receiving said PCM signals and deriving therefrom the pitch period T, two shift registers having unequal number M and N of stages with M N, two exclusive OR gates respectively associated with the shift registers with input connected to the last and penultimate stages of the shift registers and an output connected to the first stage thereof, means for generating pulses of a given repetition period for synchronously advancing said shift registers, means for controlling said given repetition period and equalizing it to T/(2" -A), means for detecting pitch periods equal to zero, a
speech synthesizer and switch means controlled by said zero pitch period detecting means for selectively applying to said speech synthesizer the output signal of the M-stage shift register and the output signal of the N-stage shift register.
3. A channel vocoder speech transmission system including at the transmitter station a pitch detector circuit producing pitch marker pulses the majority of which have a repetition period equal to the fundamental pitch period T of the speech to be transmitted, a pitch marker pulse sorter fed by said pitch marker pulses and adapted to eliminatetherefrom spurious pitch marker pulses whose repetition period differs from said fundamental pitch period by a predetermined percentage of the fundamental pitch period and to retain normal pitch marker pulses whose repetition period is equal to said fundamental pitch period and means for coding the intervals between the normal pitch marker pulses into a PCM code in which the unity bit represents a time increment i and, at the receiver station, means for receiving said PCM signals and deriving therefrom the pitch period T, two shift registers having unequal number M and N of stages with M N, two exclusive OR gates respectively associated with the shift registers with input connected to the last and penultimate stages of the shift registers and an output connected to the first stage thereof, register means for storing the coded pitch period, a counter counting down with a rate r=(2l )/i from T/i, down to zero, means for detecting the zero count of said countingdown counter, said count-down from T/i down to zero lasting 8=Tl(2"l and means for generating pulses of recurrence period 5 for shifting said shift registers.
4. A channel vocoder speech transmission system as set forth in claim 3 in which r=2(10) Hertz