Publication number | US3622762 A |

Publication type | Grant |

Publication date | Nov 23, 1971 |

Filing date | Jun 11, 1969 |

Priority date | Jun 11, 1969 |

Also published as | CA924017A, CA924017A1 |

Publication number | US 3622762 A, US 3622762A, US-A-3622762, US3622762 A, US3622762A |

Inventors | Dyer Lester W, Houston Theodore W, Policky Gary J |

Original Assignee | Texas Instruments Inc |

Export Citation | BiBTeX, EndNote, RefMan |

Non-Patent Citations (3), Referenced by (31), Classifications (11) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 3622762 A

Abstract available in

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Description (OCR text may contain errors)

United States Patent [72] Inventors beaten-W. Dyer Plano More w. Houston, Richardson; Gu J. Policlty, Plano, all of Tex. [21 Appl. No. 833,892 [22] Filed June 11, 1969 [45] Patented Nov. 23, 1971 [73] Assignee Texas Instruments Incorporated Dallas, Tex.

[54] CIRCUIT DESIGN BY AN AUTOMATED DATA PROCESSING MACHINE 31 Claims, 5 Drawlng Figs.

[52] US. Cl 235/150 [SI] Int. Cl. 606i 15/56 [50] Field of Search... 235/150 [56] References Cited OTHER REFERENCES Computer-Aided Design of Microwave Integrated Circuits;" lEEE-Wescon Tech Papers; Vol. 13 pt. 2; Session 6/6/69; pp. 1- 3; Houston, Dyer, & Policky Optimal Design of Matching Networks for Microwave Transistor Amplifiers;" IEEE Transactions on Microwave Theory and Techniques; Vol. M'IT- 14; pp. 696- 698; Dec. I966; F. E. Emery and M. O Hagan Design of Digital Loaded-Line Phase-Shift Networks for Microwave Thin-Film Applications;" IEEE Transactions on Microwave Theory and Techniques; Vol. MTT-IG, No. 7; July 1968; Frances L. Opp and W. F. Hoffman ABSTRACT: Using representations of circuit topologies and initial values of all elements, a circuit design may be modified by an automated data processing machine to improve operation for at least one performance characteristic by changing design variables. A desired circuit topology is selected and the initial values for all the circuit elements are coded and stored in the data processor. In addition, the desired performance characteristic is also selected and coded. Using coded input information, the data processor generates and stores a representation of a continuous analytical objective function. In the operation of the data processor, a value of the objective function is generated and stored. This value is dependent upon the sum of a power function of the difference between an actual performance and a specified performance characteristic. To obtain a specified performance characteristic for a given circuit topol gy, the value of the objective function is improved.

DEVICE CHARACTERIZATION TOPOLOGY OBJECTIVE FUNCTIONS- SELECTIONS GENERATE Y-MATRIX a DERIVATIVES 58 ANALYSIS INFORMATION INPUT FORM OBJECTIVE FUNCTIONSO DEQIVATNES CALCOMP LAYOUT PLOT OPTION PAIENTEBNUY 231911 3.622.762

SHEET 1 BF 3 DEVICE I8 7 DATA 28 LAYOUT DEVICE DATA DATA I i l ,2 ICHaLIOGY i 32 3o T 1 T 1/ K MICROSTRIP X-Y MASKS I4 TOPCgLOGY PTIMIZATIONI LAYOUT CONTROL GENERATED PARAMETER 10 34 24 K 2o LAYOUT FLAYOUT CONTROLG PARAMETER DATA DATA OBJECTIVE LIST sTART GENERATE OBJECTIVE FUNCTION a GRADIENT INVENTORS: LESTER W. DYE-R THEODORE GARY J. Pout-KY PAIENTEDIIUV 23 I97I SHEET 2 [IF 3 DEVICE CHARACTERIZATION TOPOLOGY V OBJECTIVE FUNCTIONS- SELECTIONS OPTIMIZE FIG. 3

GENERATE Y'MATRIX BI DERIVATIVES 58 ANALYSIS INFORMATION INPUT CALCOM P P LOT FORM OBJECTIVE FUNCTIONS 8I DERIVATIVES LAYOUT OPTION LESTER W. DYER THEODORE W. HOUSTON GARY J. POL/CK Y PATENTEDunv 2 3 I97! SHEET 3 BF 3 IBa FIG. 4

FIG.5

INVENTORS: LESTER W. DYER THEODORE W. HOUSTON GARY J. POL/CK Y CIRCUIT DESIGN BY AN AUTOMATED DATA PROCESSING MACHINE This invention relates to circuit design, and more particularly to optimization of a circuit design by means of an automated data processing machine.

Circuit designing for years has been the task of an engineer calculating various circuit parameters with a slide rule and paper and pencil. Typically, an engineer is assigned the task of designing a circuit having certain performance characteristics. Either from memory or from a reference text, he selects a circuit topology having known performance characteristics similar to those desired. The designer then calculates the value of each circuit element for a specific performance characteristic. The end result is a circuit that is intended to operate in accordance with the assigned performance characteristic. The final circuit, however, is usually a compromise from what is desired.

ln recent years, considerable emphasis has been placed on computerized designs in all fields including electronic circuits, and, as expected, in many cases the computer has outperformed the engineer. It must be recognized, however, that a computer is only a tool in the hands of the design engineer replacing his slide rule. Thus, a computer-designed circuit may be no better than that produced by an engineer using a slide rule. For example, a wide band linear amplifier consisting of several stages might be designed by considering each circuit element of each stage individually and then cascading the results to obtain the desired overall effect. This, in essence, is the same procedure used by the engineer in his manual computations. The desired band width might be achieved by either stagger-tuning or single-tuning the stages. Whether the end result is an amplifier having stagger-tuning or single-tuning depends on the instructions to the computer. ln effect, the computer merely relieves the engineer of his slide rule calculations. The final circuit design may operate no better than that designed by hand calculations.

In accordance with the present invention, an engineer selects a representative circuit topology and assigns initial values to all the circuit elements. This information is coded into a computer along with selected options that outline a specified circuit performance characteristic. The automated data processing machine, using a program listing, then considers the overall circuit topology in light of the desired performance characteristic and provides an optimized circuit design. Using the programlisting, the data processor changes design variables, including circuit elements, in a manner that is not limited to any specific design approach. The process considers the entire circuit as a whole, and not individual parts that must later be combined. Consider the previous example, all the design variables of the several stages are evaluated simultaneously to improve the performance as specified by selected performance characteristics. The final circuit design may be stagger-tuned, singled-tuned, or some combination. A data processor operating in accordance with the present invention is not limited to any specified approach. Rather, it is free to choose the approach that provides optimized circuit operation.

In designing a circuit, the automated data processor constructs an admittance matrix and the first derivative thereof with respect to the design variables. The admittance matrix and the first derivative are then used to generate a continuous analytical objective function in accordance with the performance characteristic options selected by the user. The first derivative of the objective function is also generated by the processor. Both the objective function and its first derivative are called by an optimizer routine that modifies at least one of the design variables in a direction and by an amount dependent on the objective function and the objective function derivative. Using the modified design values, a selected circuit topology is then reconsidered to determine if additional im provement is possible. An optimized circuit design is achieved by considering the selected circuit topology and the objective function over a range of frequencies.

To optimize a particular circuit topology to achieve a given performance characteristic, the objective function includes terms for the sum of a power function of the difference between a specified performance characteristic and a calculated performance over a range of frequencies. Where applicable, the objective function includes a term to minimize the difference between an actual performance characteristic and a specified performance characteristic beyond preset limits. Further, the objective function may include terms such that the final circuit design will operate at a given frequency either at, below, or above a specified value of a performance characteristic.

Further, in accordance with the process of the present invention, an automatic data processing machine will optimize the operation of a circuit that includes elements that may be switched into and out of the circuit, that is, a circuit that has several operating modes. Again, the data processor considers the entire circuit as a whole. An admittance matrix and the first derivative thereof with respect to the design variables is constructed for each of the several operating modes. A composite objective function is then generated using the admittance matrix and the first derivative for each of the several operating modes. The composite objective function is then called by the optimizer routine that modifies design variables throughout the several operating modes in a direction and by an amount dependent on the composite objective function and the objective function derivative. As explained, the design values modified in the optimizer routine are then used to determine if additional improvement is possible.

The improvements in circuit operation achieved by the method of the present invention is primarily the result of generating a continuous analytical objective function that has a continuous first derivative. This continuous analytical objective function and its continuous first derivative are generated in a routine that employs the admittance matrix of a selected circuit topology and the first derivative of the matrix. Both the objectivefunction and the first derivative are inputs to an optimizer routine. in the optimizer routine the original element values are adjusted in a manner to improve a numerical representation of the objective function. The optimizer routine may be repeated several times, each time using a new value of the objective function and its first derivative (generated from design variables modified in the previous optimizer pass) to further adjust the circuit element values. This readjustment continues for a preselected number of passes at a preselected number of frequency points to produce the best possible circuit design.

A morecomplete understanding of the invention and its advantages will ,be apparent from the specification and claims, and from the accompanying drawings illustrative of the invention.

Referring to the drawings:

FIG. 1 is a block diagram of a total automated data processing machine for generating circuit masks representing an optimized circuit design;

FIG. 2 is a basic fiow chart of the optimization operation in a circuit design sequence;

FIG. 3 is a logic fiow chart illustrating the method of op-- timizing and analyzing a circuit design;

FIG. 4 is a schematic of a single-mode representative circuit topology that may be optimized by the method of the present invention; and

FIG. 5 is a schematic of a multimode circuit which also may be optimized by the method of the present invention.

Referring to FIG. 1, there is shown a block diagram of a system for computerized design of linear time invariant electronic circuits consisting of resistors, capacitors, inductors, transmission lines, controlled current and voltage sources, circulators, transformers, and three terminal devices characterized by s or y parameters as a function of frequency and one other variable. The input to the system is a circuit topology and circuit performance criteria. Outputs include optimized values for the parameters of the circuit topology along with performance characteristics of the optimized circuit, and for microstrip circuitry a photomask for producing an optimized circuit.

Coded data of a selected circuit topology may be inputted to an analysis and optimization routine 10 from a memory storage 12 or punched cards 14. Catalog circuits in the memory storage 12 may be retrieved by an identifying code number. These circuits have been optimized for particular objectives, and can be reoptimized for difierent objectives or with different active device characterization data. Also, it is possible to modify the topology of the cataloged circuits by adding, changing, or deleting elements. Use of the catalog of circuits simplifies setting up the analysis and optimization routine. Where the desired circuit topology is not one of the cataloged circuits, however, the desired circuit may be coded onto the punched cards 14 as an input to the analysis and optimization routine 10.

In addition to a circuit topology and initial circuit element values, the analysis and optimization routine 10 may receive input information on active circuit components in the form of s or y parameters as a function of frequency and some second variable. Again, the device data may be inputted to the analysis and optimization routine 10 from a device memory storage 16 or device punched cards 18. In addition to device data and circuit topology and parameters, the analysis and optimization routine must receive input data in the form of a design goal for the selected circuit. This design goal is an expression (objective function) which is in some way proportional to the goodness of the circuit. The objective function may be selected from a number of available options or prepared to satisfy a particular design goal. In either case, the objective function is inputed into the analysis and optimization routine by means of punched cards 20.

After receiving input information on a desired circuit topology and initial values of all circuit elements, and at least one desired performance characteristic, the analysis and optimization routine 10 produces an output giving optimized values for the circuit elements and a circuit analysis, when requested, which is an input to a microstrip layout routine 22. For microstrip circuits, the values for the circuit elements in the output from the analysis and optimization routine 10 will include the physical length and width of the transmission lines. As an alternative, the output from the optimization routine 10 may be readout and printed on a layout parameter list 24. The information on the list 24 may then be used to punch layout data cards 26. Layout data cards may then be used at some later time to provide coded information to the microstrip layout routine 22. There usually will be one data card 26 per circuit element giving the line length and width, the nodal connection, and approximate coordinates of the end points. In addition to the optimization routine l0 and the layout cards 26, the microstrip layout routine 22 may also receive layout data from a memory drum 28. The memory drum 28 and/or the data cards 26 supplies data on the approximate configuration of the microstrip lines.

The output of the layout routine 22 consists of coordinates of the end points and bend points of all elements of the circuit topology optimized by the analysis and optimization 10. A mask 30 will be generated outlining the desired circuit topology with the optimized circuit values. This mask will be generated by means of a plotter 32, for example, a Gerber plotter, connected to the output of the layout routine 22. The layout 22 will also produce a listing of data cards 34 which may be punched for future mask generation.

Referring to FIG. 2, there is shown a basic block diagram of a logic flow chart for the optimization routine 10 for a circuit design. The program for optimization of a circuit design includes subroutines that perform nodal analysis on a specified circuit topology coupled with a subroutine of conjugate gradient optimization. After the selected circuit topology, with nodal points identified, and all circuit element values, has been coded and stored, an objective function is generated from the selected objective function options (block 36). In addition to an objective function, the first derivative or gradient thereof with respect to design variables is generated and stored. Optimization of a circuit design begins by questioning whether the selected circuit is to be optimized or channeled to an output circuit 38. If the inquiry, identified by the diamond 40, produces an answer that the selected circuit requires further optimization, then the objective function and its gradient are called by an optimizer subroutine to optimize the objective function by adjusting circuit design variables, indicated by the block 42. The selected circuit topology with the adjusted design variables is then analyzed and a new objective function and a first derivative are generated by the subroutine of block 36, The analysis compares a synthesized performance characteristic with a desired performance characteristic, as represented by the objective function.

If the desired performance characteristic has not been achieved in the last optimization and adjusting pass, a new ob jective function and its gradient are generated and stored based on the adjusted values of the circuit elements. Again, an inquiry is made as to whether another optimization pass will be made. If additional optimization of the circuit is desired, another pass will be made through the optimizer subroutine 42. Another adjustment of the circuit elements takes place, and another evaluation of the objective function and its gradient is made. This cycle continues until either the desired performance characteristics have been obtained, or the number of passes reaches a preset number. In either case, the selected circuit topology and final circuit element values are coupled to the output circuit 38.

Referring to FIG. 3, there is shown a logic flow chart for the optimization routine 10 including the generation of objective functions and a circuit admittance matrix. To run the optimization routine, a selected circuit topology together with initial circuit element values must be coded and made available. The suggested procedure for coding a selected topology is to sketch the circuit and label all the nodes and place identifiers on all the elements. It is not necessary that the node numbers be in any special sequence. The input and output nodes may be specified; however, if no value is specified for the input node the lowest numbered node will assume to be the input. If no value is specified for the output node, the highest numbered node is assumed to be the output. The datum node (a reference mode) is normally assumed to be the zero node. The source admittance is always connected between the input node and the reference node and the load admittance is always connected between the output node and the reference node. Source and load admittances and black box (s) or (y) parameters are inputted to the optimizer routine as a sequence of measured data points. In order to interpolate between the data points, a polynominal of specified degree is fit through these points such that the mean-squared error is minimized. Referring to the following equation:

the coefficients A0, A l, AN, are determined by means of the measured data points and coded and stored in the memory 46 along with the circuit topology and circuit element values. For any frequency F, the admittance Y(F) for the source, load or black box may be calculated using the above equation. As an alternative, the exact data for the source and/or load admittance at each frequency to be used in the optimization routine may be supplied and coded for storage in the memory 46. The optimization routine will then use the exact values of the source and/or load admittance. For a black box, it is possible to specify the s or y parameters as a function of some second variable, such as collector current in the case of a transistor, in addition to the frequency.

In addition to a selected circuit topology and device characterization, the optimization routine must also be supplied with at least one selection from a plurality of objective function options. The objective function may be written as follows:

OBJECTIVE FUNCTION 2;,,( Wr'gi(Gain)+W 'gz(Noise Figure etc.) (2) Where the constants W are weighting factors which allow emphasis to be placed on one or the other of the'quantities to be optimized, and the 8 terms are arbitrary functions of the quantity in parenthesis. The term f indicates that the objective function is formed by summing the expression at (2) over several frequencies in the range of interest. Various expressions available for use in generating an objective function are listed in table i.

When an engineer is designing an electrical circuit, he has a set of well-defined circuit characteristics and specifications which he desires the completed circuit to achieve. As previously mentioned, the design engineer selects options that outline such specified circuit performance characteristics. For example, his goal might be to maximize the gain over the frequency band for his circuit, subject to the condition that the variation in the gain over that frequency band be small. The design engineer would then examine the list of available optimization options in table I to determine if an option is included which corresponds to his design goals. in this case, he would find that a combination of options 2 and 3 correspond to these exemplary design goals. When more than one option is chosen by the design engineer, as here, he must also assign a weighing factor to each option which signifies the relative importance of one chosen option with respect to another chosen option. That is, the design engineer might determine that the goals of the circuit which he is designing require optimization according to options 4 and 5 of table i. By optimizing according to option 4, however, the characteristics according to option might become less optimized; while, by optimizing 5, 4 might become less optimized, these being unavoidable characteristics of the physical laws of electricity. The design engineer must then assign relative weights to each ofthe objective function selected. Thus, where the design engineers circuit requirements as to the relative importance of options 4 and 5 are equal, an equal weight would be assigned to each. On the other hand, if the design engineer's circuit requirements are such that, although optimization according to options 4 and 5 are desired, the optimization according to the equation of op tion 5 is more important that that of option 4, a higher weighing factor will be given to option 5. The relative importance given to each by the processing machine is determined by the actual weighing factor assigned to each which is totally in the control of the design engineer to exactly meet his circuit goals. This same procedure isused for any other set of design specifications which the engineer might have for a circuit he is designing. A more detailed explanation of the optimization of characteristics for a specific circuit is later described in detail with respect to FIG. 4.

in addition to the objective function options, the memory 46 must also receive coded data on the number of frequency points at which the circuit topology will be evaluated to meet the selected performance characteristic. Further, the memory 46 must receive instructions as to the maximum number of passes through the optimizer routine for evaluating the selected circuit.

With all the above instructions coded into the system, the optimization routine first inquires as to whether or not optimization of the selected topology is desired. if optimization of the selected circuit topology is to be bypassed, the number of passes through the optimizer will be zero (N=)as indicated by the block 48. in this case, the selected circuit topology data and the values of the circuit elements will bypass the optimization routine, and instead be transferred to a circuit analysis routine to be described.

if N (the number of optimizer passes) is greater than zero, however, then the selected circuit topology will be optimized. To optimize and adjust a selected circuit, the routine generates an admittance matrix (Y-matrix) from the selected circuit topology as identified by the block 50. By using nodal analysis, a full nXn admittance matrix for the selective circuit may be formed in most cases. To reduce the order of an admittance matrix, series or cascaded elements are reduced to a single 2X2 matrix which is then added to the system Y-matrix.

TABLE t-pnmcrrvn FUNCTION OPTIONS l. 21 .(l,lN(fk) (l RE F (11.)) Tho calculated 'nin, UN, at

the sampled iioqnoncius, fk, is least-squnrotl-orror iii. to n rcfurnnco znin,

(lREF, fixed by the user. 2".-. 2I| (0:N(/|t)UFLOAT) The gain isllt to (ll LOA'l,

a floating lint reference gain, in the sense of itiilSiZ-SQlllil'tlfi-tl'iOl. This floatin reference gain (listed as the next option) is a variable and must be given a starting, value and an up or and lower limit. l (G LOA GF OA MAX) GFLO T is the amplitude of the floating reference gain which is fit. in option .2. GFLOAT is maximized and must he used in conjunction with option 2. Options 2 and 3 are listed separately to allow differential weighting of the "smoothness" and overall flat-gain" objectives. (lFLOAT- MAX is the maximum or upper limit of .SJE T- The area under the noise figure squared vs. frequency'curvo is minimized. The calculated noise figure, NF, at the sampled frequencies, [1, is least-squarcd-error fit to a reference noise figure, SPECNF, fixed bribe la e The area under the source mismatch squared vs. frequency curve is minimized. The calculated source mismatch, MMS, at the sampled frequencies, fk, is least-squarederror fit to zero source mismatch. ,7

The area under the load mismatch squared vs. frequency curve is minimized, The calculated load mismatch, MML, at the sampled frequencics, Jr, is least-squaredcrror fit to zero load swig-J.- W.

Z matrix of circuit is matchd to a s ecificd Z matrix. The matrix, impedance matrix, of circuit at sampled frequencies, fk, is 1east-squared-error fit to an m -(NFUo-smonrr:

501. s ran est impedance matrix E011 ZSPECIZ ZSP'ECZI ZSPEC22 fixed by the user. IIN is the node number assigned to the input node by the user and IQUT is the node number assigned to output node by the user. AIMAG is program shorthand for the imagieh aLurc i The phase is fit to a floating reference phase. The calculated phase, PH, at sampled frequencies, fk, is ieast-squared-error fit to a reference phase. The reference phase is the sum of PHREF, which is specified by the user as a function offk, and PFLOAT-l-SFLOAT'fk where PFLOAT and SFLOAT are parameters of the optimization which may vary between limits set by the user.

This procedure is known as ABCD reduction. To generate the admittance or Y-matrix, the system goes through the selected circuit, element by element, cumulatively adding the contributions of each element to the matrix. In many cases the admittance matrix for a circuit will be sparse, i.e., many of the entries are zero.

In addition to the admittance matrix, the first derivative of the matrix is formed by the routine of block 50. Further, as indicated by the block 52, the system has a special matrix inverting routine which takes advantage of the sparsity of the Y- matrix to produce an inverted Y-matrix or Z-matrix which can be used to readily obtain most characteristics of a selected circuit.

Assuming that at least one performance characteristic has been selected such that J (the number of chosen objective function options) is not zero, then the routine of block 54 will generate and store an objective function and the first derivative thereof with respect to the design variables. From the objective function and its first derivative, a numerical value thereof will be generated and stored for circuit optimization. The objective function is generated from the options selected from table 1. Using the value of the objective function and the value of the objective function gradient, an optimizer subroutine of block 56 adjusts circuit design variables in a mannerdependent upon the objective function and its gradient.

The optimizer subroutine (block 56) may be thought of as trying to find the highest point in an m-dimensional space, where m is the number of variables, and the height is the value of the objective function. By placing constraints on the variables, i.e., the circuit elements, boundaries are formed in this m-dimensional space. The optimizer routine of block 56 uses the conjugate gradient of the objective function and the value of the gradient of the objective function in finding the highest point, that is, a circuit that operates as near as possible to the selected performance characteristics.

First the objective function and its gradient are evaluated at some feasible starting point in the m-dimensional space. Having initially evaluated the objective function gradient, the next step is to optimize by adjusting a circuit element to produce a value for the objective function in the steepest uphill direction allowed by the constraints. The objective function and its gradients are again evaluated at the new point. If the value of the objective function has not been increased, the subroutine cuts back on its step size and reevaluates the objective function. This interpolation of the step size continues until the objective function is increased or a limit on the number of cutbacks allowed is reached.

The matrix of conjugate directions is then updated by using the newly found better value for the objective function and its gradient. All future steps are taken in the same direct manner as the first step except that instead of the true gradient, the conjugate gradient is used to determine the direction of the step. The conjugate gradient is derived from the true gradient by multiplying by the matrix of conjugate directions. For a more detailed explanation of the optimizer, reference is made to the Ph. D. thesis of Donald Goldfarb, entitled A Conjugate Gradient Method for Nonlinear Programming," Ph. D. thesis, Princeton University, 1967. The optimization routine continues until it no longer improves the objective function, or the maximum number of passes through the optimization routine has been reached or the allowed time expires. Although a conjugate gradient optimizer has been described, other optimizer routines may be used with the objective function options of table I for optimization of a circuit design. For example, the optimizer routine of R. Fletcher and M. J. D. Powell, entitled A Rapidly Convergent Descent Method for Minimization," British Computer Journal, Volume 6 (1963), pages 163 through 168 may be used. Another example of an acceptable optimizer routine mentioned in the Fletcher and Powell article is a direct search optimization routine commonly identified as the Spider routine. The latter routine is described in detail in a paper by R. Hooke and T. A. Jeever, entitled "Direct Search Solution of Numerical and Statistical Problems, Jour- Power Gain-NCVP=1, phase is same as for NCVP=4 G=10 Lo (CABS(Z(IOUT, IIN))**2*ABS (REAL YL)* REAL(YS)*4.))=1() Log Les.

uv ill 0 Current Gain and PhaseNCVP- 2 (1:20 Log (CABS(A)) P=ARG(A) Voltage Gain and Phase NCVP=3 r ut A= Z (IOUT, IIN)/Z (IIN, IIN) G=20 Log (CAB(A)) P=ARG (A) Source Voltage Gain and Phase NCVP=4 G=20 Log CABS (A) P=ARG (A) Phase deviation PD, is calculated from the phase, P; frequency, FR; PFLOAT; and SFLOAT as follows:

PD=PPFLOATSFLOAT*FR Mismatch SourceSet A YS and L=IIN LoadSet A=YL and L=IOUT MM=10 Log(ABS(4.*REAL(A)*REAL(1./Z(L,

L) A))*CABS(Z (L,L))**2) 10 LO 4*VSWR (vsWR+1 Input Admittance YIN= 1000.*(1./Z(IIN, IIN) YS) Output Admittance YOUT=1000.*(1.Z(IOUT, IOUT) YL) Input Impedance ZIN= 1./(1./Z(IIN, IIN) YS Stability Factor For the stability factor option, Y2B2(1,1) and Y2 B2 (2,2) have the source and load substractcd out i.e.

Y2B2(1,1)=Y2B2(1,1)YS Y2B2(2,2) Y2B2(2,2) YL For loaded stabilit factor they are not modified SF: (2.*REAL Y2B2(1,1))*REAL(Y2B2(2,2))

REAL(Y2B2(1,2)*Y2B2(2,1))/CABS(Y2B2(2,1) *Y2B2(1,2)) Input VSWR DUM=CABS(2.*REAL(YS)*Z(INN, INN)1.0) VSWR= (1+DUM)/(l-DUM) Output VSWR-substitute YL for YS and IOUT for IIN in input VSWR. Reflection loss and phase angle RHO=2.*YS*(INN, INN)1. ANGLE=.ARG(RHO) LOSS=20 Log (CABS(RHO)) N (gs; figure and Noise Parameters unu ce oot TABLE II Definition of terms Z-MATRIX-A matrix Z(I,J), where I and J are node numbers, defined by the equation V=ZI where V is the vector of node voltages and I is the vector of node tenants. rmal yse le the ,immdm tamatsix.--

Table ll- Continued -ZSThe source impedance.

IINThe number of the input node.

IOUTThc number of the output node.

Modes-Various states which a circuit may alternate between. For example in a phase shifter, two modes might be the phase shift mode and the 22.5 phase shift mode.

Y2B2(I,J)A two by two matrix of admittances formed by taking the inverse of the matrix Z(IIN,IIN) Z(IIN,IOUT) Z(IOUT,IIN) Z(IOUT,IOUT) ABSA function which means take the absolute value of the quantity in parenthesis.

CABS-Same as ABS except the quantity in parenthesis is complex.

CON J G-A function which means take the conjugate of the quantity in parenthesis.

ARGThe polar angle of the complex quantity in parenthesis.

GFLOATGFLOAT is a variable which provides a floating reference for the gain of a circuit when optimizing. This allows one to do such things as maximize the flat gain of an amplifier over some frequency band.

PFLOATPFLOAT is a variable which provides a floating reference for the phase of a circuit when optimizing.

SFLOAT-SFLOAT is a variable which provides a floating reference for the slope of the phase of a circuit when optimizing. Used in conjunctionwith PFLOAT and a specified phase curve, it allows one to fit the phase deviation from linear to a specified curve.

KIND NUMBER'The type of an element (e.g. re-

sistor, capacitor, etc.) is specified in the Program Listing by a KIND number. (See page 22.)

KIND numbers Element Type:

Black box (up to ten kinds of black boxes allowed) 1-10 Resistor 11 Capacitor 12 Inductor 13 Series transmission lineBL 15 Shorted transmission lineBL 16 Open transmission lineBL 17 Series lossy transmission lineBL 18 Shorted lossy transmission LineBL 19 Open lossy transmission line-BL 20 Open radial lineOuter radius 23 Parameter Type:

Characteristic admittance 14 Attenuation for lossy line 40 Guided to freespace wavelength 4 Inner radius for radial line 42 Angle for radial line 43 Thickness of substrate material 44 Dielectric constant of substrate 45 1 If an element is in a series branch, add 200 to its KIND number.

Of particular significance to the improvement of a circuit design in accordance with the present invention is the various options available for generating the objective function. These objective function options result in the generation and storage of a value which depends on the sum of a power function of the difference between a specified performance characteristic and a calculated performance characteristic beyond a specified tolerance. Further, a circuit may be adjusted at a particular frequency such that the difference between a specified performance and a calculated performance is zero. In addition, where applicable, the calculated performance can be made to be greater than or less than a specified performance characteristic at a given frequency. Consider options 1 and 2 listed in table l. These two options are the same with the exception that for the second option GREF and NEQGRF (an index) are always zero. Let:

A2Uk) A 1(f otherwise; then the contribution of option 1 or option 2 to the objective function is:

Thus for the gain options 1 and 2, the calculated performance characteristic may be made to equal, be less than, or greater than the desired performance characteristic. Similarly. for option 7. a calculated attenuation versus frequency curve may be made to fit a specified curve to the degree required.

Referring again to that portion of the flowchart for the optimization of aselected circuit topology. Input data in the form of a selected circuit topology and objective function op tions are inputted to the memory 46 along with the number of passes (N through the optimization routine and the frequency points (K) to be evaluated.

The optimization routine of Donald Goldfarb is as follows:

Let the current point be .r' with a function value of f(.t') and a gradient g'=g(x'). It is assumed that x is in R and lies in the ('afi'lne) subspace M determined by the intersection of q linearly independent hyperplanes. The matrix operator H is therefore H The conjugate-gradient algorithm is then:

lfH;,'g"=0 and 01 0, then x is global maximum.

If the former holds proceed to step (3). if the latter applies, drop-the q"' hyperplane from the constraint basis and obtain H from H n n; 'HJ i q i lllllllllo Set i=i+l and return to step l If the initial feasible point is an interior point of the allowable convex region R, H is initially chosen to be any positive definite symmetric matrix, usually I the identity matrix. However, if the initial point lies on the boundary B on exactly q linearly independent hyperplanes H,, is set equal to P,,.

In the above algorithm, b, is the right-hand side of constraint; b is the i" diagonal element of (N N Y fis the objective function; g is the vector gradient; n, is the unit normal to j" constraint; P is the number of constraints; q is the number of constraints in basis; s is the conjugate gradient direction s=H,,g,' y is the difference in gradients between neighboring points y=g 'g; x is the solution variable vector; B is the boundary of feasible region; H is the non-Euclidean projection operator basic to the conjugate gradient algorithm; I is the identity matrix; M is the linear manifold formed by the intersection of q linearly independent hyperplanes; N is the mXq basis matrix whose columns are the q linearly independent unit normals n,, i=1, q; P is the Euclidean projection operator which maps E'" onto M,,, where: P =I-N (N 'N "N -R is the feasible region; a is the vector of Lagrange multipliers (shadow prices) aqN N f N 'g; y is bound on the quadratic term in the equation where: f( )=f( 0)+( a)'g( o)+( o)'( 2/ 10) where g(x,,) is the gradient of f(x) at x,,;

7 is the scalar denoting distance in direction s; A is the distance in positive s direction to nearest constraint (defined in the equation where:

Set c"+ =x+ ds" and compute }+=g(x k is the total number of inequality constraints; o is th e distance along conjugate gradient direction to maximum in that direction o"=y's'.

Assuming the use of a computer, such as the UNIVAC l 108, to optimize the selected circuit topology, a program listing of instructions to generate an objective function and its gradient for use in an optimization routine, such as that of Donald Goldfarb, is given in table Ill. The language of the program is FORTRAN 5. Instructions 36 through 40, 42 through 58, through 70, 83 through 84, and 90 through 96 are scaling and timing instructions which are not required to generate an objective function and have not been included in table Ill. Other instructions which may not be self-explanatory are explained in table lV.

After the computer has carried out instructions 1 to 249, the objection function and its conjugate gradient are called by an optimizer program (block 56) that optimizes and adjusts the circuit topology design variables, as explained. If the circuit has not been optimized to the desired level or the programmed number of passes (N) has not been exceeded, the computer again utilizes instructions 1 through 249 of the program listing to generate a new objective function and conjugate gradient using the adjusted circuit element values. The new objective function and conjugate gradient are again called by the optimizer program to again optimize the circuit topology by adjusting circuit design variables. This sequence continues until the circuit is optimized to the desired level or the number ofpasses equals the programmed number (N).

TABLE II I Program Listing KALPHA, ITYPE ITYPEI ICARD IIUSER, I M ODI ILIST ,USERN, IERR, IREDO, IOCARD ISECUR COMMON/MATRIX/Y(50,50) ,ZCJG(51) ,Cl(50) ,C2(50) ,c3(5o) ),XMIN(200) ,XMAX(200) ,TOL(200) r ,26) ,XLOAD(2,26) ,NSO,NLO,NNT,

1 SUBRQUTINE OBJ'IIV 2 c 3 COMMON/SPECS/GTOL,SPECIN,SPECOT 4 COMMON /CONTRL IFACT(6) ICODE,IBEGIN, 5 6 REAL NF,LMDALO g COMPLEX 9 INTEGER*2 NDBR1,NDBR2,INDEX 10 COMMON G(50) ,x(20o) ,F,N,NSPI 11 COMMON/ERASE/E(6) 12 Cll (5 13 COMMON/CALl/DES(200, 2 NCOD(200), 1 1 1 NELE(200) ,NSTR(200) 15 COMMON/GAIN/GN,DGN(50) ,GL,PZ,DPZ (50) 16 OOMMON/G'ENRAL/OMEGA,DGRGEN(5O) 17 OOMMON /DDT/SOURCE(2 NAME(20) ,LOCATE 18 1(11), BBOX(l600) 19 DIMENSION IBBOX(1600) 20 EQUIVALENCE (IBBOX,BBOX) 21 COMMON/TITLEl/TITLE (18) 22 COMMON/NOISE/NF,DNF(51) ,YBRNCH(50, l),NDBRl(50) NDBRZQQLN R H Table ill-Continued 23 1 GO TO 717. 235 716 IF(DUM.GT.3.l i159265) GO TO 718 236 DUM DUM 6.2831853 237 GO TO 716 238 718 DUM PZ PHASE(KREF) DUM 239 IF(ABS(DUM) .GT. 1.7) DUM DUM SIGN(6.283185 ,DUM) 2 10 AUM=ABS(DUM)PTOL 2 81 IF(AUM.LE.O. )GO TO 7 1 242 DUM=SIGN(AUM,DUM) 2 43 F=F-CONOPF(JN)*DUM*DUM 2 M GDUM=2. *CONOPF(JN)*DUM 2 DO 1012 I=l,N 2 46 1012 G(I)=G(I)-GDUM*DPZ(I) 2 17 7 1 CONTINUE 2N8 GO TO 1002 2 19 1002 CONTINUE TABLE IV TABLE IV-Cominued Instruction Instruction number Explanation number Explanation 86 This instruction calls for a subroutine to form the Y-matrix "189 This instruction calls for the same subroutine as called by of the selected circuit topology at a frequency K and for Instruction 89 to be used in conjunction with Instruction 89 Tl iis irfgtr i i t i n calls for a subroutine to invert the Y- 193 Tgs instruction calls for the same subroutine as called at matrix of Instruction 86 and to form the Z-matrix. Instruction 117. 117 This instruction calls for a subroutine to calculate the gain 194 This instruction calls for the same subroutine as called by at a frequency KR. Instruction 118. 118. This instruction calls for a subroutine to calculate the 212 This instruction calls for a subroutine that generates a derivative of the gain calculated at Instruction 117 at a deviation of the Z-matrix of a circuit from some specified frequency KR. Zrnatrix This subroutine is given in Table V. 152 This instruction calls for a subroutine to calculate the noise 217 This instruction calls in a subroutine to calculate the gain figure for the mode under conssideration. and phase of the selected circuit topology at a frequency 153 This instruction calls for a subroutine to calculate the KB.

derivative of the noise figure with respect to the element 218 This instruction calls for a subroutine to calculate the values. derivative of the gain and phase for a selected circuit 166 This instruction calls for a subroutine to calculate the topology atai'requency KR.

mismatch and the derivative 01' the mismatch at the source (Kind X-l indicates source) and a frequency KR. Nora 1.The margin numbers at Instruction 117, 142, 146, 152, 165, 175, 172 This instruction calls for Instruction 166 to be stored in the 184, 212, and 216 refer to the objective function options listed in Table I. array DGRGN. NOTE 2.Any oi the subroutines called by the program for one objec- 176 This instruction calls for a subroutine to calculate the tives function will not be called for another objective function since the mismatch and the derivative for the load (Kind X-2 calculation is already stored. indicates load) at a frequency KR. NOTE 3.Instructions 1-35 establish common areas, equivalencies 182 The mismatch calculated at Instruction 176 is stored in and type statements.

the array DGRGN. l 1 188 This instruction calls for the same subroutine as called at I igiflllslftflon 86 to be evaluated at additional frequency TABLE V Program Listing 1 SUBROUTINE FITYOZ 2 COMPLEX DELZ,DZ (2,2) ,Y(2,2) ,DY(2,2) ,DUM(2,2) 3 INTEGER* 2KIND NODEl NODE2 ,NODE3 ,NCOR i COMPLEX ZCJG,Cl,C2,C3,C i 5 COMMON /MATRIX/ Z (50,50) ,ZCJG(51) ,C1(50) ,C2(50) 3(5 (5 6 COMMON/ELEMET/KIND(200) ,NODE1(200) ,NODE2(200),NODE3(200) NCOR(200) 7 COMMON C() ,X(200) ,F,M 8 COMMON/MATCH/NAMEY(2),NZOY,WEIGHT(8),ZTOL LZOY,SECPZY 9 COMMON/SUBCOM/ABM) ,KINDS,K,WF,Y1,Y2,Y3,Y5 10 COMPLEXZ,Yl,Y2,Y3,Y i,Zl,Z2,Z3,Z i,ZSl,ZS2,ZS3,ZS l ll COMMON/INDEXl/NSWl,NSW2,NCVP,NBL,NTOTAL,NNODE,MPLOT,

NREF,MREORD, 7 12 l INDEX(50,2) ,NTO'I',NVAR,NLARGE,NGO l3 INTEGER*2 INDEX l l EQUIVALENCE (DY(1,1) ,DZ(1 ,1) (Y(1,1) ,Zl) (Y(1,2) ,Z2)

,Z3) 5 .(Y4 2 a DOG Table V-Conlinued KINDS LZOY SAvE= x(2oo) x(200) SECPZY CALL GENFIT GENFIT FINDS y OF BLACK B0X KI-NDS=LZ0Y x(200) SAVE SAVE THE FOLLOWING, A VALUES WHILE FORMING 2BY,2'-Y,Z ZSl z(1,1)

ZSA. z(2,2)

GO'TO (1,2),NZOY

1 FITY, 2FI'I'Z z(1,2) Z(l,NNODE') Z (NNO z(2,2) Z'(NNODE,NNODE) THE 2 MATRIX IS Now; CoNvERTED TOI-THELY MATRIX. FOR THE CIRCUIT CALLv CMTINV(2,2)

THE FOLLOWING A. VALUES ARE YH'S GO TO 3 21 z,(1,1)

TURN MATCHING MATRIX. To A -z, MATRIX CALL CMTINV(2,2) THE FOLLOWING A VALUES ARE 2 's THE ABOVE l STATEMENTS RETURN TO- ORIGINAL VALUES ZSl STORES THE DIFFERENCE IN Y="S' FOR NZOY =l Z Sl STORES, THE DIFFERENCE IN Z 'S FOR"NZO Y=-2 D0 201 4 I=l,M

THE FOLLOWING DOUBLEDO LOOP CALCLATES THE GRADIENT OF Z;W .R .T.ELE

MENT I *REAL(ZS3 )*-REAL(DY (DY(2 ,1) )+WEIGHT(7 *REAL (-23 1 *REAL (2,1))+WEIGHT(6)* 133 3AIMAG(ZS3)*AIMAG (DY(2,2))+WEIGHT 13 1 l(8)*AIMAG( ZS l)*AIMAG(DY(2,2))) *SIGN 135 1 CONTINUE 136 RETURN 137 .END

TABLE VI.EXPLANAT1ON OF INSTRUCTIONS OF TABLEV Instruction number Explanation 20 This instruction calls for a subroutine to generate a specified 2Sianatrix (black box matrix) as explained at Instruction 34 This instruction calls for a subroutine to invert the Y- matrix of Instruction 20.

50 This instruction calls for the same subroutine as called by Instruction 34.

127 This instruction calls for a subroutine to multiply the Y- matn'x bythe derivative of the Z-matrix and stores the result in array D UM. This instruction is skipped if the routine is calling for a Z-matrix fit.

128 This instruction calls for a subroutine that multiplies tho Y-matrix by the derivative of the Y-matrix and stores the result in array DUM.

136 This instruction returns the computer to Instruction 74 of Table III.

NoTE.Instructions 30 through 40 and 41 through 55 are alternate setts loftilnstmctions. Either one or the other of the sets will be used, but no 0 After a given circuit topology has been optimized in a routine that generates and stores an admittance matrix .and its derivatives and forms an objective function and its derivative. coded information representing the circuit topology and-the final circuit element values are transferred to an analysis subroutine. In particular, the information is transferred to an analysis information section 58. The circuitis now analyzed at selected frequency points and in accordance with selected analysis options listed in table VII. For each selected frequency, the final optimized circuit and the circuit element values are analyzed (block 60) to determine the final circuit performance. After analysis at the last frequency point (k,,,,,,.) coded information representing the final circuit is transferred to either a calculator-computer plotter 62, a circuit layout routine 64, or readout and stored. At the completion of any of these last three options, a signal is transferred to the memory 46 to begin the optimization routine on another selected circuit topology.

mpor vswR ourrur VSWR neruscreo PHASE ANGLEIdegre'es) REFLECTION-LOSS INPUTRESISTANCE ('ohms) mrur REACTANCE (ohms) LOADED STABILITY FACTOR USER SUPPLIED OPTION NOISE PARAMETERS PHASE DEVIATION s1 1 s12 s21 s22 Y] 1 v12 v21 v22 *NCVP= l for. power gain, for phase of source voltage gain 2 for current gain 3 ltbr yoltaggain =1 for source toload voltage gain.

Referringto'zF-IG. 4, the circuit illustrated is an example of a typical topology that may be optimized by the method of the presentinvcntion. The circuit includes shorted transmission lines 20, 8a, llaand 160. In addition, the circuit includes series transmission lines 4a, 6a, 104 and 14a. Two transistors 17a and 180 complete a two-stage broad band amplifier. Assume that .the elements and parameters have the starting values given in table VIII with the characteristic admittances Y.) in millimhos and electrical le'ngths'(B, measured in fractions of a wavelength at L5 6112. The source impedance is fixed at 20.'000+.I.000 millimhos and the load impedance fixed at 20.000+J.000 millimhos. Elements 17a and 180 are transistors with the following S parameters:

Frequency S11 S12 S21 S22 NQ (DB) RN YOPT TABLE VII. OPTIONS FOR ANALYSIS GA1NTYPE DETERMINED BY NCVP*-(db.) NOISE FIGURE-(db.)

MISMATCH AT SOURCE-(db.)

MISMATCH AT LOAD-(db) INPUT CONDUCTANCE-( mmhos) INPUT SUSCEPTANCE (mmhos) OUTPUT CONDUCTANCE (mmhos) OUTPUT SUSCEPTANCE (mmhos) STABILITY FACTOR PHASE-TYPE DETERMINED BY NCVP* (degrees) This is fit to a fifth order polynomial in frequency Referring to table I, options l, 3 and 4 have been selected for the objective function, each having an equal weight distribution. This circuit was optimized at the following eight frequencies:

TABLE \III Nodes Maxi- Element Kind Starting Minimum mum number code Description 1) (2) (3) NC R value bound bound Tolerance 1 GFLOAT 0 0 0 0 20. 0000 18.0000 25.0000 .000000 16 L SIBl 1 0 0 1 287185 100000-01 490000 600000-01 14 Y SE R1 1 2 -0 4 10. 040 10.0000 30. 0000 .500000-01 15 L SERI 1 2 0 3 705181-01 100000-01 240000 .500000-01 14 Y SE R2 3 4 0 6 10.0000 10.0000 30. 0000 .500000-01 15 L SE R2 3 4 0 5 165011 100000-01 240000 500000-01 14 Y STB2 4 0 0 8 10.00000 10. 0000 30. 0000 .600000-01 16 L S'IB2 4 0 0 7 211851 100000-01 490000 600000-01 14 Y SE R3 4 5 0 18. 4430 10. 0000 30. 0000 500000-01 L SER3 4 5 0 9 600000-01 500000-01 240000 500000-01 14 Y STB3 5 0 0 12 10.0000 10.0000 30. 0000 .500000-01 16 L STB3 6 0 0 11 827344-01 100000-01 490000 500000-01 14 Y SE R4 6 7 -0 14 17. 6546 10.0000 30. 0000 500000-01 15 L SE R4 6 7 0 13 978295-01 100000-01 240000 500000-01 14 Y STB4 7 0 0 16 15. 8530 10.0000 30. 0000 .500000-01 16 L STB4 7 0 0 16 714040-01 100000-01 490000 500000-01 14 Y STBl 1 0 0 2 22. 9142 10.0000 30. 0000 500000-01 1 TRAN-2 5 6 0 0 000000 00000 00000 000000 1 TRAN-1 2 3 0 0 .000000 .00000 00000 000000 NOTE.-Unlcss Otherwise specified TABLE IX Ele- Optimized Range of X ment values No Description of X Lower Upper 19 GFLOAT 18. 00000 18. 00000 25. 00000 2 L S'IBl 26979 .01000 49000 3 Y SERl 10. 00000 10.00000 30. 00000 4 L SERI 03479 .01000 24000 5 Y SER2 10. 00075 10. 00000 30. 00000 6 L SER2 13969 .01000 24000 7 Y STB2 10. 00000 10. 00000 30. 00000 8 L S'IB2 .27803 01000 .49000 9 Y SER3 19. 21691 10. 00000 30. 00000 10 L SE R3 05451 05000 24000 11 Y STB3 10. 00000 10. 00000 30. 00000 12 L STB3 11538 .01000 .49000 13 Y SER4 10. 92270 10. 00000 30. 00000 14 L SER4 13994 01000 24000 15 Y S'1B4 15. 35098 10. 00000 30. 00000 16 L STB4 08314 .01000 49000 1 Y STBl 21. 60968 10. 00000 30. 00000 TABLE X VSWR Frequency Gain (db) N F (db) Phase In Out TABLE XI.DIMENSIONS OF TRANSMISSION LINES IN IN CHES [FREF=1.50000] through NCOR. the following parameter values are used: ATEN= .40000-01; LMDALO=.40000; RINNER=.10000-01; H=.20000-01; ER=9.6000.

After completion of twenty optimization passes through the routine (N=20). the optimized values of the circuit elements are given in table IX. Using the values of table IX and analyzed for a power gain (NCVP=I the analysis results are given in table X. In addition to optimization and analysis results, a computer for optimization of the circuit of FIG. 4 also generated a readout giving the dimensions in inches for the transmission lines. These are listed in table XI and comprise the information used by the layout option 64, which may be a Gerber Plotter, to produce a pattern for fabricating the illustrated circuit.

In addition to optimizing a circuit of the type shown in FIG. 4, the method of the present invention may also be used for optimizing a circuit that has several switching states or modes. that is. elements that may be switched into and out of the circuit. Referring to FIG. 5, a circuit is shown having four switching modes or states. An input impedance 88 connects directly to one pole of a double-pole double-throw switch 90 and to the second pole through an inductor 92. Each branch of the circuit shown includes a resistor 94 in series with a capacitor 96. The first four branches are interconnected and connect directly to one pole of a double-pole double-throw switch 98 and to the second pole through an inductor 100. The second four branches are interconnected to an output impedance 104. Again, the circled numbers are the nodes for analysis and admittance matrix generation for the optimization routine.

Optimization of a multimode circuit of a type illustrated in FIG. 5 is similar to the optimization of a single-mode circuit. In addition to the previously described input information to the memory 46, a multimode circuit requires information identifying the number of modes. With reference to the program listing of table 111, the data processor completes instructions 1 through 249 for mode one with the matrix generated from the circuit elements in the circuit in the first mode. This same routine is repeated for mode two using the circuit elements of the second mode to generate the admittance matrix and its derivative with respect to the design variables. For the circuit of FIG. 5, the routine set out in table 111 is repeated four times. Upon completion of the fourth mode, a composite value of the objective function and a composite value of its conjugate gradient are generated and stored for use by the optimizer routine of block 56.

In the optimizer routine, all the circuit elements in the various modes may be adjusted in a manner and a direction dependent upon the objective function and its conjugate gradient. If additional passes are to be made through the optimization routine, the program listing of table 111 is again used to evaluate the circuit in each of its four modes. In the logic flow chart of FIG. 3. the multimode instructions appear immediately below the optimizer routine block 56.

Comparing the optimization routine ofa multimode circuit generation of the objective function and its conjugate gradient. The same options as given in table I may be used for generating the objective function. in a single mode circuit, the subroutine given in table III is completed once for each optimization pass. For a multimode circuit, the subroutine of table I1] is repeated once for each mode for each optimization pass.

Having described the invention in accordance with applicable United States statutes, we claim:

1. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing a value of said continuous objective function which depends. on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

c. modifying at least one of the design variables in a direction and by an amount dependent on said objective function to improve the generated and stored value thereof.

2. The method of designing a circuit by an automated data processing machine as set forth claim 1 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greaterthan. less than or equal to difference between the specified performance characteristic and the synthesized performance characteristic.

3. The method of designing a circuit by an automated data processing machine as set forth in claim 1 including repeating steps (a), (b) and (c) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

4. The method of designing a circuit by an automated data processing machine as set forth in claim 3 including the step of analyzing the selected circuit topology at thefinal values of the circuit elements.

5. The method of designing a circuit to, improvethe operation thereof for at least one performance characteristic by an automated data processing machine having input-thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function wherein a synthesized performance characteristic 7 may be less than, greater than, or equal to a specified performance characteristic, and

c. modifying at least one of the design variables in a direction and by an amount dependent on said objective function to improve the generated and stored value thereof.

6. The method of designing acircuit by an automated data processing machine as set forth in claim including repeating steps (a), (b) and (c) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

7. The method of designing a circuit by anautomated data' processing machine as set forth in claim 6 including the step of analyzing the selected circuit-topology at the final values of the circuit elements.

8. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processingmachine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analyticalobjective function for a circuit of a selected topology and initial element values,

b. generating and storing representations of analytical derivatives of said objective function with respect to design variables,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

d. modifying at least one of the, design variables in a direction and by an amount dependent on said objective function and said representations of the analytical derivatives to improve the generated and stored value of the objective function. i

. 9. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the generated and stored value of said continuous objective function depends on the sum, over a'range of frequencies, of a power function. of the difference between a specified performance characteristic and a synthesized, performance characteristic beyond preset limits and a greater than, less than or equal to difference between the specified performance characteristic and the synthesized performance characteristic. 10. The method of designingacircuit by an automated data processing machine as set forth in claim 9 including repeating steps (a), (b), (c) and (d) for a preselected number of passes utilizing thegdesign variables as modified in the previous pass to generate andstore a new objective function and to further improve the-generated and stored value of the objective function.

11. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous objective function is modified by ignoring the differences betweensaid specified performance characteristic and said synthesized performance characteristic within a selected tolerance band at selected frequencies over said range of frequencies.

12.The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous analytical objectivefunction is modified by ignoring negative" differences between .said specified performance characteristic and said synthesized performance characteristic at selected, frequencies over said range of frequencies.

13. The method of designinga circuit by an automated data processing machine; as set forth in claim 9 wherein the continuous analytical objective function is modified byignoring positive differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

14. The method of designing a circuit by an automated data processing machine as set forth in claim 9 wherein the continuous analytical objective function is modified by ignoring 0 differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

15. The method of designing a circuit by an automated data processing machine as setforth in claim 8 wherein the continuous analytical objective function comprises at least one of the options selected from the following options:

wherein the calculated gain GN at sampled frequencies f is least-squared-error fit to the a reference gain GREF:

b. f ;,.(GN(f,,.)-CvFL.OAT) wherein the calculated gain GN at sampled frequencies 1}. is least-squared-error fit to a floating flat reference gain GFLOAT;

2 c. fu(GFLOATGFLQATMAX) wherein GFLOATMAX is the maximum limit of the amplitude of a floating reference gain GFLOAT and GFLOAT is maximized at sampled frequencies f d. fi-(Nf-(flkSPl-ZCNF) wherein the calculated noise figure NF at sampled frequencies f}. is least-squared-error fit to a reference noise figure SPECNF;

it-(misus wherein the calculated source mismatch MMS at sampled frequencies f is least-squared-error fit to zero source mismatch;

Z. f.7, .(MML(fl wherein the calculated load mismatch MML at sampled frequencies f is least-squared-error fit to zero load mismatch;

22 g. f 1fe(GN(f +Afe)GREF(Afe)) wherein the calculated gain GN at sampled frequencies 11- +A fe, where f are center frequencies and Afe define a distribution of sampling about such center frequencies, is leastsquared-error fit to a reference gain GREF;

ZSPECZI ZSPECZZ where "N is the node number assigned to the input node and IOUT is the node number assigned to the output node; and

ZSPECl l i. j PHU),)PHREF(/).)PFI..OATSFLOAT"fl) wherein the calculated phase PH at sampled frequencies f is least-squared-error fit to a reference phase PHREF and where PFLOAT and SFLOAT are optimization parameters.

16. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring negative differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

17. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring positive differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

18. The method of designing a circuit by an automated data processing machine as set forth in claim 8 wherein the continuous analytical objective function is modified by ignoring differences between said specified performance characteristic and said synthesized performance characteristic at selected frequencies over said range of frequencies.

19. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values,

b. generating and storing representations of analytical derivatives of said objective function,

e. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function wherein a synthesized performance characteristic may be less than, greater than, or equal to a specified performance characteristic, and

d. modifying at least one of the design variables in a direction and by an amount dependent on said objective function and said representations of the analytical derivatives to improve the generated and stored value of the objective function.

20. The method of designing a circuit by an automated data processing machine as set forth in claim 19 including repeating steps (a), (b), (c) and (d) for a preselected number of passes utilizing the design variables as modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the objective function.

21. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing representations of an admittance matrix of the selected circuit topology and initial element values,

b. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial element values with said admittance matrix,

c. generating and storing a value of said continuous objective function which depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits, and

d. modifying at least one of the design variables in a direction by an amount dependent on said objective function to improve the generated and stored value thereof.

22. The method of circuit design by an automated data processing machine as set forth in claim 21 including:

e. generating and storing representations of analytical derivatives with respect to the design variables of said objective function and wherein the design variables are modified in part by an amount dependent on said analytical derivatives and said objective function.

23. The method of circuit design by an automated data processing machine as set forth in claim 22 including repeating steps (a), (b), (c), (d) and (e) for a preselected number of passes using values of the design variablesas modified in the previous pass to generate and store a new objective function and to further improve the generated and stored value of the new objective function.

24. The method of designing a circuit by an automated data processing machine as set forth in claim 23 wherein the generated and stored value of said continuous objective function depends on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic beyond preset limits and a greater than, less than, or equal to difi'erence between the specified performance characteristic and the synthesized performance characteristic.

25. The method of designing a circuit to improve the operation thereof for at least one performance characteristic by an automated data processing machine having input thereto a representative circuit topology and initial values of all design variables comprising:

a. generating and storing a representative continuous analytical objective function for a circuit of a selected topology and initial values at one of the operating modes,

Non-Patent Citations

Reference | ||
---|---|---|

1 | * | Computer-Aided Design of Microwave Integrated Circuits; IEEE-Wescon Tech Papers; Vol. 13 pt. 2; Session 6/6/69; pp. 1 3; Houston, Dyer, & Policky |

2 | * | Design of Digital Loaded-Line Phase-Shift Networks for Microwave Thin-Film Applications; IEEE Transactions on Microwave Theory and Techniques; Vol. MTT-16, No. 7; July 1968; Frances L. Opp and W. F. Hoffman |

3 | * | Optimal Design of Matching Networks for Microwave Transistor Amplifiers; IEEE Transactions on Microwave Theory and Techniques; Vol. MTT 14; pp. 696 698; Dec. 1966; F. E. Emery and M. O Hagan |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US4447881 * | May 29, 1980 | May 8, 1984 | Texas Instruments Incorporated | Data processing system integrated circuit having modular memory add-on capacity |

US4495559 * | Nov 2, 1981 | Jan 22, 1985 | International Business Machines Corporation | Optimization of an organization of many discrete elements |

US4580228 * | Jun 6, 1983 | Apr 1, 1986 | The United States Of America As Represented By The Secretary Of The Army | Automated design program for LSI and VLSI circuits |

US4628471 * | Feb 2, 1984 | Dec 9, 1986 | Prime Computer, Inc. | Digital system simulation method and apparatus having two signal-level modes of operation |

US4635208 * | Jan 18, 1985 | Jan 6, 1987 | Hewlett-Packard Company | Computer-aided design of systems |

US4916627 * | Dec 2, 1987 | Apr 10, 1990 | International Business Machines Corporation | Logic path length reduction using boolean minimization |

US4989132 * | Oct 24, 1988 | Jan 29, 1991 | Eastman Kodak Company | Object-oriented, logic, and database programming tool with garbage collection |

US5020009 * | Mar 22, 1989 | May 28, 1991 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for preparing measurement specifications of electronic circuits |

US5047971 * | Aug 15, 1989 | Sep 10, 1991 | Intergraph Corporation | Circuit simulation |

US5113352 * | Jun 20, 1989 | May 12, 1992 | Digital Equipment Corporation | Integrating the logical and physical design of electronically linked objects |

US5257201 * | Aug 14, 1989 | Oct 26, 1993 | International Business Machines Corporation | Method to efficiently reduce the number of connections in a circuit |

US5282148 * | May 23, 1989 | Jan 25, 1994 | Vlsi Technology, Inc. | Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic |

US5377122 * | Nov 1, 1993 | Dec 27, 1994 | Lsi Logic Corporation | Logic compiler for design of circuit models |

US5497337 * | Oct 21, 1994 | Mar 5, 1996 | International Business Machines Corporation | Method for designing high-Q inductors in silicon technology without expensive metalization |

US6282693 * | Dec 16, 1998 | Aug 28, 2001 | Synopsys, Inc. | Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer |

US6301693 * | Dec 16, 1998 | Oct 9, 2001 | Synopsys, Inc. | Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer |

US6662348 * | Jul 20, 2001 | Dec 9, 2003 | Synopsys, Inc. | Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer |

US6671859 * | Jan 24, 2001 | Dec 30, 2003 | Synopsys, Inc. | Non-linear optimization system and method for wire length and delay optimization for an automatic electronic circuit placer |

US7114134 | May 27, 2004 | Sep 26, 2006 | Veri Silicon Holdings, Co. Ltd | Automatic circuit design method with a cell library providing transistor size information |

US7131097 * | Sep 24, 2002 | Oct 31, 2006 | Altera Corporation | Logic generation for multiple memory functions |

US7254802 | May 27, 2004 | Aug 7, 2007 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |

US7260562 * | Jun 30, 2003 | Aug 21, 2007 | Intel Corporation | Solutions for constraint satisfaction problems requiring multiple constraints |

US7426710 * | Nov 15, 2005 | Sep 16, 2008 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |

US8347261 * | Sep 9, 2010 | Jan 1, 2013 | Cadence Design Systems, Inc. | Method and system for implementing graphically editable parameterized cells |

US20050010922 * | Jun 30, 2003 | Jan 13, 2005 | Greg Czajkowski | Solutions for constraint satisfaction problems requiring multiple constraints |

US20050278658 * | May 27, 2004 | Dec 15, 2005 | Xiaonan Zhang | Standard cell library having cell drive strengths selected according to delay |

US20050278659 * | May 27, 2004 | Dec 15, 2005 | Xiaonan Zhang | Cell library providing transistor size information for automatic circuit design |

US20050278660 * | May 27, 2004 | Dec 15, 2005 | Xiaonan Zhang | Automatic circuit design method with a cell library providing transistor size information |

US20060107239 * | Nov 15, 2005 | May 18, 2006 | Verisilicon Holdings, Co., Ltd. | Standard cell library having cell drive strengths selected according to delay |

US20110061034 * | Sep 9, 2010 | Mar 10, 2011 | Cadence Design Systems, Inc. | Method and system for implementing graphically editable parameterized cells |

WO1984002050A1 * | Nov 3, 1983 | May 24, 1984 | Int Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |

Classifications

U.S. Classification | 716/102, 968/579, 716/106, 716/135 |

International Classification | G04C19/04, G06F17/50, G04C19/00 |

Cooperative Classification | G06F17/5063, G04C19/04 |

European Classification | G04C19/04, G06F17/50D8 |

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