US 3623069 A
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United States Patent  Inventor Ancile E. Malden Potomac, Md. [211 App]. No. 878,713  Filed Nov. 21, 1969  Patented Nov. 23, 1971  Assignee international Business Machines Corporation Armonk, N.Y.
 MULTIPLEX CHARACTER GENERATOR 35 Claims, 18 Drawing Figs.
 [1.5. CI 340/324 A, 340/ l 7215  Int.Cl G06f3/14  Field of Search 340/324 A, 172.5; 178/175; 340/324 A, 172.5, 366 R  References Cited UNITED STATES PATENTS 3,109,166 10/1963 Kronenberg et a1. 340/324 A 3,256,516 6/1966 Melia et a1. 340/324 A 3,307,156 2/1967 Durr 340/324 A 3,345,458 10/1967 Cole et a1. 340/324 A 3,396,377 8/1968 Strout 340/324 A mao-ia album-- Primary Examiner-John W. Caldwell Assistant Examiner-Marshall M. Curtis Atlorneyx-Hanifin and Jancin and George E. Clark ABSTRACT: A display system including a symbol generator which consists of a group of segment generators. Each seg ment generator generates a portion of the symbol to be displayed in time sequence so that the segment generator which generates the first portion of the symbol will be free to generate the first portion ofa following symbol or the first portion of a symbol on another display device while the other segment generators are generating the remainder of the first symbol. The outputs from this group of segment generators is transmitted through a group of multiplex gates which assemble the symbols into video data signals for a group of display devices.
The segmented character generator permits the generation of lower case characters, the generation of color symbols and words and expansion or reduction of display cluster sizes with high efficiency.
l234567812345678123456781 23456781234567812345678l23456i8123456781 2345678123456l2345678l 234567812345678 PAIENTEDunv 2 3 1971 SHEET 05 [1F 13 6'2 SYNC GENERATOR CLOCK *VERT SYNC 1 VERT SYNC VERT SYNC 2 VERT SYNC 5 *VERT SYNC4 CTR =VERT SYNC5 VERT SYNCG VERT SYNC 7 VERT SYNC 8 PATENIEDNUV 23 1971 3, 23 069 sum 09 0F 13 FIG. 11
HEXADECIMAL REPRESENTATION OF VIDEO DATA-ROW1 ODD PCG1 18 18 18 18 18 18 18 18 FC 2 7E 7E 7E 7E 7E 715 TE 7E c7 3 c3 c3 c3 c3 c3 c3 c3 (:3 FE
4 FF FF FF FF FF FF FF FF c7 5 C3 c5 c3 c3 c3 (:5 c3 c3 FE HEXADECIMAL REPRESENTATION OF VIDEO DATArROWI EVEN PCGI 36 3c 3C BC 3c 3c 3c 3c FE 2 E7 E7 E7 E7 E7 E7 E7 E7 (:7
3 FF FF FF FF FF FF FF FF FF 4 C3 c3 c3 c3 C3 c3 03 C3 c7 5 C3 C3 C3 C3 C3 C3 C3 C3 FC PATENTEuuuv 23 I97! SHEET 11 HF 13 R m U 5 Mi m v M R V- R 0G LE wum m w im wm o MWWWBM 6 W1 TF w Lm mm m m C S k 7 3 IL 0 8 W 8 F WW WWW W m m W 1 J1 m fl 4 m d ha liiifi i i ???Eiii iiii E E R LATC H FROM REFRESH Com STORAGE PATENTEnuuv 23 Ml 3. 623 O69 SHEET 12 [1F 13 FIG.14 15o ERT 651 t??? V SY1NCH* ENCODER m a saw a g m SYNC MIXER c0L0R- 4 onlon 0R 505 curesoR FROM PARTIAL 833 in, A356 EKS? CHAR 181, a
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1 MULTIPLEX CHARACTER GENERATOR CROSS-REFERENCE TO RELATED APPLICATIONS W. .l. Hogan, et.
BACKGROUND OF THE INVENTION This invention relates to computer connected input/output systems and more particularly to systems for generating symbols for display on display devices in response to information signals from a central processor unit.
In the prior art, symbol generators have been described in which a group of display devices received inputs from a corresponding group of synchronous refresh storage devices such as delay lines or rotating magnetic disks. These synchronous storage devices received as inputs a stream of video information generated by a corresponding group of character generators wherein each character generator generated the complete character for one or possibly two display devices. The inputs to this group of character generators was in the form of parallel digital information usually from some form of temporary storage.
Systems of this nature require many character generators and many synchronous storage elements to generate information for presentation on a large cluster of display devices. Due to limitations of cost and size, systems of this nature were usually limited to a maximum of eight display devices per control unit.
Accordingly, it is an object of this invention to more efficiently generate symbols for presentation on a large cluster of input/output devices.
It is another object of this invention to generate symbols for a large cluster of input/output devices using a single segmented character generator.
Further, it is another object of this invention to generate both upper case and lower case symbols with common apparatus for presentation on input/output devices.
Another object of this invention is to generate graphic symbols for presentation on input/output devices.
Another object of this invention is to generate color information corresponding to each symbol generated.
In an alternate embodiment, it is another object of this invention to generate color information corresponding to each word of symbols generated,
It is a still further object of this invention to generate symbols for a wide-range of I/O device cluster sizes.
SUMMARY OF THE INVENTION Accordingly, to the invention comprises a system for information display which includes a central processing unit for transmitting information to and receiving information from a group of input/output devices, a control unit connected to the central processor unit at one interface and to a group of input/output devices at a second interface for receiving the information to be displayed, storing the information to be displayed, and generating video signals representative of the information to be displayed.
The control unit comprises an interface control means for communicating with the processor unit, storage means for temporarily storing the information received from the processor unit, segment character generation means which includes a group of segment generators each of said segment generators being connected to one of a group of outputs of the storage means and wherein each of said segment generators simultaneously generates predetermined segments of the video representation of symbols to be displayed on a plurality of the input/output devices, and gating means for distributing the outputs from the group of segment generators to the respective input/output devices in proper time sequence.
In one embodiment, a symbol font in which each symbol occupies a block of IO horizontal spaces and sixteen vertical lines of a scanned raster display device is employed. In this embodiment, a segmented character generator which comprises five segment generators is capable of producing video signals for 32 display devices.
Another embodiment, in which two groups of segment generators are employed where one group is operative with the even horizontal lines and the other group is operative with the odd horizontal lines, during a first field and then reversed, odd for even, and vice versa, during a second field of each frame, expands the total capability of the character generation means to provide video signals for 64 display devices using standard television synchronization signal timing.
A still further embodiment contemplates the addition of segment generators to allow for the generation of lower case characters including those characters which have portions below the base line as well as upper case characters to improve the overall efficiency of the display system.
Still other embodiments contemplate the generation of color information to display individual characters or symbols in a range of colors or alternatively to generate color information which corresponds to a given word of symbols to be displayed.
Due to the great flexibility of this invention, apparatus employing the basic segmented character generator can be used to generate video information for raster scan display devices, directed beam display devices, or digital plotters.
The various embodiments and features of the invention and details of operation are defined with particularity in the following specification.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a graphical illustration of the formation of individual symbol patterns for a group of eight display terminals;
FIG. 2 is a block diagram showing a systems environment embodying the invention;
FIG. 3 is a block diagram ofa terminal control unit embodying the invention;
FIG. 4 is a block diagram illustrating a segmented character generator with a refresh storage connected to the inputs of the various segment generators;
FIG. 5 shows a block diagram which illustrates an embodiment of a single segment generator;
FIG. 6 is a block diagram showing the connections between the segmented character generator and a group of parallel to serial registers;
FIG. 6A 'shows in more detail the construction of a representative parallel to serial register;
FIG. 7 is a block diagram showing the generation of the various synchronization and control signals necessary for the operation of the multiplexed character generator;
FIG. 8 is a timing diagram showing the relationship between the vertical synchronization signals used to drive the group of display terminals;
FIG. 9 is a chart illustrating how the video signals for display terminal NO. 1 and display tenninal No. 20 are multiplexed;
FIG. 10 shows the gating circuits which perform the multiplexing of the signals shown in the chart of FIG. 9 to generate the video signals for representative video terminals No. l and No. 20;
FIG. 11 shows a hexidecimal representation of the video data for arow of characters on the odd and even scan, showing the data that is being generated by each of the segment generators atany instant of time; the first eight symbols shown are the letter A the ninth symbol generated is the letter B. This corresponds to the illustration shown in FIG. 1;
FIG. 4A is a block diagram showing how the basic symbol generator can be expanded to accommodate lower case characters;
FIG. 12 is a block diagram which illustrates how the system can be expanded by using a separate set of segment generators for the odd and even fields of an interlaced TV frame;
FIG. 13 is a block diagram showing how information indicating the color of complete words may be added to the multiplexed character generator;
FIG. 14 is a block diagram showing how the multiplexed character generator may be expanded to included information representative of the color of each individual character;
FIG. 15 is a block diagram showing another embodiment of the refresh storage and segment generators for use with a smaller number of display terminals;
FIG. 16 is a chart showing how the embodiment of FIG. 15 would be multiplexed.
DETAILED DESCRIPTION OF THE INVENTION System Environment Referring now to FIG. 2, a group of display terminals 101 through 132 are connected to a terminal control unit (TCU) 200 by lines 201. TCU 200 communicates with central processing unit (CPU) 50 by lines 52. For illustrative purposes the symbols A and B are shown to be the first two symbols of the first row of characters on each of the first eight display terminals 101 through 1108.
Terminal Control Unit Referring now to FIG. 3, TCU 200 is shown in block diagram form. Incoming information is presented to I/0 unit 204 on lines 202. [/0 unit 204 then transfers in parallel the appropriate signals to refresh storage 300 on lines 206. Refresh storage 300 has a plurality of output lines 208, 210, 212, 214 and 216 which are connected respectively to segment generators PCGl 410 PCGZ 430, PCG3 440, PCG4 450 and PCGS 460. The data transferred between refresh storage 300 and character generator 400 along each of the lines mentioned is in parallel byte form. The segmented character generator has a plurality of output lines, one group of lines in parallel from each of the five segment generators. PCGI is connected to multiplex generator 500 by line 428, PCGZ by line 438, PCG3 by line 448, PCG4 by line 458 and PCGS by line 468. Multiplex video generator 500 accepts the video signals from said segmented character generator 400 and synchronization signals from timing & control unit 600 and generates appropriate video scanning signals which are distributed to the plurality of display terminals by lines 252. Timing the control unit 600 is connected to [/0 unit 204 by lines 601, to refresh storage 300 by lines 602, to segmented character generator 400 by lines 603 and to multiplex video generator 500 by lines 604.
Refresh STORAGE Referring now to FIG. 4, refresh storage 300 has two major sections. Information bytes in binary form are presented to core storage 302 by line 206 which connects the I/O unit 204 (see also FIG. 3) to the refresh storage 300. Core storage 302 stores command and data information in parallel in byte form for transmission to a group of line buffers. Core storage 302 is connected to the first line buffer 310 by lines 304. In an exemplary embodiment line buffer 310 contains four parallel, six bit, 64 character buffers 312, 319, 316 and 318. Four parallel buffers allow simultaneous generation of video symbols for four times as many terminals as if a single six bit, 64 character buffer were used. Line buffers 320, 330, 340 and 350 are identical to line buffer 310. The outputs of line buffer 310 are connected to the inputs of segment generator PCGI 410 and also to the inputs of line buffer 320. In like manner, the outputs of line buffer 320 are connected by lines 210 to the inputs of segment generator 430 and to the inputs of line buffer 330. The outputs of line buffer 330 are connected by lines 212 to the inputs of segment generator 440 and to the inputs of line buffer 340. The outputs of line buffer 340 are connected by lines 214 to the inputs of segment generator 450 and to the inputs of line buffer 350. The outputs of line buffer 350 are connected by lines 216 to segment generator 460. It can be seen that in like manner, if the number of segment generators PCGn are increased, the number of line buffers can be also be increased to adapt the system to any font of symbols desired.
Segmented Symbol Generator Referring now to FIG. 5, an exemplary segment generator 410 is shown. Lines 208 which are the outputs of the four buffers which make up line buffer 310 (see also FIG. 4) are connected to a plurality or OR circuits 411, 412, 413, 414, 415, and 416. The output 421 of OR-circuit 411 represents symbol data bit 1. The output 422 of ORcircuit 412 represents symbol data bit 2. The output 423 of OR-circuit 413 represents symbol data bit 3. The output 424 of OR-circuit 414 represents symbol data bit 4. The output 425 of OR-circuit 415 represents symbol data bit 5 and the output 426 of OR- circuit 416 represents symbol data bit 6. It can be seen also that a number of data bits used to encode the symbol information could be either contracted or expanded depending upon the specific group of symbols involved. For example, an eightbit code could be used wherein additional OR circuits and inputs to read-only storage 420 would be necessary.
The odd/even signal is presented to read-only storage 420 on line 427. This signal is generated by flip-flop 417 which has as its input the vertical synchronization signal which appears on line 658.
Read-only storage 420 accepts as its input a data byte representative of a particular symbol to be generated. The output lines 423 of read-only storage 420 represent a single horizontal line segment of the symbol to be generated, which in the exemplary case is an eight-bit parallel byte.
Read-only storage output lines 428 from PCGI are connected to parallel-to-serial register W8 1 505 (see FIG. 6). In like manner, the outputs 338, (see also FIG. 4) 448, 458 and 468 from segment generators 430, 440, 450, and 460 respectively, are connected to P/S 2 506, P/S 3 507, PIS 4 508 and P/S S 509, respectively.
Referring now to FIG. 6A, an exemplary P/S register is shown. Register P/S 1 505 contains four n-bit shift registers where n is equal to the number of bits in the data byte from the read-only storage elements. Since in the preferred embodiment being described, 32 display terminals are being controlled by one terminal control unit, four distinct shift lines are necessary which correspond to the four distinct buffers in each of the line buffers 310, 320, 330, 340, and 350 (see also FIG. 4). Line 428 is connected in parallel to n-bit shift registers 510, 520, 530, and 540. Referring also to FIG. 7, group shift lines are generated in group shift counter 630 which is connected to basic clock 610 by lines 613. Line shift 1 631 is connected to shift input of shift register 510 (see also FIG. 6A). Line shift 2 is connected to shift register 520 on line 632. Line shift 3 is connected to shift register 530 on line 633. Line shift 4 is connected to shift register 540 on line 634. The serial outputs from the shift registers are presented to the multiplexed video gates, an example of which is shown in FIG. 10 as AND-circuits 552, 554, 556, SS8, 560, 572, 574, 576, 578 and S80.
Multiplexed Video Generator Referring to FIGS. 6, 6A, 9 and 10, the multiplexed data connections necessary to generate the video signals for representative terminals 1 and 20 of a group of 32 terminals are shown.
In order to generate the correct video signals for display terminal 1, it can be seen from FIG. 9 that at line count 1 times the segment generator output PCGIGRI (see also FIG. 6) must be gated to the video line, and at line count 2 PCGZGRI must be gated to the video line. In like manner PCG3GR1 at line count 3, PCG4GR1 at line count 4, and PCGSGRl at line count 5 must be gated to the video line for each field of data to achieve a complete horizontal line row of symbols for display terminal I.
In like manner, to generate the video signals for display terminal 20, at line count 4, segment generator PCG1GR3 is gated; and at line count, 5 PCG2GR3 is gated; at line count 6 PCG3GR3 is gated; at line count 7, PCG4GR3 is gated; and at line count, 8 PCGSGRJ is gated to the video line for display tenninal 20.
The outputs from P/S registers 505, 506, 507, 508, 509, are presented to the multiplex video gates according to the chart shown in FIG. 9.
For display terminal 1, P/S register output 511 (see also FIG. 6) is connected to AND-circuit 552 (see also FIG. as one input. Line 641 (see also FIG. 7) is connected from 8 line counter 640 to a second input of AND-circuit 552 (FIG. 10) such that the infonnation presented on line 511 will be gated to OR-circuit 562 along output line 553 at count LCl. In like manner, output line 512 representing PCGZGRI is connected to a first input to AND-circuit 554 while line 642 is connected from 8 line counter 640 to a second input of AND 554. The output 555 ofAND-circuit 554 is connected to a second input of OR-circuit 562 and represents the second horizontal line each field to be displayed on display terminal 1. Line 643 is connected to an input of AND-circuit 556 along with PCG3GR1 513. The output 557 of AND-circuit 556 is con nected to a third input of or-circuit 562 and represents the third horizontal line in each field for each row of symbols to be generated on display terminal 1. Line 644 is connected to an input of AND-circuit 558 as is PCG4GR1 514. The output 559 of AND-circuit 558 is connected to a fourth input to OR- circuit 562 and represents the fourth line to be generated in each field of each row of symbols to be generated on display terminal 1. Line 645 is connected to an input of AND-circuit 560 while PCGSGRI 515 is connected to a second input of AN Dcircuit 560. The output 561 of AND-circuit 560 is connected to a fifth input of ORcircuit 562 to provide the fifth line of each field of each row of symbols to be generated on display terminal 1.
It is clear that if a different symbol set where used, the number of segment generators or the line count outputs could be increased or decreased to meet the requirements of a particular symbol set. In such a case the number of AND-circuits 552 through 560 would accordingly be increased or decreased as well as the number of inputs to OR-circuits 562.
The output 563 of OR circuit 562 is connected to one input ofsync mixer 564. The second input to sync mixer 564 is vertical sync l 651 (see FIG. 7) which is generated by vertical sync counter 650.
Sync mixer 564 can be any one of a number of circuits known in the television art to add a synchronization signal to an information signal for proper display on a display terminal.
The output 565 of sync mixer 564 is then connected to the No. I display terminal 101 (FIG. 2). Referring to FIG. 9, it can be seen that the video signals for display terminals 1 through 8 are generated from the GRI signals of segment generators PCGl, 2, 3, 4, and 5. GR2 provides a gating signal for the generation of the video signals for display terminals 9 through 16. GR3 provides the gating signals for the generation of video signals for display terminals 17 through 24 and GR4 generates the gating signals for the generation of video signals for display terminals 25 through 32.
Referring again to FIG. 10 and to FIG. 9, the video signals for display terminal (not shown) is generated in AND-circuit 572 by line count 4 644 and PCG1GR3 531, in AND-circuit 574 by line count 5 645 and GCG2GR3 532, in AND-circuit 576 by line count 6 646 and PCG3, GR3 533, ANDing in AND-circuit 578 line count 7 647 and PCG4 GR3 534 and in AND-circuit 580 by line count 8 648 and PCGS GR3 535. The outputs 573, 575, 577, 579, 581 of AND-circuits 572, 574, 576, 578, 580 respectively are connected to respective inputs of OR-circuit 562 along with a cursor input as in the circuitry for generating the .video signals for No. I display terminal 101 (FIG. 2).
The cursor can be generated by any conventional means and is ORed into the video stream at AND-circuits 562 or 682. The output 583 of OR-circuit 582 is connected to sync mixer 584 which has as another input vertical sync 4 654 which is generated by vertical sync counter 650. Sync mixer 584 is an identical circuit to sync mixer 564 and circuits of this type are well known in the art. The output 585 of sync mixer 584 is connected to display terminal 20 120.
Timing and control Referring now to FIGS. 7, 8 and 12, a clock signal generator 610 generates a basic timing signal which is used to generate all the necessary timing signals for the terminal control unit 200. The output of clock generator 610 is connected to sync generator 620 by line 612 and to group shift counter 630 by line 613. Sync generator 620 generates the horizontal synchronization signal which is presented on line 621 and a base vertical synchronization signal which is presented on line 625.
Sync generator 620 is connected to vertical sync counter 650 by line 625 and to 8 line counter 640 by line 621.
Eight line counter 640 generates signal line count 1 through line count 8 which are requiredfor the multiplex video gating. Vertical sync counter 650 generates a series of n vertical synchronization signals each of which is staggered in time by one horizontal time period. Vertical sync 1 through vertical sync 8 are presented on lines 651 through 658. The time displacement of the vertical synchronization signals is shown clearly in FIG. 8. Where It is equal to one horizontal line time, including trace and retrace.
The time displacement of vertical synchronization signals 2 through 8, allows the video signals for each of the 32 display tenninals 101 (see FIG. 2) through 132 to begin at the same relative position on the face of the display device. Referring to FIG. 11, it can be seen that if the vertical synchronization signals were not displaced in time, at a first instance in time, a video signal would appear only on display terminals 1, 9, l7, and 25. At the beginning of a second horizontal line scan in each field, a video signal would appear in addition only on display terminals 2, 10, 18 and 26, on the third horizontal line scan display terminals 3, l1, l9 and 27 and so on with an additional four displays beginning with each successive horizontal line until all 32 displays are presenting symbols.
The staggering of the vertical synchronization signals allows the video signal for each of the 32 display terminals to begin the first horizontal line of each field at the same relative position on each display device.
Group shift counter 630 provides four shift signals shift 1, 631, shift 2, 632, shift 3 633 and shift 4 634. These shift signals are presented to P/S registers to gate the video information for the proper display terminal to the multiplex gate at the correct time.
Lower Case Character Generation Referring now to FIGS. 1, 4A and 11, the system previously described is capable of generating a symbol set which occupies l0 horizontal lines for symbol generation plus an additional six horizontal lines for blank space between rows of symbols.
It is most common in alphanumeric display systems to use a symbol font which contains only upper case characters. The apparatus of the instant invention has the capability with the addition of two additional 64 character three-bit line buffers, six-bit to three-bit parallel converter logic and two read-only storage segment generators of generating lower case characters which have tails below the bottom line of the upper case symbols. That is,-the tails of the lower case characters would extend into horizontal lines 11 through 14.
Referring now to FIG. 4A, line buffer 5, 350 is connected by line 216 to a 64 character three-bit line buffer 360, which includes six-bit to threebit parallel converter logic at the input, in addition to segment generator 460. The output 218 of line buffer 360 is connected to segment generator 470 and also to the input of line buffer 370. Line bufiers 360 and 370 are capable of storing a fully 64 character row of three-bit characters. Since a three-bit character will allows eight combinations, and since there are five lower case characters in a normal alphabet which extend below the base line (g,f, p, q, y), with a single code reserved for upper case and lower case characters which do not extend below the case line to blank out segment generator 470 and segment generator 480, there are two unused codes available for additional symbols in raster lines 11, 12,13 and 14 of each horizontal row of symbols. The output 478 of segment generator 470 and the output 488 of segment generator 480 are then connected to additional P/S registers which must be added to accommodate the lower case symbols.
Additional logic is required to implement the P/S registers and additional multiplex AND gates which are required for lower case character generation.
System Expansion Referring now to FIG. 12, the number of display terminals which can be accommodated by apparatus embodying the instant invention, can be expanded from 32 to 64 by the division of a set of segment generators 410, 430. 440, 450, 460 into two sets 49], 492 which would be used to generate the odd and even field of the two sets of display terminals simultaneously.
Odd/even flip-flop 417 gates lines 208, 210, 212, 214, 216 to segment generator 491 or 492 on alternate fields to achieve I percent utilization of the ROS elements 420 (see FIG. of each segment generator.
The complete duplicate structure is not shown since it is clear from the preceding description of the basic embodiment.
Generation of Color Information Referring now to FIGS. 13 and 14, the instant invention also includes embodiments for generating color information for display on a display tenninal either on a character-bycharacter basis as shown in FIG. 14 or on a word-by-word basis as shown in F IO. 13.
Word-by-Word Color Buffer output lines 208, 210, 212, 214, and 216 in addition to being connected to the segment generators as shown in FIG. 4, are also connected to an AND-gate 710 (FIG. 13) which generates an active output signal to color latch 1, 720 when the information on lines 208 represent a color code signal. This color code signal would occur only during the space between words in the flow of information to be displayed. Color latch X, 720 is necessary when the signals on lines 208 are not present for a sufficient length of time to provide the proper gating signals to AND-group 730. The output 721 of color latch I, 720 is connected to a first input of each of a group of AND circuits which comprise the AND-group 730. A second input of each of these AND circuits is from 8 line counter 640 which is this illustrative example would be lines 641, 642, 643, 644, 645, 646, 647, and 648. In like manner, an AND circuit and for color latch in a group of AND gates will be required to accommodate each of the segment generators 410, 430, 440, 450, 460 shown in FIG. d. These are not shown in detail here since they are duplicates of the logic necessary to generate the color information for the first two lines of each symbol represented by the output from PCGi. The output 731 of the first AND circuit in AND-group 730 is connected to a first input of OR-circuit 780. Outputs 2 through 8 of AND-group 730 would be connected to other OR circuits to generate color information for display terminals other than display terminal I. In like manner, the second out put 742 from AND-group 740 is connected to a second input of OR-circuit 780, the third output 753 from AND-group 750 the fourth output 764 from AND-group 760 and the fifth output 775 from AND-group 770 are connected to respective inputs of OR-circuits 780 to provide complete color information for a word of symbols each of which occupy ten horizontal lines on a display device.
The output 781 of OR 780 is connected to AND-circuit 784 and to inverter 782 The output 783 of inverter 782 is connected to a first input of AND circuit 786. A second input to AND-circuits 784 and 786 is from the appropriate multiplex video gates 562 on output line 563 as shown in FIG. 10. The output of AND-circuit 784 provides a shift signal to the threebit color shift register 790. The output 787 of AND-circuit 786 provides a gating input to color gates 794, 796, and 798. The three primary colors, red, green and blue are represented by outputs 791, 792 and 793 respectively which are connected to second inputs of color gates 794, 796 and 798. Outputs 795, 797 and 799 of color gates 794, 796, and 798 are connected to color/gray level encoder and sync mixer 810. Vertical sync I, 651 is connected to color/gray level encoder and sync mixer 810 to provide the appropriate synchronization signals. Output SI] of encoder and sync mixer 810 provides video signals for display terminal I which can contain, in addition to the information to be displayed, color word information or gray scale information.
The apparatus described for defining the color of words on the display device inherently have the capability also of defining the gray scale rendition of the information to be displayed.
Character by Character Color Referring now to FIG. 14, exemplary apparatus is shown which allows generation of color information on a characterby-character basis rather than a word-by-word basis. Basically, this mode of operation requires in addition to the symbol code byte three additional bits in parallel which carry a color code for each symbol. Lines 208 (FIG. 3) from refresh storage in addition to being connected to the segment generators are now expanded to include three additional lines which are connected to a group of AND-circuits 820 which represents in this case three AND circuits each of which produces an active output when the inputs represent a color code. Output lines 821 from AND-circuits 820 are connected to additional three-bit section 822 of parallel to serial register 505.
The portions of the apparatus are not described in detail here, but have been previously described in detail either in the description of the basic embodiment of the invention or in the embodiment for generating color words.
The color information contained in the three-bit section 822 of parallel to serial register 505 is now placed directly in the data path for video generation. Circuits 730, 780, 790 are the same as described previously. Counter 824 has asits input shift line 631. Counter 824 provides a running count to II with an output whenever the count exceeds three. This output 825 is connected to AND-circuit 830 and to inverter 826. When the count exceeds three, symbol information rather than color information is being presented. At this time, output line 825 from counter 824 activates AND-circuit 830 to allow the color information to be presented to gates 832, 834 and 836 The outputs 833, 835 and 837 of these gates are connected in turn to first inputs of OR-circuits 840, 842 and 844 which are in turn connected to encoder and sync mixer 810.
It is to be noted, that in each of the embodiments described, the signal path was shown only for display terminal 101. Identical circuitry would be used for each of the other 2] displays in the typical system with the connections made according to the chart shown in FIG. 9.
Reduced System In those applications where a small number of display terminals will be attached to the terminal control unit, a minimum system is desired to eliminate unnecessary hardware. Referring now to FIGS. 15 and 16, a reduced embodiment is shown in which the character generator is generating symbol information for only four display terminals.
In this embodiment, the output of core storage 302 (FIG. 4) is connected to the input of segment generator PCGI, 410 and to a group of OR-circuits 308. The output of OR-circuits 308 provide the inputs to line buffer 310. The outputs from line buffer 310 are connected to segment generator PCG2/4, 430 and to line buffer 320. The outputs from line buffer 320 are connected to PCG3/5, 440 and to AND-circuits 306. Counter 660, which is an 8 line counter similar to line counter 640 with additional gates to generate outputs C2, C3, C4, and C5, has its input connected to horizontal sync 621 (FIG. 7) and presents outputs C2, C3, C4 and C5. C2 and C4 are connected to PCGZ/d, 930 to control the operation of PCG2/4 to generate either the third and fourth lines of a symbol or the seventh and eighth lines of a symbol. In like manner, output lines C3 and C5 are connected to PCG3/5, 440 to activate PCG3 to generate lines 5 and 6 of a symbol or to generate lines 9 and 10 of a symbol respectively. Line C3 is also connected to each of the AND circuits in AND-group 306 to allow recirculation of the symbol information. The outputs of AND-group 306 are connected to second sets of inputs in OR- circuits 308 to provide recirculation of the symbol information to line buffer 310. The Boolean expression for the outputs C2, C3, C4 and C5 are:
Since there are not only three sets of outputs from the segments generators, the amount of multiplex logic that is needed is greatly reduced.
Some of the details of the embodiments of the invention described have not been shown since these details would be clear to those skilled in the art.
As has been shown in the detailed description of the invention, there are many combinations of apparatus which can be built utilizing the instant invention.
OPERATION Referring now to FIGS. 2, 3, 4 and 5, the operation of an preferred embodiment of the invention will be described.
Information to be displayed is transmitted from CPU 50 (FIG. 2) to terminal control unit 200 along lines 52. Terminal control unit 200 then generates appropriate video signals for the various display terminals in response to the information from the CPU 50. These video signals are transmitted to display terminals 101 through 132 along lines 201.
The terminal control unit 200 receives the information from CPU 50 in H0 control 204 (FIG. 3) which performs all necessary interface communications with the CPU 50. The information is then transmitted to refresh storage 300 and stored in core storage 302. At the appropriate time under the control of timing and control element 600 (FIG. 3), information bytes representing symbols to be displayed are transmitted to a first line buffer 310. Line buffer 310 acts as a buffer between core storage 302 and the first segment generator PCGl 410. Line buffer 310 is not necessary in applications where the operating speed of the core storage and the segment generator are comparablev Segment generator 410 generates the first scan line of a symbol in each row of symbols on the odd horizontal scans and the second line ofa symbol in each row of symbols on the even horizontal scans in response to the infonnation byte from line buffer 310.
Each of the line buffers 310, 320, 330, 340 and 350 provides a delay of one horizontal line scan time so that the output signals from line buffer 310 to line buffer 320, from line buffer 320 to line buffer 330, from line buffer 330 to line buffer 340 and from line bufi'er 340 to line buffer 350 begin at the start of a row of symbols. Thus, in response to the inputs from the respective line buffers, PCG2 430 generates the third line of each symbol in a row on the odd horizontal scans and the fourth line of each symbol in a row on the even horizontal scans, PCG3 440 generates the fifth line of each symbol in a row on the odd horizontal scans and the sixth line of each symbol in a row on the even horizontal scans, PCG4 450 generates the seventh line of each symbol in a row on the odd horizontal scans and the eighth line of each symbol in a row on the even horizontal scans and the PCGS 460 generates the ninth line of each symbol ,in a row on the odd horizontal scans and the tenth line of each symbol in a row on the even horizontal scans.
It is clear that this apparatus could be extended to accommodate larger character sizes or reduced to accommodate smaller character or reduced to sizes by adding or deleting line buffers and segment generators.
Timing and control circuitry 600 controls the gating of each of the four groups of information signals from the line buffers to the segment generators along lines 208 and also controls the timing of the output signals from the read-only storage elements 420 to multiplex video generator 500.
The outputs from character generator 400 present a parallel signal which contains the video information. Timing and control unit 600 also provides control signals and timing signals along lines 604 to multiplex video generator 500. Multiplex video generator 500 transmits the video signals to the appropriate display terminal for visual display.
Referring now to FIGS. 1, 2, 3, and II, the generation of representative symbols will be explained.
If for example, as shown in FIG. 2, it is desired to generate the symbol upper case A in the first symbol position in the first row of symbols on each of the first eight display devices, and the symbol upper case B in the second symbol position on the first row of symbols in each of the first display devices, the apparatus embodying the invention would operate in the following manner.
A group of information signals in parallel byte form representing the symbol A is transmitted from CPU 50 to terminal control 200 and stored in core storage 302. Each of these information bytes takes the binary form 00000 I, which is the binary representation for the symbol A. At the appropriate instant of time, in synchronism with the raster scan for the display devices, the information byte representing the symbol A for the first row of symbols of the first display device is gated to the sequential line buffers (FIG. 4).
The binary representation 000001 acts as an address for a particular group of storage elements in segment generator 410 which have stored therein the video representation for the first line of the symbol A.
In eight-bit binary form, the video representation for the first line of the symbol A is 0001 I000. This binary information is also represented in hexidecimal notation as l 8.
The eight-bit binary representation is transmitted on line 428 to P/S converter 505 (FIGS. 6, 6A).
P/S converter 505 serializes the eight-bit video representation and presents this serial representation along line 511 to multiplex video generator gates 552 (FIG. 10).
Since this example deals only with the data generated for the first eight display devices 101 through 108, the other outputs 521, 531 and 541 of P/S converter 505 will not be explained in detail. These outputs represent the video signals for display devices 109 through 116, 117 through l24 and through 132 respectively.
Due to the speed of operation of the core storage 302 and the segment generators 410 through 460, are generated four groups of signals in parallel through a single set of line buffers and a single segmented character generator.
Referring now to FIGS. 6 and 10 the output line 511 which transmits the video signals for the first segment of each symbol to be displayed on display devices 101 through 108, multiplex gate 552 is turned on by signal LCl on line 641 during line I of each row of symbols on odd horizontal scans and line 2 the first line of each row of symbols on even horizontal scans. The video being presented on line 511 at the time of the first line of an odd horizontal scan is hexadecimal l8," which is transmitted to sync mixer 564 (FIG. 10) through OR-circuit 562.
In Sync mixer 564 synchronization signals are added to the video signals to form a composite video signal for transmission to display terminal 101. The sync signal vertical sync 1 represents a set of scanning synchronization signals which cause the raster on display devices 101, I09, 117, 125 to begin one horizontal scanning line time in advance of the beginning of the raster scan, for display devices 102, 110, 118, and 126, which is in synchronism with sync signal vertical sync 2.
This staggering" of the synchronization signals, and therefore of the raster scan of the groups of display devices, allows the visual image presented by each display device to begin at the same relative location on the face of each display device.
If the synchronization signals were not stagered" the visual impression obtained on viewing eight display devices side by side would be that each row of characters in the second and subsequent displays would be displaced vertically oown two horizontal lines from the preceding display device. This would result in an effect similar to that shown in FIG. I if the first symbol from each display device were placed side by side on a single composite display device.
In a similar manner as described above, one horizontal line time after the information byte has passed through line buffer 320, the binary representation 000001 is presented to segment generator 430 which then in response to this input address signal and ODD/EVEN flip-flop 417 in ODD state, generates the binary representation 01 l l l l 1 10 which represents line 3 of the symbol A. At the same time, the information signals representative of the first symbol on display devices 102, 110, 118 and 126 are presented to segment generator 410.
For simplicity of explanation, the symbol A will be generated also as the first symbol in the first line of symbols on display device 102.
In a similar manner to that description above, the video signal from segment generator 430 (FIG. 4) is serialized and presented to gate 554 which is turned on by LC2 during the second line of each row of symbols in each horizontal scan. Thus, the video representation 01 l l l 1 10 is transmitted to display device 101 in proper time sequence.
As can be seen from P16. 1, the data representing the first line of the first row of symbols for the display device 102 is similarly presented to the display device at the same time. However, the gating for display terminal 102 is not shown since the chart of P10. 9 sets out the appropriate gating conditions for each of the display terminals for each line count and segment generator.
In like manner, on horizontal line time later the information signal, representing upper case A, is presented to segment generator 440 (FlG. 4) which responds by generating video representation 1 1000011 which corresponds to the fifth line of the symbol A. At the same time, line 3 of the first symbol on display device 102 is being generated and line 1 of the first symbol for display devices 103, 111, 119 and 127 are being generated.
In like manner, lines 7 and 9 of the first symbol in the first row of symbols for display device 101 is generated on the first odd horizontal scan. The video representation for line 7 being 1 l l l l 1 l 1 and for line 9 being 11000011.
At the time line 7 is being generated on display device 101, line 5 is being generated for display device 102, line 3 is being generated for display device 103 and line 1 being generated for display devices 104, 112, 120 and 128. It may be noted at this point, that when the first symbol to be generated on each display is being displayed, the segment generators 410, 430, 440, 450 and 460 (F 1G. 4) are operated in a staggered manner as shown in F lg. 11, with segment generator 460 not active to generate line 9 for the first display device 101 until PCGl segment generator 410 is generating the first line of the first symbol for display devices 105, 113, 121 and 129.
In the manner described above, the first line of the first symbol to be displayed on each of the display devices 101 through 108 is generated in the first eight multiplexed symbol positions. In the ninth symbol position, the first scan line of the first symbol in the second row of symbols on display device 101 can be generated since segment generator 410 is free. In like manner, on horizontal line time later the third line of the first symbol in the second row to be generated on the first display device 101 is generated while the first scan line of the first symbol in the second row to be generated on display device 102 is generated. Similarly, the second and further symbols on each row of symbols for each display device are generated in the staggered manner described above.
Referring to F168. 9 and 10, the multiplexing of the video representations to form the visual images on a representative display device 120 is shown.
Display device 120 is contained in the third group of eight multiplexed video display devices. It can be seen that the video signals representing the video to be displayed on display device 120 are represented in each case by PCG1GR3 on line 531, PCGZGRS on line 532, PCG3GR3 on line 533, PCG4GR3 on line 534 and PCGSGR3 on line 535.
Slnce display device 120 is the fourth unit in the third group, the staggered synchronization signals are the same as for display device 104.
Thus, the first line of video for each symbol to be generated on display device 120 is gated by signal LC4 along line 644. This means that while the fourth segment (lines 7 on odd or 8 on even scans) of each symbol on display device 101 is being generated, the first segment (lines 1 on odd or 2 on even scans) of each symbol on display device 120 is being generated. 1n like manner, the second segment is generated at LC5 time, the third segment is generated at LC6 time, the fourth segment is generated at LC7 time and the fifth segment is generated at LCQ time.
The video signals are mixed in sync mixer 584 with vertical sync 4 to allow the visual image presented to begin at the same relative location on the display device as each of the other display devices.
The particular font of characters employed requires eight spots in the horizontal direction and ten lines in the vertical direction with an additional six vertical lines providing the space between rows of symbols and two spots providing the horizontal space between characters in each row. This format, of course, is completely flexible and the invention as described could be used with any symbol format.
While the operation of the invention has been primarily described for an odd horizontal field, operation on the even horizontal field would be identical with line counts 1 through 8 representing horizontal lines 2, 4, 6, 8, 10, 12, 14 and 16 respectively, rather than lines 1, 3, 5, 7, 9, 11, 13, and 15 for each row of symbols.
Lower Case Characters Referring now to FIG. 4A, the apparatus embodying the instant invention has the capability of expansion to generate tails" for those lower case characters which have portions below the upper case character base line. For example, the lower case characters 3, j, p, q, and y have that portion of the character above the base line generated in the manner described above, and that portion of the character below the base line, that is, the tail, generated by additional segment generators 470 and 480 which together have the capability of generating information on four additional lines of each symbol block.
Llne buffers 360 and 370 store 64 three-bit symbols which represent the lower case information of a symbol being generated or the absence of lower case information. For example, the three bit character 600 could be used to represent all upper case characters and lower case characters which do not extend below the base line in which case segment generators 470 and 480 would not be used at all since the three bit character 000 would not address any of the active locations of either of these segment generators.
The three bit character O01 might represent lower case g, 010-}, 00l-p, lOOq and 101-y. This information would be gated through the multiplex video generator in a manner similar to that described for upper case characters. The details of the implementation for lower case characters could readily be added by one skilled in the art in view of the prior disclosure regarding upper case character generation.
System Expansion Referring now to FIG. 12, it is seen that the number of display devices serviced by the multiplexed character generator can be doubled by dividing the set of segment generators into odd and even subsets 491, 492 so that one subset of segment generators 491 can be generating an odd horizontal field of a first group of 32 display terminals while a second set of seg ment generators 492 is generating video information for an even horizontal field for a second set of 32 display devices.
Generation of Color information Referring now to FIGS. 13 and 14, it can be seen that a character containing only color information can readily be handled by the apparatus during the time of a space between words on any line of symbols.
A word color signal is received and detected by AND-gate 710 (E16. 13) which sets color latch 1, 720. This color latch then remains set for the entire word to be displayed in a particular' color. The video information from the segmented character generators is then gated with the color latch signal through a series of logic gates to a color shift register 790. The output of the color shift register determined which combination of the three gates 832, 834, 836 will be encoded in encod-