US 3628099 A
Abstract available in
Claims available in
Description (OCR text may contain errors)
United States Patent Inventors Carl E. Atkins Montclalr, N.J.; Arthur F. Cake, Smithtown, Long Island, N.Y.
Appl. No. 46,984
Filed June 17, 1970 Patented Dec. 14, 1971. Assignee Wagner Electric Corporation RESlSTANCE-RESPCNSIVE CONTROL CIRCUIT 10Claims, 1 Drawing Fig.
U.S.Cl 317/134, 70/DlG. 46, 317/D1G. 5, 324/62 C int. Cl E05b 49/00 Field of Search 317/134,
DIG. 5; 340/147 R, 147 A, 149 A; 70/278, DlG. 46; 324/62 R, 62 C; 307/218, 235
 Relerences Cited UNITED STATES PATENTS 3,136,307 6/1964 Richard 317/134 X 3,159,772 12/1964 Van Doorn 3l7/DIG. 5
Primary Examiner-J. D. Miller Assistant ExaminerHarry E. Moose, Jr. Attorney-Eyre, Mann & Lucas ABSTRACT: A circuit for controlling energization and deenergization of a load only in response to a value of resistance falling within a narrow predetermined range of resistances. The circuit has the capability of preventing unlocking by the insertion of a variable resistor between the terminals provided for sensing the keying resistance and hunting for the proper value of resistance.
Patented Dec. 14, 1971 RESISTANCE-RESPONSIVE CONTROL CIRCUIT The present invention relates to a resistance-responsive control circuit including discrimination and antitamper features. Specifically, this circuit is designed to control the energization state of a load, e.g., a solenoid-controlled door lock of an automobile, by connecting a predetermined keying resistance falling within a narrow range of resistances across a pair of terminals. Preferably, the location of these terminals will not be readily determinable by an unauthorized person. In any event, the anti tamper feature will deter unlocking by connecting a variable resistor across the terminals and hunting for the proper value of resistance. Of course, the control circuit disclosed herein is readily adaptable to a wide variety of applications, which include controlling the closing of the ignition circuit of an automobile, and controlling a lock on a garage door or on one or more doors providing ingress to a house or a room within a house.
A better understanding of the present invention may be had by reference to the drawing, which illustrates the preferred embodiment of the present invention. The control circuit shown in the drawing is constantly energized by a l2-volt direct current source of electromotive force, the positive terminal of which is connected to the circuit terminal T-l. The. predetermined keying resistance R-l is connectable across terminals T-2 and T-3, thereby forming a voltage divider circuit comprising resistances R-1 and R-Z connected in series between ground and the line voltage applied at terminal T-l. Terminals T-2 and T-3 are the input terminals of the twostage emitter-follower amplifier comprising transistors Q-l and (3-2 and resistance R-3, the latter being connected in series between the emitter of transistor -2 and ground. This amplifier has a high input impedance between terminals T-2 and T-3 in order to minimize the effects of current loading on the voltage developed at the junction of resistances R-1 and R-Z. The output of this amplifier is derived at the junction of resistance R-3 and the emitter of transistor 0-2.
When a keying resistance R-l is connected across T-2 and T-3, a predetermined input voltage is applied to the base of transistor 0-1 which causes the positive output voltage of the emitter-follower amplifier to decrease to a predetermined output voltage. This outputvoltage controls the intermediate circuitry controlling the state of the collector-emitter junctions of transistors Q-6, 0-12 and 0-15, which are respectively connected in series with the first, second and third input channels of AND-Gate l comprising diodes D-l, D-2 and D-3, respectively. Transistors 0-6 and (1-15 are normally conductive to close shunt paths around the bias current path formed by diode D-4 and resistance R-ll of AND-Gate I. The state of transistor 0-6 is controlled by a first amplifier consisting of transistors Q-3 and 0-4 and resistors R-4, R-5 and R-6 and by a second amplifier consisting of transistor 0-5 and resistors R-7 and R-8. Resistance R-6 is connected to the base of transistor Q-4 by a slidable tap, which enables the voltage at the base of transistor Q-4 to be set so that the predetermined output voltage generated by the emitter-follower amplifier in response to insertion of a keying resistance R-l between terminals T-2 and T-.3 will cause normally nonconductive transistors Q-3 and Q-4 to become conductive. Current will then flow across resistance R- 5 to cause a positive voltage to be applied to the base of transistor 0-5 through resistance R-7. Transistor 0-5 is thus rendered conductive, and the voltage at the junction of resistance R-8 and the collector of transistor Q-S drops from essentially line voltage to near ground potential, thereby causing transistor Q-6 to become nonconductive. Thus, the current shunt path from the low side of resistor R-l0 through diode D-1 and the collector-emitter junction of transistor 06 to ground is effectively opened, and no longer shunts the current path from the low side of resistor R-l0 through diode D-4 and resistor R-l l to ground.
The state of normally nonconductive transistor Q-l2 is controlled by the intermediate amplifier consisting of transistors 0-9 and 0-10 and resistorsR-16, R-20 and R-22. Resistance R-22 is connected to'the base of the transistor 0-10 by a slidable tap which enables the voltage at the base of transistor Q- to be set so that the predetermined output voltage generated by the emitter-follower amplifier in response to insertion of a keying resistance R-1 between terminals T-2 and T-3 will cause normally nonconductive transistors Q-9 and Q-10 to remain nonconductive. Under these conditions, no current flows across resistance R- which is connected between the collector of transistor 0-9 and ground. Thus, the base of transistor 0-12 is at essentially ground potential by virtue of the connection to ground through resistances R-20 and R-21. Transistor 0-12 thus remains nonconductive, and the bias current shunt path from the low side of resistor R-l0 through diode D-2 and the collector-emitter junction of transistor 0-12 remains open. Thus, the bias current path in AND-Gate 1 from the low side of resistor R-10 through diode D-4 and resistor R-ll to ground is not bypassed.
Transistor Q-15 and its biasing resistors R-31 and R-32 are interconnected with a relaxation oscillator comprising unijunction transistor (UJT) 0-16, resistances R-30, R-33 and R-34 and capacitance C-3, the latter being connected between the emitter of UJT 0-16 and the base of transistor 0-15. A third bias current shunt path is formed by diode D-3 of AND-Gate I and the collector-emitter junction of transistor Q-l5, this path being in parallel with the first and second bias current shunt paths formed by diode D-l5, this path being in 7 parallel with the first and second bias current shunt paths formed by diode D-1 and the collector-emitter junction of transistor Q-6 and by diode D-2 and the collector-emitter junction of transistor Q-12, respectively. The state of transistor Q-l5 is controlled by an amplifier comprising transistor Q-ll and biasing resistors R-IS, R-17, R-18 and R-19. As with the other intermediate amplifiers controlling transistors 0-6 and 0-12, this amplifier derives its input from the emitter-follower amplifier whose output is controlled by the resistance R-l between terminals T-2 and T-3. Transistor 0-11 is biased so that even a very small decrease in the positive output voltage of the resistance sensing emitter-follower amplifier will render the emitter-collector junction of transistor 0-11 conductive, thereby causing current flow through resistance R-18. A positive voltage is thus applied to the cathode of diode D-lS, the anode of which is connected directly to the junction of capacitance C-3 and the emitter of unijunction transistor 0-16. Thus. the shunt path past capacitance C-3 through diode D-15 and resistance R-18 is blocked, and since the parallel capacitance C-2 is normally charged by current passing through resistance R-29, capacitance C-3 now becomes charged by current flowing through variable resistance R-30. The relaxation oscillator thus becomes oscillatory, with capacitance C-3 periodically charging to the triggering voltage of UJT Q-l6 and discharging through the emitter and base No. l of UJT 0-16 to ground. Consequently, the collector-emitter junction of transistor 0-15 is periodically rendered nonconductive by the negative voltage applied at the base of transistor Q-lS each time capacitor C-3 charges.
Thus, with the first and second shunt paths being held constantly open, positive voltage pulses will be applied to the base of transistor 0-7 of N AND-Gate i each time the collectoremitter junction of transistor Q-l5 is rendered nonconductive, thereby rendering the collector-emitter junction of transistor Q-7 conductive with the application of each positive voltage pulse to its base. Thus, capacitance C-l discharges rapidly to ground through diode D-5 and the periodically conductive collector-emitter junction of transistor 0-7. The voltage which was applied by capacitor C-l through resistor R-14 to the base of the relay-controlling transistor 0-8 to become conductive. By adjusting the value of variable resistor R-30 in the relaxation oscillator so that capacitor C-3 charges more rapidly than capacitor C-l is charged through resistor R-l3, transistor Q-7 is rendered conductive with sufficient frequency to prevent capacitance C-l from being charged to a level at which transistor 0-8 would become nonconductive. The winding of the relay Re is thus constantly energized, causing the relay contacts to close and energize the load controlled thereby. Keying resistance R-l may then be removed from between the terminals T-2 and T-3, thereby causing transistors Q-6 and -15 to return to their original state, i.e., having constantly conductive collector-emitter junctions. Transistor 0-7 will consequently be rendered nonconductive, and capacitor C-l will be charged through resistance R-l to turn off the relay-controlling transistor 0-8.
The antitamper feature of the present invention resides in the combination of AND-Gates ll and Ill and the relaxation oscillator comprising UJT 0-16. When the proper keying resistance R-l is connected between terminals T 2 and T-3, and transistors 0-6 and 0-l2 respectively become and remain nonconductive as described earlier, the voltage at the junction of resistor R-26 and the collector terminal of transistor 0-13 of AND-Gate ll falls to approximately ground potential in response to the coincident positive voltages at the cathodes of diodes D-8 and D-9. Thus, a bias current shunt path is closed through diode D-ll of AND-Gate Ill and the collector-emitter junction of transistor 0-13 of AND-Gate ll. Thus, the collector-emitter junction of transistor 0-14 of AND-Gate III is prevented from periodically being rendered conductive by the periodic closing of the shunt path through diode D-lZ and the collector-emitter junction of transistor 0-15, since the bias current path formed by diode D13 and resistor R-28 is shunted. Consequently, the normally charged capacitor C-2 connected across the collector-emitter junction of transistor 0-14 will not be able to discharge through that junction.
If the resistance R-l were above the minimum value required to effect unlocking, the decrease in the positive output voltage of the emitter-follower amplifier will not be sufficient to cause transistor 0-6 to become nonconductive. Consequently, the bias current shunt path through diode D-1 and the collector-emitter junction of transistor 0-6 remains closed and prevents transistor 0-7 from becoming conductive. In addition, the shunt path through diode D-8 of AND-Gate II and the collector-emitter junction of transistor 0-6 remains closed, preventing transistor 0-13 from becoming conductive.
A low value of resistance R-l will result in an excessive decrease in the positive output voltage of the emitter-follower, causing transistor Q-l2 to become conductive and thereby closing the bias current shunt path through diode D-Z of AND-Gate l and the collector-emitter junction of transistor 0-12. Thus, the shunt path through diode D-9 of AND-Gate ll and also closed. Consequently, transistor 0-13 of AND- Gate ll remains nonconductive, thereby holding open the bias current shunt path through diode D-ll of AND-Gate Ill and the collector-emitter junction of transistor 0-13.
Under either of the foregoing conditions, i.e., whether resistance R-l is too high so as to cause the output voltage of the emitter-follower amplifier to be higher than the predetermined value and thereby maintain transistor 0-6 conductive, or whether resistance R-l is too low so as to cause the output voltage of the emitter-follower amplifier to be lower than the predetermined value and thereby cause transistor 0-12 to become conductive, only one of the two required coincident inputs will be provided to AND-Gate ll. Consequently, the bias current path through diode D-l0 and resistor R-25 will remain shunted and transistor 0-13 will remain nonconductive, thus providing one of the two required coincident inputs to AND-Gate III by maintaining a high positive voltage at the cathode of diode Dl l The second input to AND-Gate lll is provided by the periodically nonconductive transistor 0-15 which causes transistor 0-14 to become periodically conductive each time transistor 0-15 becomes nonconductive as a result of discharging of capacitance C-3. it will be recalled that the bias voltages on transistor 0-11 are such that virtually any decrease in the output voltage of the emitter-follower amplifier will cause transistor 0-11 to become conductive, thus placing the necessary positive voltage on the cathode of diode D- to enable charging of capacitance C-3 which in turn causes the relaxation oscillator to become oscillatory With transistor 0-14 now periodically conductive, capacitor C-2 will discharge rapidly through the collector-emitter junction of that transistor, the magnitude of discharge current being limited only by the resistance of that junction. Thus, capacitor C-2 becomes virtually completely discharged very rapidly, and will shunt charging current from capacitor C-3 during each hiatus between periods of conductivity of transistor Q-l4. Thus, the relaxation oscillator is rendered nonoscillatory, and transistor 0-15 is again maintained continuously conductive. Transistor 0-14 simultaneously becomes nonconductive, since the bias current shunt path through diode D-l2 and transistor 0-15 is again closed. Since capacitor C-2 is much larger than capacitor C-3, it will continue to shunt most of the charging current from C-3 after the discharge path through the collector-emitter junction of transistor 0-14 is opened.
'The relaxation oscillator is thereby disabled for a period of time on the order of 40 seconds, during which the transistor 0-15 is maintained constantly conductive. During this period of disability of the relaxation oscillator, it is not possible to actuate the load circuit even if the proper value of resistance R-l is connected between terminals T-2 and T-3. If a variable resistance is connected between terminals T-2 and T-3 for the purpose of hunting for the correct value of keying resistance R-l, and that correct value is momentarily set, the period of time required for the parallel-connected capacitors C-2 and C-3 to charge to a level which will permit capacitor C-3 to render the relaxation oscillator circuit oscillatory is sufficiently long that a different and incorrect setting of the variable resistor will almost certainly be reached before the end of that time period, resulting again in the discharging of capacitor C-2 in the manner described above.
In the preferred embodiment of the invention shown in the drawing and described herein, the values of the various circuit components are as follows:
Resistances Capacilances R-I 50 kit (-1 l0 microfarads R-2 50 k0 C-2 microfaruds RJ l k!) (-3 5 microfarads R-4 I00 kfl R-S 100 k!) R-6 l k!) R-6 l0 k!) NPN Transistors R-8 l0 kil R-9 10k!) ZNSlJS R-IO l0 kil R-l I I00 kll R-l 2 H) k!) R-lJ l0 kfl PNP-Transistors R44 l0 k1) R-lS 100 k!) 2N4248 R-l6 100 k!) R-l7 L5 kil R-l8 R-26 It!) R-l9 4.7 kl] Unijunction Transistors R-ZO I00 kl] RZl l0 H1 ZNl67l R-ZZ l k!) R-23 l0 kQ R-24 kl] 10 k1] [(-25 I00 kit Diodes R-26 ll) k0 R47 10 Ml 1N9l4 R-Z8 100 kil R-29 100 k!) R-Jo I00 kl] R-3l l0 kl) R-SZ It) kll R-33 1S0 kil R-34 27 ohms It will be readily appreciated that the disclosed circuit will serve to perform a discrimination function with the third signal-generating circuit and the antitamper circuitry omitted, i.e., if transistors 0-11 and 0-15 and their bias circuitry were eliminated along with AND-Gates ll and Ill and the relaxation oscillator, the remainder of the circuit will operate only in response to the same predetermined range of keying resistances R-l. in applications where the antitamper feature is not deemed significant, this subcombination afiords obvious economies. Certain modifications of the disclosed circuit, e.g.,
the use of a latching circuit with the relay Re, or connecting an alarm such as a buzzer or a lamp in series with the collectoremitter junction of transistor 0-14, may be desirable in diverse applications of the disclosed circuit.
The advantages of the present invention, as well as certain changes and modifications of the disclosed embodiment thereof, will be readily apparent to those skilled in the art. It is the applicants intention to cover all those changes and modifications which could be made to the embodiment of the invention herein chosen for the purposes of the disclosure without departing from the spirit and scope of the invention.
What is claimed is;
l. A resistance-responsive circuit for controlling the energization and deenergization of a load comprising:
l. sensing circuit means having a pair of input terminals and operative to generate a predetermined output voltage in response to the connection of a keying resistance between said input terminals;
2. first, second and third signal-generating circuit means, each operative in response to said predetermined output voltage to generate first, second and third predetermined output signals, respectively; and
. signal-responsive circuit means having first, second and third input channels and being operative to alter the energization state of a load only in response to the coincident application of said first, second and third predetermined output signals to said first, second and third input channels, respectively.
2. A resistance-responsive circuit according to claim 1 wherein said signal-responsive circuit means comprises:
1. a first AND gate having first, second and third input channels connected to the outputs of said first, second and third signal-generating means, respectively;
2. charging circuit means comprising a resistance and a first capacitance connected in series, said first capacitance being dischargeable by said first AND gate when coincident signals are provided to said first, second and third input channels; and
. semiconductor switching means operative to control the energization state of a load, being maintained normally nonconductive by the voltage developed across said capacitance of said charging circuit means.
3. A resistance-responsive circuit according to claim 2 including antitamper circuit means coupled to each of said first, second and third signal-generating circuit means and operative for a predetermined period of time after actuation by connecting of a nonkeying resistance between said input terminals to prevent said signal-responsive circuit means from changing the energization state of a load when a keying resistance is connected between said input terminals.
4. A resistance-responsive control circuit according to claim 3 wherein said antitamper circuit means comprises:
1. a second AND gate controlled by said first and second signalgenerating circuit means;
2. a third AND gate controlled by said first AND gate and by said third signal-generating circuit means;
3. relaxation oscillator circuit means comprising a normally discharged during periods of oscillation of said relaxation oscillator circuit means, charging being controlled by said third signal-generating circuit means; and
4. a normally charged third capacitance connected in a parallel charging current path with said second capacitance and to a normally open discharge current path controlled by said second AND gate which is operative to close said discharging current path when a nonkeying resistance is connected between said input terminals.
5. A resistance-responsive circuit according to claim 1 wherein said sensing circuit means consists of a two-stage emitter-follower amplifier having a high input impedance at said in ut terminals.
resistance-responsive circuit according to claim 1 wherein each of said signal-generating means includes a normally conducting output transistor which provides said predetermined output signal by becoming nonconductive in response to said predetermined output voltage of said sensing circuit means.
7. A resistance-responsive circuit according to claim 1 wherein each of said signal-generating circuit means comprises:
1. threshold circuit means operative to generate a predetermined intermediate output in response to said predetermined output voltage of said sensing circuit means; and
2. output switching means operative to change its conductivity state in response to said intennediate output of said threshold circuit means.
8. A resistanceresponsive circuit according to claim 7 wherein:
l said threshold circuit means of said first signal-generating circuit means includes variable bias means set to maintain said threshold circuit means normally nonconducting;
2. said threshold circuit means of said second signalgenerating circuit means includes variable bias means set to maintain said threshold circuit means normally conducting; and
3. said threshold circuit means of said third signal-generating circuit means includes bias circuit means operative to maintain said threshold circuit means nonconductive and to enable said threshold circuit means to be rendered conductive by virtually any decrease in the normal'output of said sensing circuit means.
9. A control circuit for controlling the energization and deenergization of a load comprising;
1. first signal-generating circuit means operative in response to a first predetermined minimum input voltage to generate a first predetermined output signal;
2. second signal-generating circuit means normally operative to generate a second predetermined output signal, and further operative in response to a second predetermined minimum input voltage greater than said first predetermined minimum input voltage to cease generation of said second predetermined output signal; and
3. signal-responsive circuit means having first and second input channels and being operative to alter the energization state of a load only in response to the coincident application of said first and second predetermined output signals to said first and second input channels, respectively.
10. A control circuit according to claim 9 and further including a voltage divider circuit comprising a fixedly connected resistor and a selectively connectable keying resistor operative in combination to provide at their junction an input voltage falling between said first and second predetermined minimum input voltages.
UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,628,099 D es ember l lfill Inventor(s) Carl E. Atkins. et a1 It is certified that error appears in the aboveidentified patent and that said Letters Patent are hereby corrected as shown below:
Column 2, line 59, "N AND-Gate i" should read AND Gate I line 68, after "transistor Q-8" insert is reduced almost to ground potential, thereby causing the emittercollector junction of transistor Q-8 Column 3, line 48, after "and" insert the collector-emitter junction of transistor Q-l2 is Column 4, after line 36, under the heading "Resistances", YR- 6", second occurrence, should read R-7 "R-l8 R-26 kfl. should read R-18 10K ohms "12-24 kn 10 m" should read 12-24 10K ohms and "12-33 150 kfZ. should read 13-33 150 ohms Column .5, line 61, after "discharged", insert second capacitance which is alternately charged and discharged Signed and sealed this 31st day of October 1972.
EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer 1 Commissioner of Patents FORM P0-1050 (10-69) uscoMM-oc 60376-P69 U.S. GOVERNMENT PRINTING OFFICE 1969 O3$6-384.
nnurrn srlrns Parent @FFMJIE Chh'llllti'lh WE tdhtltt'llwhl Patent No. 3 ,628 O99 Inventor(s) Carl E", Atkins et al It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
Column 2;, line 59 N AND-*Gate i" should read AND Gate I line 68 after transistor (2-8 insert is reduced almost to ground potential thereby causing the emittercollector junction of transistor Q--8 m. Column 3 line 48, after and insert the collector-emitter junction of transistor Ql2 is Column 4 after line 36 under the heading '"Resistanoes It- 6" second occurrence should read R--7 R-==-l8 R 26 kl]. should read R -lB 10K ohms "Ii-24 kfl lOlcIl" should read R-24 lOK ohms and "II-33 150 kjt" should read e33 150 ohms M Column 5 line 61, after "discharged",, insert second capacitance which is alternately charged and discharged we o Signed and sealed this 31st day of October 1972m (SEAL) Attest:
EDWARD MmFLETCHER JR. ROBERT GOTTSCHALK Attesting Officer Cormnissioner of Patents FORM powso (wsg) USCOMM-DC 60376-P69 U,S. GOVERNMENT PRINTING OFFICE: 1969 0-366-334,