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Publication numberUS3629831 A
Publication typeGrant
Publication dateDec 21, 1971
Filing dateJan 3, 1967
Priority dateDec 27, 1962
Also published asDE1268181B
Publication numberUS 3629831 A, US 3629831A, US-A-3629831, US3629831 A, US3629831A
InventorsWilliam G Harvey, Leonard E Mikus
Original AssigneeHoneywell Inf Systems
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Data transmission controller for central to remote system
US 3629831 A
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Description  (OCR text may contain errors)

United States Patent Leonard E. Mikus Phoenix;

William G. Harvey, Glendale, both 01 Ariz. 613,707

Jan. 3, 1967 Dec. 21, 197 1 Honeywell information Systems Inc. Continuation of application Ser. No. 247,734, Dec. 27, 1962, now abandoned. This application Jan. 3, 1967, Ser. No. 613,707

inventors Appl. No. Filed Patented Assignee DATA TRANSMISSION CONTROLLER FOR CENTRAL TO REMOTE SYSTEM 13 Claims, 5 Drawing Figs.

US. Cl 340/152, 340/147, 340/151, 340/163 Int. Cl ll04q 5/00, H04q 1 1/00 Field of Search 340/ 147, 151, 152, 163

References Cited UNITED STATES PATENTS 7/1960 Bolgiano 340/163 UX Primary Examiner-Harold 1. Pitts Attorneys-F red Jacob and Edward W. Hughes ABSTRACT: An apparatus for controlling a link in transferring information between a plurality of remote stations and a central location employing automatic data-processing equipment wherein the apparatus communicates with the central location in character serial form and communicates with the remote station in bit serial form. Selection means comprising a plurality of counters are actuated in a given manner to indicate the selection of a particular station,

DATA TRANSMISSION CONTROLLER FOR CENTRAL TO REMOTE SYSTEM CROSS-REFERENCE This application is a continuation of application, Ser. No. 247,734 filed Dec. 27, 1962 by Leonard E. Mikus and William G. Harvey, titled Data Transmission Controller and now abandoned.

BACKGROUND OF THE INVENTION The present invention pertains to apparatus for controlling data transmission, and more specifically to apparatus for controlling data in binary form being transmitted between remote stations and a central location.

Recent improvements in computer design which increase their power and versatility and important new advances in the communication art have brought us to the threshold of a new era in computer utilization. The combination of computer technology and communications technology may be designed to form a vast network connecting all geographically separated operations of a business. The nerve center of the system is the data-processing center where timely and accurate information is received from diverse locations, acted upon, and results or replies sent back on demand.

Traditional concepts of communications have dealt with the transfer of information from one location to another, preferably with little or no change in form. However, the integration of automatic data-processing equipment and techniques with communications facilities provides a new dimension to communications planning. Data-processing equipment can calculate, sort, merge, compare, collate, correlate, abstract, filter, change format, and otherwise manipulate information. Thus, the computer-based data communication system is not only capable of transferring information from one location to another, but also of transforming it in content and format.

In order to take advantage of the new concept of data transmission however, a data traffic-controlling device must be developed which will accept information from the transmission lines, convert it into the language of the computer, and feed it into the computer for processing. It also must be able to accept outgoing information from the computer and process it for transmission over the lines. Previously, the bulk of controller devices developed have been too expensive to interest the small or even large organization. Furthermore, in many of the devices developed, it is necessary to record the output data from the controller on magnetic tape, paper tape, or punched cards before it can be entered into the computer. Still another shortcoming of many controllers is the limitation as to the number and types of transmission channels and the types of transmission code structures that can be accommodated.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data transmission controller that can accept data from a plurality of remote stations and transmit the received data to a computer.

It is also an object of the present invention to provide a data transmission controller that can accept data in a plurality of different codes, and translate these codes into an appropriate information structure for presentation to a computer.

It is still another object of the present invention to provide a data transmission controller that will enable a remote station to communicate directly with a computer memory.

It is a further object of the present invention to provide apparatus for controlling data transmission between a plurality of remote stations and a central location wherein the speed of communication from the remote station and the speed of communication to the computer are vastly different.

Briefly stated, in accordance with one aspect of the present invention, a data transmission controller is provided for receiving data, in digital form, from a plurality of remote stations. Each incoming line from a remote station is connected to a selecting means which scans the respective remote stations until a station is detected that either will transmit or receive information in communication with a data processor. The selected station may then either transmit or receive digital data through a timing unit and a code-converting storage means. The storage means may conveniently be a serial-parallel conversion register which accepts serial data and transmits serial data from and to remote stations while communicating in parallel with the data processor memory. Means are provided for the data-processing system to enter a remote station address into the data transmission controller, and for subsequent communication with the selected remote station after the data transmission controller matches the address received from the data-processing system with the proper remote station address. Further, logic is provided for requesting communication time with the computer upon receipt of a requesting signal from a remote station. Message length, and data processor memory locations are also determined by the data transmission controller of the present invention.

Apparatus is therefore provided to permit efficient utilization of data-processing time while enabling remote stations to communicate directly with a data processor memory.

BRIEF DESCRIPTION OF THE DRAWINGS The invention, both as to its organization and operation together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which:

FIG. 1 is a block diagram of a data transmission controller constructed in accordance with the teachings of the present invention.

FIG. 2 is a detailed block diagram of the scan counter of FIG. 1.

FIG. 3 is a detailed block diagram of the timing unit of FIG. 1.

FIG. 4 is an illustration of representative data pulses useful for describing the operation of the present invention.

FIG. 5 is a detailed block diagram of the serial-parallel conversion register of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a data transmission controller is shown constructed in accordance with the teachings of the present invention. A plurality of remote stations 10, ll, 12, and 13 (in the embodiment chosen for illustration a total number of 15 remote stations are indicated as connected to the data transmission controller of the present invention) are connected via transmission lines 15 to the data transmission controller illustrated generally within the heavy lines 16. Each of the remote stations may comprise any type of remote terminal equipment suitable for encoding and transmitting information in binary serial fashion. For example, the remote inquiry stations may be keyboard-operated transmission and typewriter-receiving channels.

The transmission lines 15 may be conventional two wire conductors connecting separate locations within a factory or industrial complex, or the transmission lines could be national and international telephone or telegraph communication facilities. Each of the remote stations is connected to the data transmission controller 16 through a remote station selecting means or scan counter 20. Associated with each remote station, and connected to the incoming transmission lines from the remote station, is a station flip-flop shown in FIG. I at 21, 22, 23, and 24.

A paper tape reader/punch 30 may also be connected to the scan counter 20; a paper tape flip-flop 31 is provided in the event the paper tape device is connected to the scan counter. The scan counter and the associated station flip-flops enable the data transmission controller to sequentially scan the incoming transmission lines from the remote stations and determine which station will be permitted access to the computer memory or which station will receive a communication from the computer memory. A timing unit 35 receives the serial bit data from the cognizant transmission line asynchronously to computer timing, and retimes the data bits to synchronize with the computer clock. The timing unit also enables the data being communicated to a remote station from the computer memory to be transmitted at a predetermined transmission rate compatible with the type of transmission network used. This rate may be substantially different from data transmission rates within data processors. The information received from the remote station over the corresponding transmission line is in bit serial form. Accordingly, to enable this information to be made available to the computer memory in the least amount of time, and in accordance with the computer timing, a storage means such as serial-parallel conversion register 36 is provided which receives the remote station data in hit serial form until an adequate number of bits have been stored to form a data word.

The transfer of information from the data transmission controller to the computer memory is thus from the serial-parallel conversion register in bit parallel, rather than bit serial. Conversely, information received from the computer memory in the form of bit parallel or word serial form, is strobed from the serial-parallel conversion register to the remote station in bit serial form. The combination of scan counter 20, timing unit 35, and serial-parallel conversion register 36 enable the data transmission controller of the present invention to readily accept bit serial information from remote stations and bit parallel information from a computer memory while maintaining efficient communication paths for data between any of the selected remote stations and the computer memory.

The data transmission controller of the present invention is also provided with an interface 40 which receives and accepts information of the appropriate logic level for communication with the transmission lines 15, and converts these logic levels to the appropriate levels for communication with the computer memory.

A mode change counter 41 is provided to impose a delay between the transmit and receive modes, and the receive and transmit modes. This delay enables all of the circuits involved in the transmission and reception of data to switch from the transmit mode to the receive mode, and vice versa. The mode change counter 41 may also be utilized to impose a somewhat greater delay when the communication between the computer memory is to be with the paper tape reader/punch 30. The data exchanged between the remote stations and the computer memory are generally in the form of successive characters with a predetermined number of characters constituting a message. Accordingly, when a message is transferred from the computer memory to a remote station, the computer memory address marking the start of the message may be stored in an address counter 42 provided for that purpose.

A character counter 43 is provided to count the number of characters in a message. The address counter 42 and the character counter 43 thereby permit the addressing of a specific memory location within a computer memory, and subsequently count the characters as they are read from memory until a predetermined message length has been attained. When the communication is from the computer memory to a remote station without the remote station having first requested the communication, a transmit address register 45 enables the computer memory to stop the scan counter at the appropriate station so that the message from the computer memory may be directed to the proper remote station. When the communication is initiated by a request from a remote station, the request initiates a logical sequence to address the computer memory. The initial request logic may conveniently be indicated in FIG. 1 in block form at 50. The initial request logic recognizes a request by a remote station at the scan counter 20 for communication with the computer memory, and subsequently initiates the appropriate action to request communication with the computer.

The interface 40 of the data transmission controller 16 may be connected to a data-processing system, a portion of which is indicated at 51. The data-processing system may generally be of the type having a peripheral selection device such as a controller selector S2 for controlling access to the computer memory 53. Several peripheral equipments may be connected to the computer through the controller selector 52, the latter being useful for switching, granting priority, providing queueing, and selecting the appropriate peripheral equipment for each given operation. Therefore, a request by the data transmission controller 16 for communication with the computer memory would constitute a request to the controller selector 52 for priority. Upon receipt of recognition from the controller selector 52 that priority is afforded to the data transmission controller 16, further steps may be taken to receive the message from the requesting remote station and transfer the message to the computer memory.

Referring to FIG. 2, a more detailed block diagram of the scan counter 20 and transmit address register 45 of FIG. I are shown. Computer clock pulses are admitted to a gate 60 which applies these clock pulses to a four-stage binary counter 61. The gate 60 and the binary counter 61 may be of any conventional design wherein the counter is advanced one count for' each clock pulse received. The counter 61 is symbolically illustrated as four flip-flops each representing succeeding higher powers of the radix 2. Thus, as computer clock pulses are received by the gate 60 and applied to the counter 61, the counter proceeds to count through the I6 possible binary combinations of the four flip-flops. The output of the counter 61 is applied to the computer, to a station decode 63, and to compare logic 64. A second counter 62, similar to the counter 61, receives parallel binary information from the computer (representing a desired station address) and applies this information to the compare logic 64. The results of the comparison of counters 61 and 62, applied to the compare logic 64, result in the compare logic signal being applied through an inhibit signal generator 67 to the gate 60.

The station decode 63 is provided with 16 outputs (only two of which are shown in FIG. 2), one for each station. For example, the output indicated by the line 70 is applied to an AND- gate 71 and to the station No. 1 enable circuit 72. The second input to the AND-gate 71 is supplied by a flip-flop 73, unique to station No. 1, which is set or reset in accordance with the information received from the remote station as indicated by the line 75. The station No. 1 enable circuit 72 is also connected to the correspondingly numbered remote station, and is also connected to the serial-parallel register. The output of the AND-gate 71 is applied to the initial request logic indicated in FIG. I at 50.

When the computer desires to communicate with a specific remote station, the address from the computer, (the computer-generated address is the result of the computer program) is applied from the computer through the interface 40 (FIG. 1) to the register 62. The output of the register 62 is applied to the compare logic 641 which also receives the information contained in counter 61. The computer clock pulses applied through the gate 60 to the counter 61 cause the counter 61 to continue to count until the address contained in counter 61 corresponds to the address placed in the counter 62 from the computer. The comparison of the information or addresses contained in the counters 61 and 62 takes place in the compare logic circuit 64. When a positive comparison occurs, a signal, generated in the compare logic, is applied to the inhibit signal generator 67 which, in turn, applies an inhibiting signal to the gate 60. This inhibiting signal applied to the gate 60 prevents further computer clock pulses from being applied to the counter 61. Therefore, the address contained in the counter 61 represents the address of the remote station with which the computer will communicate. The contents of the counter 61, applied to the station decode 63 results in the gating of the designated station enable circuit thereby connecting the appropriate remote station through the corresponding station enable circuit to the serial-parallel register.

When a remote station desires access to the computer, the corresponding remote station applies a signal (for example station No. l) to the conductor 75 which sets the flip-flop 73. The output from flip-flop 73 is applied to the AND-gate 71. The counter 61 continues to count as it receives computer clock pulses; the output of counter 61, applied to the station decode 63, ultimately results in the application of a signal to the conductor 70. The second input to the AND-gate 71 is thus applied from the conductor 70; thus, AND-gate 71 applies a signal to the initial request logic to thereby request priority to communicate with the computer. It may be noted, that throughout the operation of the scan counter and transmit address register shown in FIG. 2, the computer is proceeding with its normal program without interruption, and will not be interrupted except in accordance with a predetermined controller sequence.

Referring to FIG. 3, a more detailed block diagram is shown of the timing unit 35 of FIG. 1. The timing unit provides appropriate strobing pulses to sample incoming information pulses and provide the appropriately strobed information to the serial-parallel conversion register. The timing unit also provides the necessary conversion from serial transmission speeds to parallel computer speeds. Computer clock pulses are applied through a gate 80 to a l2-stage counter 81. The counter communicates the present count contained in the counter through a timing plug 82 to a strobe decode circuit 83. Since the computer clock pulses will have a repetition rate much higher than the repetition rate of the successive information pulses being transmitted, the rate at which information pulses occur is reduced by counting pulses in the counter 81 and providing a single strobe after a predetermined number of computer clock pulses have been counted. Therefore, the function of the strobe decode circuit 83 is to yield a strobe pulse when the predetermined number of clock pulses have been counted in the counter 81. The function of the timing plug 82 is to provide a convenient means for changing the ratio of computer clock pulses to strobe pulses. This may conveniently be done by providing the timing plug 82 between the counter 81 and the strobe decode circuit 83. Thus, while the strobe decode circuit 83 may be designed to provide a strobe pulse for each x number of counts in the counter 81, the timing plug 82 may readily be designed to apply one out of every y counts of the counter 81 to the strobe decode circuit 83. The result of utilizing this timing plug would then be that a strobe pulse is provided by the strobe decode circuit 83 after every xy computer clock pulse occurs.

The strobe pulses from the strobe decode circuit 83 are applied to the serial-parallel register and to a strobe counter 85 The strobe counter 85 counts the number of strobe pulses applied thereto and provides this count to the decode circuit 86. The decode circuit 86 will provide a signal indicating that the strobe counter 85 has counted the number of strobe pulses required for the particular code being used by the remote stations and the data transmission controller. For example, if a five-bit code were utilized, the decode circuit 86 would provide a signal when seven strobe pulses had been counted by the strobe counter 85 (five information bits, one start bit, and one stop bit). The output of the decode circuit 86 is applied to the gate 80 to prevent further clock pulses from being applied to the counter 81. The output of the decode circuit 86 is also utilized to signal the computer that the character in the serialparallel register is ready for dump to the computer memory (in the receive mode).

An example of the operation of the timing unit is illustrated in FIG. 4. It is assumed in FIG. 4 that the code being utilized by the remote stations and the data transmission controller is a five-bit code. The serial input characters received from the remote station is a two-level code, i.e., a low voltage level indicates a binary l and a high voltage level indicates a binary 0, as indicated in FIG. 4. The initial rise in voltage indicates a start pulse and a strobe pulse occurs at the center of the first bit. Thereafter, strobe pulses are provided by the timing unit at predetermined intervals in accordance with the bit repetition rate utilized by the transmission system. The timing of the strobe pulses is provided by the timing unit in accordance with the description of the conversion of computer clock pulses to strobe pulses as shown in FIG. 3. The strobe pulses may thus be termed as sampling pulses" at which time the information being received from the remote station is sampled to determine whether the voltage level is high or low (whether the information being received at that instant is a binary 0 or a binary l). The illustration shown in FIG. 4 indicates that in bit positions 1, 2, and 4 the voltage level is low and consequently a binary l is represented; in bit positions 3 and 5, a high voltage level exists, and a binary 0 is indicated. The five-channel code thus conveyed by the serial input character of FIG. 4 is 1 1010.

Referring to FIG. 5, a more detailed block diagram of the serial-parallel conversion register 36 of FIG. 1 is shown. The serial-parallel conversion register accepts parallel information from the computer and converts this information into serial form for transmission to remote stations. Similarly, the serial information received from remote stations is converted into parallel form for transfer to the computer memory. As noted previously, the rate of transmission to remote stations is determined by the transmission system; and transmission from the data transmission controller is controlled by the timing unit. Further, communication between the data transmission controller and the computer is determined by the computer clock rate, and is consequently controlled by, and occurs at, the frequency of the computer clock. A shift register receives serial input pulses from the remote stations, and simultaneously receives strobe pulses from the timing unit. As indicated previously in connection with the description of the timing unit in FIGS. 3 and 4, the information received from remote stations is in the form of two-level voltage pulses, one voltage indicating a binary l and a second voltage level indicating a binary 0. As these pulses are applied to the shift register 90, the strobe pulses from the timing units are also applied to the shift register 90. When the strobe pulses are applied, the voltage level of the signal from the remote station is sampled, and the information stored in the shift register.

A parallel input circuit 91 receives information characters in bit parallel from the paper tape recorder and the computer. Similarly, a parallel output circuit 92 transfers information characters in bit parallel to the paper tape recorder and the computer. The parallel input circuit 91 transfers the information received by it to the shift register 90, and the shift register 90 transfers the information contained therein to the parallel output circuit 92. The two dotted enclosures 94, shown in FIG. 5, represent patch plugs which may be utilized for code alteration such as digit transposition. In this manner, code flexibility is provided within the data transmission controller in the communication of data between the paper tape recorder, the computer, and the data transmission controller.

The output from the shift register 90 is applied to the parallel output circuit 92, to the corresponding remote station through the timing unit, and is also applied to a control character decode circuit 98. Certain characters have special significance in codes normally utilized for transmission over long distances. Such codes as figures to designate an alphabetic character, numbers" to designate a numeric character, and an End of Message, etc. These specific control characters are detected by the control character decode 98 which provides an appropriate signal as a control function.

When the data transmission controller is in the receive mode (receiving information from a remote station for transmission to a computer) the serial infonnation from the remote station is applied to the shift register 90 simultaneously with the strobe pulse from the timing unit. As the serial information is stored in the shift register 90, the predetermined number of bits, in accordance with the designated code, is obtained resulting in a signal from the decode circuit 86 of FIG. 3 indicating that the character in the shift register is ready for dump to the computer memory. Accordingly, the information in the shaft register 90 is transferred through the parallel output circuit 92 to the computer. When the data transmission controller is in the transmission mode (information to be transmitted from the computer to a remote station), the information is transferred from the computer memory, through the parallel input circuit 91 to the shift register 90. When the transfer of information from the parallel input circuit 91 to the shift register 90 is complete, the timing unit applies strobe pulses to the shift register causing the information contained therein to be shifted out of the register in bit serial fashion. It may be noted that the strobe pulses applied to the shift register during the transmission of information from the shift register to the remote station occur at the proper bit repetition or frequency for the transmission system.

The block diagrams represent circuitry that may be constructed in accordance with well-known principles and dataprocessing techniques. For example, the usual decode circuits comprise a conventional interconnection of logic elements such as AND or OR gates. When certain conditions obtain, the outputs from AND and OR gates are applied to still further AND and OR gates to yield an output signal indicating the logical conditions that exist at the input to the decode circuit. Similarly, shift registers, counters, and compare logic circuits are well known in the art. Examples of these circuits may be found in such standard texts as: Digital Computer Components & Circuits" by R. K. Richards, Handbook of Automation Computation and Control" by Eugene M. Grabbe, Digital Computer and Control Engineering" by Robert Steven Ledley.

Returning to FIG. 1, the operation of the data transmission controller of the present invention may now be described. In the description of operation, we will first assume that the computer is processing information in accordance with a predetermined program, and the data transmission controller is scanning the remote stations. There is presently no communication between the computer and any of the remote stations. We will further assume that the first instance of communication between the computer and a remote station will be at the request of the remote station. Accordingly, the scan counter 20 of the data transmission controller proceeds to scan the remote stations and paper tape recorder at a rate determined by the computer clock rate. Assuming that a remote station requests permission to communicate to the computer, the corresponding flip-flop will be set. The scan counter will continue scanning until the address of the requesting station is reached at which time the scan counter locks on that station. When the scan counter stops scanning and locks on the remote station, the initial request logic 50 provides a signal through the interface 40 to the controller selector 52 requesting priority for the data transmission controller along with other peripherals that may be connected to the computer. Assuming that priority is granted, the contents of the address counter 42 are applied through the interface 40 to the memory address register of the data-processing system 51. It may be noted that usually a dataprocessing system to be utilized in connection with remote inquiry stations will reserve a specific memory location for storing the address of the requesting remote station. Accordingly, the contents of the address counter 42 will normally be the predetermined reserved memory address of the computer. When this address is placed in the memory address register of the computer through the interface 40, the address of the requesting station (already present in the scan counter) may be transferred directly to the memory location designated by the address in the memory address register. Therefore, the remote station has now requested communication with the computer. The address of the requesting station has been placed in the computer memory, and the data transmission controller is now in a state of readiness awaiting computer action.

During this time, the computer has continued to process information in accordance with its program, and no interruption has been made in the processing sequence; however, it is now necessary for the computer program to determine whether or not to receive the information from the remote station or whether to ignore the request. Accordingly, under computer program control, the computer program may be interrupted to communicate with the remote station or may continue its processing and ignore the request. It will be assumed that the computer program has been designed to receive the information from the remote station at this time; therefore, the computer may now initiate a transmit sequence to tell the remote station that it will receive the message. The usual communication from the computer will be contained in a computer word or words which will turn the data transmission controller from the receive to the transmit mode and will then send characters to the remote station indicating that the computer will receive the message. Reception of this command will set the mode change counter 41 to thereby instigate an appropriate delay and allow ample time for any type of communication line equipment to change modes. The address of the station to which this message is to be sent (it may be recalled that the address of the station was previously placed in the computer memory) is placed in the transmit address register 45. If the address in the transmit address register 45 corresponds to the scan counter address 20 (which will be the case in most instances) no further scanning is necessary; however, if the two addresses do not match, then the scan counter scans until the scan counter address corresponds to the transmit address register 45 as described previously in connection with FIG. 2. The starting address of where to put the information when it is received from the remote station may now be put into the address counter 42; also, the maximum message length may be placed in the character counter 43. It may be noted that while the receipt of the command words or signals from the computer to the data transmission controller switches the mode change counter 41, it is not necessary to delay the dataprocessing system while the mode change delay proceeds; rather, after indicating that it will receive the transmission from the remote station, the data-processing system then returns to its program and continues to process information while the data transmission controller proceeds to ready the remote station for transmission. The first character to be transmitted to the remote station is then transferred, bit parallel, into the serial-parallel conversion register from the computer memory. Simultaneously, the address counter 42 is incremented by l, and the character counter 43 is incremented by l. It may be noted that address counter determines where the information will be obtained in the computer memory, and the character counter determines how many characters have been sent during this message transmission from the computer memory. In this manner, it is necessary merely to designate the beginning address in computer memory for the transmission of information, and the maximum message length, and it is unnecessary to designate the specific address of each character of information prior to the transmission of that information. The timing unit 35 thus strobes the serial-parallel conversion register 36 and the character contained in the seri al-parallel conversion register 36 is transmitted to the remote station in bit serial form. At the completion of the transmission of the character contained in the serial-parallel conversion register, the timing unit is disabled, and the computer priority is again requested for the next character. It may be noted that during the transmission of the character contained in the serial-parallel conversion register the computer has returned to its own program and is processing information without waiting for the character in the conversion register to be strobed out in bit serial form to the remote station. The remaining characters in the message from the computer are treated similarly, and each is placed in the serial-parallel conversion register in its turn, while the address counter and character counter 42 and 43, respectively, are incremented by 1. The computer then returns to its data-processing tasks and the data transmission controller of the present invention transmits the character in bit serial form to the remote station. When the transmission is complete, an End of Transmission code is included with the last character of the message. The End of Transmission code is detected by the control characters decode circuit 98 of FIG. which yields a signal to the computer to indicate that the designated information contained in the computer memory has been transmitted to the remote station and that the computer program may now decide on the next course of action. For example, the program may indicate that the data transmission controller should switch to the receive mode and receive information from the remote station (as requested initially) may return to the scanning mode, or may select another station for communication.

Assuming that the computer program has indicated that the computer is ready to receive the requesting station, the computer may send the necessary signals to turn the data transmission controller to the receive mode (thus activating the mode change counter 41 to instigate the appropriate delay to permit the necessary transmission lines to change mode) the starting address (where incoming information is to be stored in the computer memory) is placed in the address counter 42, and the maximum message length which may be received from the remote station is placed in the character counter 43. The remote station may then send its information in bit serial form which will be placed in the serial-parallel conversionregister 36v When a complete character has been strobed into the conversion register, the data transmission controller requests computer priority along with other connected peripheral equipments. Assuming that the priority is granted, the starting address (contained in the address counter 42) is placed in the computer memory address register, and the character contained in the serial-parallel conversion register is transferred bit parallel to the computer memory at the memory location indicated by the address counter 42. The address counter 42 and the character counter 43 are subsequently incremented by l. Thus, subsequently received information will be placed in succeeding memory locations in the computer memory, and the character counter will account for the number of characters received. I

The next-succeeding character is received in bit serial form from the remote station, and having been placed in the serialparallel conversion register 36, is transferred bit parallel to computer memory. Similarly, the address counter and character counters 42 and 43, respectively, are incremented by 1. Since the transfer in bit parallel form of the character in the serial-parallel conversion register to the computer memory is at the computer clock rate, whereas the bit rate of information from the remote station is at remote station transmission bit rate, and since the latter is a substantially lower rate than the former (computer clock rates may conven' tionally be I megacycle whereas data transmission rates may be 75 cycles or bits per second), the information is transferred in parallel from the serial-parallel conversion register to the computer memory, and the address counter and character counters are incremented by 1, before the next-succeeding bit is received from the remote station at the remote station transmission bit rate. The transmission from the remote station continues until an End of Message character is received from the remote station at which time the data transmission controller requests a program interruption of the data-processing system. it may be noted that during the entire time of data reception by the computer, the computer was continuing to process information in accordance with its program without disturbance from the data transmission controller. Only after the entire message was received by the data transmission controller from the remote station and transferred to the designated computer memory locations was a request made to interrupt the computer program. At this instant, the next course of action may be determined in accordance with the specific computer program. For example, the computer may be programmed to process the information received from the remote station, may be programmed to transmit a wait until later for answer signal to the remote station and process the received information at a later time, may be programmed to ignore the received information, may be programmed to consider the received information and transmit to another remote station, etc. it may be seen that the data transmission controller provides appropriate buffering between remote stations and the data processing system while permitting the remote stations to transmit and receive data in bit serial form at remote station transmission bit rates; simultaneously, the data transmission controller provides a means for a data-processing system to communicate with a remote station in bit parallel form at computer clock rates. Thus, apparatus is provided that may be utilized with a high-speed data-processing system to form a convenient link between the processing system and a relatively slower and distantly placed remote inquiry station or stations.

While the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications in structure, arrangement, proportions, the elements, materials, and components, used in the practice of the invention, and otherwise, which are particularly adapted for specific environments and operating requirements, without departing from those principles. The appended claims are therefore intended to cover and embrace any such modifications, within the limits only of the true spirit and scope of the invention.

We claim:

1. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of a said remote station, means connected to said first and second counters for comparing the contents of said counters and for generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, storage means interconnecting said stations and said central location for receiving data transmitted by said remote stations and said central location for temporary storage, and timing means connected to said storage means for controlling the rate of transfer of data from said storage means to said remote station.

2. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of a remote station, means connected to said first and second counters for comparing the contents of said counters and for generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, storage means including a shift register connected to said central location for transmitting and receiving information in bit parallel form, said storage means also connected to said stations for transmitting and receiving information in bit serial form, and timing means connected to said storage means for controlling the rate of transfer of data from said storage means to said remote stations, said timing means including a timing counter for counting at a predetermined rate, and a decoding circuit connected to said timing counter for generating strobe pulses in response to a predetermined count of said timing counter.

3. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means at said central location for selecting one of said remote stations, said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of said one of said remote stations, means connected to said first and second counters for comparing the content of said counters and for generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, storage means interconnecting said stations and said central location for simultaneously receiving a predetermined number of data bits from said central location, and timing means connected to said storage means for enabling the serial transfer of said data bits from said storage means to the selected remote station at a predetermined rate.

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4. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means at said central location for selecting one of said remote stations, said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of a remote station, means connected to said first and second counters for comparing the contents of said counters and generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, timing means connected to said selecting means and responsive to the selection of a remote station for generating a strobing pulse for each data bit received, storage means connected to said selecting means and to said timing means for storing a data bit each time a data bit and a strobing pulse are simultaneously received, and means responsive to a predetermined number of strobing pulses for enabling the simultaneous transfer of said stored data bits from said storage means to said central location.

5. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means at said central location for selecting one of said remote stations. said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of a remote station, means connected to said first and second counters for comparing the contents of said counters and for generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, timing means connected to said selecting means, said timing means including a timing counter for counting at a predetermined rate, a decoding circuit connected to said timing counter for generating strobe pulses in response to predetermined counts of said timing counter, storage means connected to said selecting means and to said timing means for storing a data bit each time a data bit and a strobing pulse are simultaneously received, and means responsive to a predetermined number of strobing pulses for enabling the simultaneous transfer of said stored data bits from said storage means to said central location.

6. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a first counter for counting at a predetermined rate and a second counter containing the address of said remote station, means connected to said first and second counters for comparing the contents of said counters and for generating an inhibit signal when the contents are identical, said first counter responsive to said inhibit signal for stopping counting, storage means interconnecting said stations and said central location for receiving data transmitted by said remote stations and said central location for temporary storage, said storage means comprising a shift register connected to said central location for transmitting and receiving information in bit parallel form, said storage means also connected to said selecting means for transmitting and receiving information in bit serial form, and timing means connected to said storage means for controlling the rate of transfer of data from said storage means to said remote station.

7. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a counter for counting at a predetermined rate and a register containing the address of said remote station, means connected to said counter and said register for comparing the contents of said counter and register and for generating an inhibit signal when the contents are identical, said counter responsive to said inhibit signal for stopping counting, storage means interconnecting said stations and said central location for receiving data transmitted by said remote stations and said central location for temporary storage, and timing means connected to said storage means for controlling the rate of transfer of data between said storage means and said remote stations.

8. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a counter for counting at a predetermined rate and a register containing the address of said remote station, means connected to said counter and said register for comparing the contents of said counter and register and for generating an inhibit signal when the contents are identical, said counter responsive to said inhibit signal for stopping counting, storage means coupled to said central location for receiving data transmitted by said remote stations and said central location for temporary storage, means responsive to the state of said counter when stopped for coupling said storage means to the remote station identified by said counter, and timing means connected to said storage means for controlling the rate of transfer of data between said storage means and said remote station.

9. The combination as defined in claim 8 wherein said register receives the address from the central location.

10. The combination as defined in claim 8 wherein said register receives the address from a remote station.

11. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a counter for counting at a predetermined rate and a register containing the address of a remote station, means connected to said counter and said register for comparing the contents of said counter and register and for generating an inhibit signal when the contents are identical, said counter responsive to said inhibit signal for stopping counting, storage means includ' ing a register coupled to said central location and said stations for transmitting and receiving information in bit form, means responsive to the state of said counter when stopped for coupling said storage means to the remote station identified by said counter, and timing means connected to said storage means for controlling the rate of transfer of data from said storage means to said remote stations, said timing means including a timing counter for counting at a predetermined rate, and a decoding circuit connected to said timing counter for generating strobe pulses in response to a predetemtined count of said timing counter.

12. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means at said central location for selecting one of said remote stations, said selecting means including a counter for counting at a predetermined rate and a register containing the address of said one of said remote stations, means connected to said counter and said register for comparing the content of said counter and register and for generating an inhibit signal when the contents are identical, said counter responsive to said inhibit signal for stopping counting, storage means coupled to said central location for simultaneously receiving a predetermined number of data bits from said central location, means responsive to the state of said counter when stopped for coupling said storage means to the remote station identified by said counter, and timing means connected to said storage means for enabling the transfer of said data bits from said storage means to the selected remote station at a predetermined rate.

13. Apparatus for controlling data transmission between a plurality of remote stations and a central location comprising, selecting means for selecting a remote station for communication with said central location, said selecting means including a counter for counting at a predetermined rate and a register containing the address of said remote station, means con nected to said counter and said register for comparing the contents of said counter and register and for generating an inhibit signal when the contents are identical, said counter responsive to said inhibit signal for stopping counting, storage means interconnecting said stations and said central location for receiving data transmitted by said remote stations and said central location for temporary storage, said storage means

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Classifications
U.S. Classification340/9.17, 367/76
International ClassificationH04L12/00, G06F13/22, G06F13/38, H04L5/22, H04Q9/14, H04L13/08
Cooperative ClassificationH04Q9/14, H04L5/22, G06F13/22, H04L12/00, G06F13/38, H04L13/08
European ClassificationG06F13/22, H04Q9/14, H04L5/22, H04L12/00, H04L13/08, G06F13/38