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Publication numberUS3633167 A
Publication typeGrant
Publication dateJan 4, 1972
Filing dateMay 25, 1970
Priority dateMay 25, 1970
Also published asCA959556A1, DE2125559A1
Publication numberUS 3633167 A, US 3633167A, US-A-3633167, US3633167 A, US3633167A
InventorsHedin Robert A
Original AssigneePhinizy R B
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Security system
US 3633167 A
Abstract
A security system for controlling access to an area includes a lock responsive to a control for providing access to a secured area. The control includes means for sequentially generating a plurality of coded signals and circuitry responsive to the signals for operating the lock or an alarm. The lock is actuated to provide access to the secured area when the proper signals are sequentially generated in a predetermined manner. The alarm is actuated and entry to the secured area is denied when incorrect coded signals are generated or the sequence of the coded signals is improper. An ambush feature is provided by enabling the circuitry for operating the lock to simultaneously actuate the lock to provide access to the area and the alarm when predetermined coded signals are generated. The system further includes timer means which reset the circuitry to prevent access to the area when the proper coded signals are not sequentially generated in a predetermined time interval.
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United States Patent v [72] Inventor Robert A. Hedin San Pedro, Calif. [21] Appl. No. 40,324 [22] Filed May 25, 1970 [45] Patented Jan. 4, 1972 [73] Assignee R. B. Phinizy Anaheim, Calif.

[54] SECURITY SYSTEM 10 Claims, 6 Drawing Figs.

[52] US. Cl 340/164, 70/278, 317/134 [51] lnt.Cl G051) 1/00, HOlh 47/00 [50] Field of Search 340/164; 317/134 [5 6] References Cited UNITED STATES PATENTS 2,973,507 2/1961 Grondin 340/164 3,320,490 5/1967 Becket al.. 317/134 3,321,673 5/1967 Wolfe... 317/134 9075,75 CO/VZPGLLEF 2 WA z/vrawvcs (foo?) I v (/0 A1 A25 jyfrJA-I PE r u 55 /51/55 I I JQKKI'J Primary Examiner Donald J. Yusko Attorney-Teagno & Toddy ABSTRACT: A security system for controlling access to an area includes a lock responsive to a control for providing access to a secured area. The control includes means for sequentially generating a plurality of coded signals and circuitry responsive to the signals for operating the lock or an alarm. The lock is actuated to provide access to the secured area when the proper signals are sequentially generated in a predetermined manner. The alarm is actuated and entry to the secured area is denied when incorrect coded signals are generated or the sequence of the coded signals is improper. An ambush feature is provided by enabling the circuitry for operating the lock to simultaneously actuate the lock to provide access to the area and the alarm when predetermined coded signals are generated. The system further includes timer means which reset the circuitry to prevent access to the area when the proper coded signals are not sequentially generated L iq tsqvia dfim nte ala v .55 awe/.1;

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SHEET 3 OF 4 Q3 NQKW W NK air-333L167 PATENTEU JAN 4 B72 SHEET H []F 4 Door Latch A/orm Dr/ ver /5 f 0 Act/Va Memory E/emenfs Pas/7 Buffons Fig 6 SECURITY SYSTEM This invention relates to security systems and more particularly to pushbutton-operated control apparatus.

At the present time there is available a number of security systems for controlling entry to or access from a given area, room, building or the like. These security systems utilize an electrical key, magnetic card or pushbuttons forgenerating coded electrical signals for controlling access to and exit from an entrance into a controlled area. In all of these systems there is required some means for the generation of the correct coded combination of signals to properly operate the system and gain access or exit from the controlled area. In addition, in the prior art pushbutton-actuated security systems a further security feature is included in that it is required that the generation of the correct combination of coded signals be generated within a preselected time period before the correct combination of signals will be effective for operating the system. Pushbutton-operated security systems of this type are exemplified by the disclosures of US. Pats. Nos. 2,855,588, 2,561,076 and 2,677,814. In the systems that are operated by means of coded electrical keys or cards and pushbuttons, there is presently known systems that employ combinations of these coded operating devices for generating the correct com bination of coded signals to further increase the security afforded by such systems. A system that includes pushbutton control and a card key switch is disclosed in U.S. Pat. No. 3,234,516. The pushbutton control systems that are presently known are generally implemented in terms of relay circuits and other electromagnetic elements which have been proven to have limited reliability and require periodic maintenance.

These electromagnetic pushbutton systems generally are noisy.

and allow unauthorized access to the area by detecting the noises or clicks for breaking down the combination and thereby allow the pushbutton system to be readily operated. At the present time there is a need for an electronic security system that is operable through pushbuttons or electrical switches and yet has no electromagnetic components, switches or relays other than the operating pushbuttons or electrical switches and is relatively inexpensive but affords a high degree of security for gaining access to or exit from a controlled area. I

The present invention provides an improved, reliable electronic security system that is operable from pushbuttons, electrical keys or combinations of the two offering almost foolproof protection for limited access areas. The pushbutton security system of the present invention allows the preselected combination for operating the system to be readily changed, in a matter of seconds, to prevent the unauthorized use of the system. The present invention also advantageously includes the provision for signaling an alarm, either audible or silent, in case there is an unauthorized attempt to gain access to an area. The alarm features may be combined with an antimanipulation circuit that eliminates the random switching of the pushbuttons for accidentally generating the correct combination of coded signals for operating the system. This feature causes an alarm to be actuated whenever a coded signal is generated that is not included within the preselected combination of signals and in addition an alarm will be activated in the event of the generation of the preselected combination of signals within a preselected time interval followed with the generation of a wrong signal and still within the preselected time interval. The generation of a wrong signal in combination with the generation of the correct group of signals is indicative of an unauthorized attempt to use the system and accordingly an alarm is signalled. In the same fashion, in the event that a fortuitous selection of the combination of pushbuttons that is the correct combination results from the simultaneous operation of a group of pushbuttons, the system of the present invention is defined to prevent access to the controlled area by the prevention of the sequential entry of the signals into the circuitry of the system.

Another important advantage of the security system of the present invention is that it affords further protection for unauthorized use of the system through an ambush protection feature which allows an authorized person to generate the combination of signals necessary for gaining access to a con trolled area when he is forced to operate the system against his will and at the same time generate a signal that is operative for activating an alarm so that the entry appears to have been accomplished under normal circumstances. The system, then, in effect is responsive not only to a preselected combination of signals but also a second combination of signals which is equivalent to the preselected combination for renderingthe system operative and includes a signal for activating an alarm that preferably is a secret alarm so that the unauthorized individual is not aware of the actuation of the alarm. This alarm may be located in a remote place, such as at a police station.

From a structural standpoint, the present invention comprises solid-state apparatus for operating a controlled device through the generation of a preselected combination of coded signals which may include means for sequentially generating the plurality of coded signals for operating a controllable device such as an electromagnetic controller or latch associated with a door to allow access to or exit from a controlled area. The signaI-generating means is employed in combination with control means coupled to said generating means for operating the controller and includes circuit means for detecting the coded signals and operating the controller only when a preselected combination of signals are-generated in a preselected sequence and in a preselected time interval. The control means also incorporates circuit means for detecting the generation of a signal other than the signals of the preselected combination or the generation of the preselected signals in other than the preselected sequence to prevent the operation of the controller.

The circuit means for the sequential order detection system may include conventional bistable memory elements connected to be switchably responsive to selected ones of the pushbuttons or switching devices for signaling the operation thereof and providing the required output indications to logical circuit means for detecting the correct sequential generation of the signals and signaling the correct or the erroneous sequential operation. The logical circuit means is further defined to provide an output indication for actuating an alarm in response to the generation of a wrong signal or the generation of the correct group of signals in the wrong sequence or not within the required time interval. In addition to the generation of the correct signals within-the correct timing interval, the logical circuit means of the present invention includes a further timing circuit for ascertaining that only the correct combination of signals are generated and that no error or wrong signal is generated subsequent thereto. In the event a correct combination of signals do not persist for a predetermined time interval without the generation of a wrong signal, the controller will not be actuated as this is indicative of an unauthorized manipulation of the pushbuttons or signal generator and access should not be gained to the controlled area.

These and other features of the present invention may be more fully appreciated when considered inthe light of the following specification and drawings, in which:

FIG. 1 is a block diagram of the general organization of the security system embodying the present invention;

FIG. 2 is a schematic circuit diagram of the security system of FIG. 1;

FIG. 3 is a schematic diagram of one of the time delay elements employed in the embodiments of FIGS. 1 and2;

FIG. 4 is a schematic diagram of another one of the time delay elements employed in the embodiment of FlGS. l and 2;

FIG. 5 is a block diagram of another embodiment of' a security system of the present invention; and

FIG. 6 is a schematic circuit diagram of the system of FIG. 5.

Now referring to the drawings the detailed examination of the circuit organization of the present invention will be explained. It should be recognized at the outset that the invention may be embodied in terms of a signal generator for generating the selected combination of coded signals either through the use of pushbuttons, electrical switches and the like or through an electrical key or combinations of such signal generating means. The present invention is particularly adapted to employ an electrical key of the type disclosed in the Hedin et al. US. Pat. No. 3,392,558. To facilitate the description, however, the invention will be initially examined as it is implemented through the generation of a coded group of signals through pushbutton operation alone.

The pushbutton station 10 is illustrated in FIG. 1 as it may be mounted on a wall 11 adjacent to a door having an electromechanical controller 12 for controlling the operation of the door and gaining access to or exit from a controlled area. The pushbutton station 10 may include a receptacle for receiving the key of the type disclosed in the aforementioned U.S. Pat. for also operating the system. The key receptacle is further identified by the reference numeral 10K. For such a system, then, a mode selection switch 13 is provided for manually selecting by means of a three-way switch the mode of operation of the system as is illustrated in FIG. 1. The three positions are identified as pushbutton only, key only and pushbutton and key. For the present it will be assumed that the mode selector switch 13 is arranged in the PB only position, as illustrated, and therefore only the operation of the pushbuttons at the station 10 will be effective on the control apparatus.

The pushbutton station 10 is illustrated with a plurality of pushbuttons that may be momentarily actuated for generating the coded electrical signals representative of decimal digits. Accordingly, the pushbutton station 10 may have 10 pushbuttons that are identified by the individual decimal digits -9 and each have an individual output wire connectable to a patch panel 14. The wires from the pushbutton station are cabled and pass from the outside surface of the wall 11 into the controlled area and are connected to the appropriate conductive sockets on the patch panel 14 in the usual fashion. The patch panel 14 is defined with a series of conductive sockets arranged on the right-hand side of the panel 14, as illustrated, for defining the sequence sockets and the error sockets. For this purpose, it will be assumed that the system is operative in response to four coded signals and accordingly the top four sockets are utilized for defining the correct combination of signals and their sequential relationship for operating the controller 12. These four sockets are further identified in FIG. 1 as the sequence sockets. The remaining sockets that are arranged in the right-hand side of the patch panel 14 as illustrated in FIG. 1 as the sockets in the left-hand side of the panel are further identified as the error sockets" for signaling the generation of a signal other than a signal within the preselected combination of controller operating signals. It will be understood that the appropriate connections to the patch panel 14 for powering the system and the mode selector switch 13 is by means of a power supply, generally identified by the block 15. To detect the correct generation of the preselected combination of signals, the sequence order detect and memory element 16 is coupled to be responsive to the signals derived from the sequence sockets of the patch panel 14. The detecting element 16 provides an output signal to the controller-actuating circuit 17 for operating the controller 12 in response to the generation and detection of the correct combination of signals. In the event that the correct combination of signals are generated in the wrong sequence an error output indication is provided to an error detection circuit 18 coupled to be responsive thereto. The patch panel 14 has its error sockets" coupled to a wrong signal detect element 19 which is responsive to the generation of a signal not included within the preselected combination of signals for operating the controller 12. The wrong signal detect element 19 provides a wrong signal output indication to the error detect element 18. The error detect element 18 will provide a signal to an alarm unit 20 for actuating the alarm indicative of the detection of an error in response to the output signals from the elements 16 and 19.

The system of FIG. 1 further includes a time delay element 21 which is further identified as a penalty delay. This element 21 is coupled to receive the output indications from the error detect element 18 and the signal from the sequential order detect and memory element 16 that is representative of the fact that the first digit of the preselected combination has been generated and received. The time delay element 21 is, then, activated or triggered in response to this first signal and is maintained in an active condition for a preselected time interval that is defined to allow the operator to generate the remaining signals of the preselected combination for correctly operating the controller 12. In the event that the signals are not all generated within the selected time interval for the time delay element 21, the element 21 will provide an output signal to the sequential order and detect memory 16 for resetting the memory element and thereby render all of the signals previously generated ineffective for operating the system. Even in the event that an authorized individual is operating the pushbutton station 10 but neglects to operate it within a preselected interval, the system will not provide an actuating or unlocking signal to the controller 12. A further time delay element which is identified in the drawings as an antimanipulation hold" associated with the controller-actuating circuit 17 is provided. This time delay circuit 17 further assures that there is not an accidental or fortuitous selection of the correct combination of signals by the provision of a further time delay for detecting whether or not any wrong or error signals are generated subsequent to the generation of the correct combination of signals in the correct sequence and within the time delay governed by the time delay element 21. It will, of course, be recognized that in the event that an unauthorized individual generates the correct combination of signals without appreciating that it is a correct combination and continues to operate the pushbuttons this indication will be sensed by the antimanipulation hold circuit and will prevent the controlleractuating circuit for providing the signal for operating the controller 12.

In addition to the sequence sockets, further sockets of the patch panel 14 may be utilized for implementation of the ambush alarm feature of the present invention. In this instance, an additional socket is utilized in combination with the sequence sockets so that an authorized individual that is being forced to operate the system because of his knowledge of the combination can operate the same number of pushbuttons (four) as he would under normal circumstances but changes one of the coded signals of the combination whereby the system is still rendered operative and yet an alarm signal is coupled to the alarm 20. This circuit organization will be described in more detail hereinafter. At this point, it should be noted that the last signal, for example, of the preselected combination of operating signals may be omitted and a fifth signal coupled so as to generate not only the ambush alarm signal but also to effectively couple the omitted signal to the detect element 16 so that it will operate in the normal fashion.

Now referring to FIG. 2, the detailed circuit implementation of the system of FIG. 1 will be described. The pushbutton station 10 is illustrated in FIG. 2 as comprising 10 pushbuttons each individually identified by one of the decimal digits 0-9. Each of the pushbuttons 0-9 is illustrated as comprising a single pole, normally open, pushbutton which momentarily makes electrical contact upon operation of same. One terminal of each pushbutton switch 0-9 is connected in common to the source of power illustrated as a negative terminal 30. The remaining terminals of the pushbuttons 0-9 are connected to individual conductive sockets, which sockets are generally identified by the reference numerals 31. In the same fashion, the negative terminal 30 is connected to a socket 31.

It will be noted from examining FIG. 2 that the patch panel 14 comprises two columns of conductive sockets identified as the A and B columns. The A and B columns are further identified by the decimal digits 0-9 for the sockets in the two columns that identify the same decimal digit. The negative terminal 30 may be considered a common or ground terminal and as such is connected to the topmost socket of the patch panel 14 arranged in the B column, socket B-l. This, then, causes this uppermost socket or the B-1 socket, as identified in the drawing, to be the ground terminal for the patch panel 14. The positive terminal of the patch panel 14 then, is the B-2 socket and this socket is connected directly to the power supply 15 as illustrated. The B-2 terminal is also connected to a socket 31 which is in turn connected to a positive terminal 34. In the event that the system is to be powered from an external battery rather than the power supply 15, the terminals and 34 are defined for accepting such a battery and are operative through the aforementioned connections to the patch panel 14. The power supply 33 is more or less of conventional construction and includes an AC to DC converter for powering the patch panel 14. In the particular embodiment illustrated in FIG. 2, the power supply 15 is illustrated as having a positive terminal 35 affording a plus 5 volt potential and a terminal 36 identified as a plus 8-volt terminal. The common or ground terminal from the power supply is identified by the reference numeral 37.

The patch panel 14 is also connected with the mode selector switch 13 for controlling the three modes of operation as described hereinabove. For this purpose the socket identified as the B-3 socket is connected by means of the lead wire (not shown) to the pushbutton terminal of the switch 13 identified as the PB terminal. In the same fashion, the socket identified as the B-4 socket is connected by means of a lead wire (not shown) to the switch terminal identified by the reference numeral 40. The PB terminal is connected to the power supply terminal 36 and is associated along with the other two terminals, identified as the key terminal and the PB and key terminal, with the left-hand switch arm 41 of the mode selecting switch 13. The mode selecting switch 13 includes another movable arm 42 ganged with and illustrated to the right of the arm 41 to be switchable between the terminals 40, 43 and 44. The terminal 44 is connected to the sequential order detect memory element 16 by means of the terminal further identified as the E terminal. In the same fashion the movable arm 42 is connected to the terminal of the sequential order detect memory element 16 identified as the F terminal.

It will be assumed that the preselected combination of decimal digits for operating the system is the digits l-3*25 and that they must be sequentially generated, reading left to right. Accordingly, the conductive socket 31 for the pushbutton for the decimal digit 1 is coupled by means of a patch cord into the conductive socket identified as the A-l socket. In the same fashion the socket 31 for the decimal digit 3 is connected into the A-2 socket, the decimal digit 2 is connected into the A-3 socket and the decimal digit 5 into the A4 socket. The

A-1 A4 so c kets ar e the sequence sockets and accordingly g are conductively connected to the sequential order detect and memory element 16 illustrated as the four bistable elements or flip-flops 45, 46, 47 and 48. The flip-flops 45-48 are of conventional construction and each has a pair of input terminals identified as the set and reset" terminals and a pair of output terminals identified as the l and 0 output terminals. The flip-flops 45-48 are normally arranged so that the 0 output terminals are in the TRUE state and the 1 output terminals are in the FALSE state. The coupling of a signal to the set or S input terminal of an element is effective to switch the state of the element and render the 1 output terminal TRUE and at the same time render the 0 output FALSE, The signal applied to the reset or R input terminal will switch the bistable element back into its initial condition. In order to detect the correct order of operation of the pushbuttons the sequential sockets A-1 through A4 are connected to the set terminals of the elements 45-48 respectively. It should be noted that the terminal A-l is connected to the set terminal for the element 45 through the terminals E and F which are in turn associated with the switch terminal 44 and the arm 42 for the mode selector switch 13 as described hereinabove. Accordingly, the elements 45-48 must be switched in the same sequence as the preselected combination of signals are generated, namely, reading from top to bottom in sequential order as the signals for the decimal digits 1, 3, 2 and 5 are generated.

It will also be noted that the sockets B-S, B-6, B-7, 3-8, B-9 and B-0 and sockets A-0, A-9, A-8, A-7 and A-6 are connected to the wrong signal detect element 19 illustrated as a conventional multiinput OR gate. The OR-gate 19, then, provides an output signal in the event any pushbutton other than the pushbutton for the decimal digits 1, 3, 2 and 5 are operated for signaling a wrong signal in response thereto. The bistable elements 4548 are connected with the logical circuit arrangement for detecting the sequential order of operation or switching thereof. The logical circuits are illustrated as three two-input AND-gates 50, 51 and 52. The AND-gate50 has one of its input circuits connected to the 0 output circuit for the bistable element 45 with the other input connected to the 1 output circuit for the element 46. In the same fashion, the AND-gate 51 is connected with the 0 output circuit of the bistable element 46 and the 1 output circuit for the bistable element 47. The AND-gate 52 is connected with the 0 output terminal for the bistable element 47 and the I output terminal for the bistable element 48. The output circuits for the AND- gates 50, 51 and 52 are connected in common with the output circuit for the OR-gate 19 to the set input terminal for the error detect bistable element 18. The 1 output circuits for each of the bistable elements 45-48 are also connected as input signals to the AND-gate 53 associated with the controller actuating circuit 17. At this point it should be noted that the 1 output circuit for the bistable element 45 is connected to a capacitor 54 having one terminal connected directly to ground. The function of the capacitor 54 will be described more fully hereinafter.

The error detect element 18 is a conventional bistable element or flip-flop and has its 1 output circuit connected as an input signal for an OR-circuit 55. The output of the ORcircuit 55 is connected to actuate the alarm 20. The 0 output circuit for the element 18 is connected as one input to an AND-gate 56 and as the remaining input to the AND-gate 53 by means of the lead wire 57. The remaining input for the AND-gate 56 is derived from the 0 output of the bistable element 45. The output circuit from the AND-gate 56 is connected to a time delay element 58 which may be a conventional one-shot multivibrator circuit. The output circuit of the time delay element 58 is connected to the reset terminal of the bistable element 18 by means of the lead wire 59 and also to the reset terminals for each of the bistable elements 45-48 by means of the lead wire 59A. The signal from the element 58 is effective to reset each of the bistable elements 45-48 and 18 to, their initial state in response to a signal from the time delay element 58. It will also be noted that the terminal A-S for the patch panel 14 is connected by means of the lead wire 60 to an inverter 61 having its output circuit connected as an input to the OR-gate 55 for actuating the element 20. The socket A-5 is also connected by means of a diode 62 to the set terminal for the bistable element 48 in common with the connection to the socket A-4. The socket A-5, which is further identified as the S socket, is utilized for implementing. the ambush protection feature, as will be described immediately hereinafter. This S socket will have to be connected to one of the sockets 31 other than the sockets for the preselected combination of digits, in this instance l, 2, 3 and 5, so that when the last decimal digit, in this instance the digit 5, is not operated, the additional pushbutton that is operated will couple a signal to the A-5 or S socket so that the flip-flop 48 will be set along with the remaining elements 4547 in the correct sequence. The circuit connection or patch cord for the S socket to the socket 31 is not illustrated in FIG. 2.

The output circuit for the AND-gate 53 is connected as one input to the AND-circuit 62. The other input to the AND-gate 62 is derived from the connection to the movable arm 41 for the mode-selector switch 13 which is illustrated as connected to the PB terminal thereof. The output of the AND-gate 62 is connected to a further delay element 63 which in turn is coupled to a controller driver circuit 64 for operating the controller 12. The remaining portion of the circuit illustrated in FIG. 2 is utilized for the purpose of key operation or the combination of key and pushbutton operation and will not be examined for the present.

With the above structure in mind and assuming that the correct combination of pushbuttons that will operate the controller 12 are the signals that represent the digits l325, and in that order, the operation of the circuit will be examined. Assuming initially that the pushbuttons of station 10 are operated in the sequence 1, 3, 2, and 5, in this instance, then, the bistable elements 45-48 will be sequentially switched to their 1 state and therefore no TRUE output signals will be derived from any of the AND-gates 50, 51 or 52. At this time, then, if no further buttons are operated, no output signal will be derived from the OR-gate 19. Accordingly, the bistable element 18 will remain in its initial state or with its output'in the TRUE state. With the switching of the bistable element 45, the input conditions to the AND-gate 56 have been satisfied and so a signal is coupled to time delay element 58 for rendering it operative. At a predetermined interval later, at which time only the correct pushbuttons have been operated, the time delay element 58 will produce an output signal resetting the bistable elements 45-48. It will also be assumed that no pushbuttons have been operated after the correct pushbuttons have been operated and after the time delay element 58 provides its output signal, the input signals to the AND-gate 53 all are TRUE and accordingly the output signal therefrom is coupled to the AND-gate 62 and from AND-gate 62 to the delay circuit 63. Since no further buttons have been operated at the pushbutton station for the time interval selected for the delay circuit 63, a signal is delivered to the circuit 64 that is effective for operating the controller 12 and a door to the controlled are a will have been unlatched or opened.

Still assuming that the correct combination of signals are those representative of the digits 1, 3, 2 and 5, and that the digits 1, 2, 3 and 5 are sequentially operated, the operation of the circuit can be examined under these operating conditions. Once the signal representing the decimal digit 1 is generated the flip-flop element 45 will be switched so that its 0 output signal will be in a FALSE condition. When the 2 button is pushed, immediately thereafter, the signal generated thereby will cause the flip-flop element 47 to switch state and therefore render its 1 output TRUE and its 0 output FALSE. Since at this interval the 0 'output from the bistable element 46 is in the TRUE state and the 1 output from the bistable element 47 is now also in the TRUE state a signal will be provided at the output circuit of the AND-gate 51 for setting the error detecting element 18. With the setting of the bistable element 18 to the 1 state, a signal is coupled to the OR-gate 55 which in turn actuates the alarm 20. This signals that a wrong button has been operated and that an unauthorized attempt is being made to enter the controlled area. It will be noted that this error detection is effected even though the decimal digit 2 is included among the combination of digits for unlatching the controller 12. It will be recalled that the sequence of operation of the pushbuttons is that the 3 signal must be generated before the 2 signal and in the illustration of the operation of the system the 2 was generated before the 3. In the same fashion in the event that a pushbutton is pressed other than the buttons 1, 3, 2 and 5, the OR-circuit 19 will signal the operation of any such button and provide a set signal to the bistable element 18 for actuating the alarm 20.

An important aspect of the invention is the ambush protection feature. In accordance with the present invention, in the event an authorized individual is forced to unlatch the controller 12, this may be accomplished through the operation of only four pushbuttons but without the unauthorized individual realizing that he has not utilized the correct code but one that will unlatch the controller 12 and provide an alarm signal. This may be accomplished, for example, instead of employing the combination 1, 3, 2 and 5, the individual may use the combination l, 3, 2 and 6. It will be assumed that for this type of operation a patch cord will have been connected from the socket 31 for the pushbutton 6 to the S socket for the patch panel 14. Accordingly, with the sequential operation of the buttons 1, 3, 2 and 6, the flip-flops 45-48 will switch in sequence, as described hereinabove. With the operation of the decimal digit 6 pushbutton, it will be seen that the two sockets A-4 and A-5 are connected in parallel circuit relationship to the set input of the flip-flop 48 and therefore the system will operate in the same fashion as if the decimal digit 5 had been generated. At this same time, however, and by means of the lead wire 60, a signal is coupled to the inverter 61 and it in turn to the OR-gate 55 for actuating the alarm 20.

Another important feature of the present invention that is to be examined is the antimanipulation hold in the event a wrong pushbutton is pushed along with the correct combination. This feature is provided by the time delay circuit 63 which requires and assures that the signals from the bistable element 4548 and 18 persist at the AND-gate 53 for a preselected time interval. If no buttons are pressed, after the correct combination is operated, all of the logical conditions for the AND-circuits 53 and 62 will be satisfied so that the delay circuit 63 and the driver circuit 64 are effective for unlatching the controller 12. In the event that after the correct four buttons are operated in the correct sequence a further button is operated, for example, the button 7, a signal will be provided from the OR-gate 19 in response to the operation of the 7 pushbutton, to reset the element 18. The resetting of the bistable element 18 will cause its 0 output circuit to go FALSE and couple a FALSE signal by means of the lead wire 57 to the AND-gate 53. If this occurs during the delay interval selected for the circuit 63, then, at the end of the delay period the output circuit of the AND-gate 53 will not be TRUE and therefore the driver circuit 64 will not unlatch the controller 12. At this same time the alarm circuit 20 will be operated as the result of the TRUE signal from the 1 output of the bistable element 18 coupled by means of the OR-gate 55.

A further antimanipulation aspect of the present invention is the possibility that an unauthorized individual may operate four buttons simultaneously and the four buttons represent the correct combination of signals for unlatching the door or operating the controller 12. Since it now should be appreciated that the elements 4548 must be sequentially switched, if, for example the elements 45 and 46 are provided setting signals at the same time, the capacitor 54 connected to the 1 output of the element 45 introduces a time delay into the switching of the element 45. When a signal is received at the set input of the element 45 at the same time as one is received at the element 46, the element 45 will not switch until after the capacitor 54 has charged up. This charging time introduces the time delay which allows the element 46 to switch before the element 45 and produce a signal from the AND-circuit 50 that an incorrect sequence of operation of the buttons has occurred. This, of course, can be avoided in normal operation since the buttons are not to be operated together but in sequential fashion and therefore the time delay afforded by the capacitor 54 will not be effective.

As mentioned hereinabove, the invention is also operable to operate the controller 12 through the combination of the pushbutton station 10 and an electrical key. In order to place the control apparatus in condition for operation by the pushbutton station 10 and an electrical key, the mode selector switch 13 must be rotated from the pushbutton position to the pushbutton and key position. When operating in this mode an electrical key will provide one of the input signals normally provided by the pushbutton station 10. A correctly coded key in combination with the operation of the correct three push buttons in the correct sequence will provide the necessary actuating signals to the controller 12. The key that may be employed with the present invention is an electrical key of the type described in the aforementioned Hedin et al. U.S. Pat. No. 3,392,558. This patent further discloses the circuitry for comparing the recorded electrical information on the key to determine whether a good or a bad" key has been employed. A more detailed description of the key and the circuits for recognizing a good and bad key may be had by reference to the disclosure of the Hedin et al. patent.

Briefly, the electrical key is constructed on an insulative substrate 71 and has a preselected conductive pattern deposited thereon. In the illustration of the key 70 of F [6. 2, a

plurality of conductive segments such as the segments 72 and 73 are arranged in an insulative spaced apart relationship adjacent one edge of the substrate 71 and all of the segments are in turn conductively connected to a common conductive segment 74 arranged adjacent the opposite edge of the substrate 71. For example, the conductive segment 75 is shown with an open circuit condition intermediate the ends of the segment. This structure is characteristic of other open circuited segments that may be required in accordance with the selection of a particular circuit pattern for defining the coding of the key 70. The key 70, then, is defined with a preselected circuit pattern comprising conductive segments and open circuit segments. The arrangement of the open and closed circuit patterns define a particular pattern individual to the key.

The key is employed with a key receptacle K providing a plurality of electrically isolated conductive segments, such as the segments 76 and 77. The segments 76 and 77 are arranged in a spaced-apart relationship similar to the spacing for the circuit pattern on the key 70 so that when the key 70 is inserted into the key receptacle 10K, the conductive segments 72, 73, etc. for the key 70 overlie in conductive relationship the conductive segments 76 and 77, etc. of the receptacle 10K. The interengagement of the key 70 and receptacle 10K in this fashion provides a circuit path through the conductive pattern of the key in accordance with the closed circuit pattern selected for the key. For this purpose, the key receptacle 10K is connected to a power source through one of the conductive segments recorded thereon. In FIG. 2, the segment 76 is illustrated connected to the negative or common terminal 30 and in parallel with the ground socket 3-1 for the patch panel 14. The remaining segments of the key receptacle 10K are connected to an individual conductive socket such as the socket 770 for the segment 77. The socket 77a and the remaining sockets associated with the remaining conductive segments for the key receptacle 10K are adapted for accepting a patch cord of the type employed with the patch panel 14. It should now be apparent that with the power applied tothe segment 76 and with the key segment 72 overlying the segment 76 that a conductive circuit path will be provided from the power source through the segment 76, the segment 72 to all of the closed circuit segments on the key 70 such as the segment 73 on the key 70 for providing corresponding output signals at the receptacle 10K. For example, the signal provided b the conductive segment 73 for the key 70 will appear at socket 77a at the receptacle 10K. In the same fashion, all other conductive segments will provide an output signal from the corresponding terminal of the receptacle 10K, while the open circuited segments on the key 70 will not provide an output signal.

To combine the key control of the key 70 along with the pushbutton 10 requires that the socket 77a be connected by means of a patch cord to the socket 8-3. In addition, the segment 78 and its respective socket 78-A is coupled by means of a patch cord to the socket B4 for the patch panel 14. The remaining segments for the key receptacle 10K have their respective sockets connected as input signals to the key recognition circuitry 80. As disclosed in the aforementioned Hedin et al. patent, this circuitry compares the pattern of electrical signals derived from the key receptacle 10K and which combination of signals is representative of the circuit pattern on the key 70 to determine whether it matches the desired circuit pattern for providing an actuating signal for the controller. If such a pattern is present on the key 70, a matching output signal is provided at the output lead wire 81 for the key recognition circuitry 80. This output signal is coupled by means of the output lead wire 81 as an input signal to the AND-gate 62. With the mode selection switch 13 in the pushbutton and key mode, when the correct key 70 is in engagement with the key receptacle 10K, the connection of sockets 78a and B4 is coupled by means of a lead wire (not shown) to the mode-selector switch terminal 40, through the movable arm 42 to socket F coupled to the set" input for operating the bistable element 45.

In the operation of the circuit, then, in the combined pushbutton and key mode it is only necessary that first a key that is a proper key be inserted into a receptacle 10K. The proper key 70 must have a conductive segment74 deposited thereon for providing a signal to the socket B4. If this is done, the bistable element 45 will signal that there is a correct key and it will switch its state. Subsequent thereto, the three selected decimal digits for operating the controller 12 are operated in sequential relationship within the constrains mentioned hereinabove for the full pushbutton operation and the circuit will respond in the same fashion as described hereinabove. Of course, if the wrong key is employed, the bistable element 45 will not switch its state and despite the fact that the correct pushbuttons are later depressed, an error signal will be generated.

As is now evident, the circuit will also operate without the pushbuttons and for this purpose a key may be solely employed for operating the controller 12. In this mode, the mode selection switch 13 is positioned in the key position. This eliminates the need for the sequential order detect memory element 16 and wrong signal detect circuit 19 associated with the pushbuttons. The recognition of the correct key is by means of the key recognition circuitry as mentioned hereinabove. For this purpose, the output signal on the lead wire 81 is applied to the AND-gate 63 for signalling the matching condition. With the switch 13 in the key mode it will be noted that one of the inputs to the AND-gate 62 is connected from the power supply terminal 36 through a dropping resistor to the socket B3. The socket end of the resistor 90 is also connected to an inverter circuit 91. and its output terminal is connected to the key contact 92 for the mode selector switch 13. Under these conditions, then, with no key positioned in the receptacle 10K the input to the inverter 91 is a high positive potential whereby a FALSE output signal is coupled to the AND-gate 62 by means of the arm 41 and thereby inhibits the operation of the controller 12. When the key 70 is correctly in position in the receptacle 10K the input to the inverter 91 is at ground potential as a result of the circuit path through the socket B3, the socket 770, the segment 77, the

segments 73 and 72 on the key 70 and the segment 76 on the.

receptacle 10K to ground potential provided by the socket A-l. Accordingly, when the input circuit to the inverter 91 is in a low voltage, its output circuit is in a TRUE condition and the signal applied by means of the arm 41 to the AND-gate 62 is in the TRUE condition to enable the gate 62. Accordingly, an output will be provided from the AND-gate 62 whenever the key recognition circuitry 80 provides a matching signal-to the AND-gate 62. The operation of the delay circuit 63 and the driver circuit 64 for operating the controller is then identical to that disclosed hereinabove.

Referring now to FIG. 3, there is shown a typical embodiment of time delay circuit 58. This circuit includes a bipolar transistor 125, the base of which is connected to the output line from AND-gate 56 (FIG. 2). The emitter of transistor is grounded, and the collector thereof is connected via resistor 126 to the gate of a unijunction transistor 127. The emitter of transistor 127 also is connected to ground via a capacitor 128, and to.+8-volt terminal 36 via a potentiometer 129.

The base 2 of transistor 127 is connected directly to terminal 36 and to the contact arm of potentiometer 129. The base 1 of transistor 127 is connected to ground via a resistor 130 and to the base of another bipolar transistor 131 via a resistor 132. The emitter of transistor 131 is grounded, and the collector is connected directly to reset line 67 and via a resistor 133 to +5-volt terminal 35.

In operation, when the output signal from AND-circuit 56 is true, transistor 125 is on and a current path is provided from terminal 36 via potentiometer 129 and resistor 126 to ground. The value of resistor 126 is appropriately chosen so as to hold the voltage on the gate of transistor 127 below the level required to turn that transistor on. Accordingly, the base 1 of transistor 127 and hence the base of transistor 131 are substantially at ground potential and transistor 131 is off. The collector of transistor 131 thus is set at approximately the .+5-volt level provided from terminal 42', and a corresponding positive signal appears on reset line 67. This positive voltage does not reset the flip-flops connected to line 59.

When the signal from AND-gate 56 goes false, transistor 125 is turned off, permitting capacitor 128 to charge via potentiometer 129. After a time delay determined by the RC time constant of potentiometer 129 and capacitor 128, the voltage at the emitter of transistor 127 goes sufficiently positive so as to turn transistor 127 on. This drives the base of transistor 131 positive, causing transistor 131 to conduct, thereby clamping reset line 59 to ground and providing a pulse which resets flip-flops 45, 46, 47, 48 and 18.

Note that the time delay in the circuit of FIG. 3 is introduced by capacitor 128 and potentiometer 129. Preferably, this time delay is adjusted (by appropriately setting potentiometer 129) to be somewhat longer than the average time taken to depress sequentially the four pushbuttons associated with sockets A-l through A-4.

A typical embodiment of delay circuit 63 and driver circuit 64 is shown in FIG. 4. Referring thereto, delay circuit 63 comprises a bipolar transistor 140 the base of which is connected to AND-circuit 62. The base of transistor 140 also is connected to ground via a capacitor 141 and to +5-volt terminal 42" via a resistor 142. The collector of transistor 140 is connected directly to terminal 42" and the emitter of transistor 140 is connected via a resistor 143 to the control electrode of a silicon-controlled rectifier (SCR) 144 in driver circuit 64. The control electrode of SCR 144 also is connected to ground via a resistor 145.

The cathode of SCR 144 is grounded, and the anode of SCR 144 is connected via line 22 to the coil 146 of an electromechanical device such as door latch 23. The other terminal of coil 146 is connected via a line 147 to a junction of the diode-rectifying network of a power supply 15, identified as X. A suppressor diode 148 is connected across coil 146.

Operation of the circuit of FIG. 4 now should be apparent. When AND-gate 62 provides a FALSE output, the input line to transistor 140 is substantially at ground potential, and transistor 140 is off. As a result, its output line is also at ground potential and SCR 144 is not conducting. When the output of AND-gate 62 goes TRUE, the input line to transistor 140 is unclamped from ground and capacitor 141 begins to charge via resistor 142. After a period of time determined by the RC time constant of capacitor 141 and resistor 142, the voltage level at the base of transistor 140 is sufficiently high to turn this transistor on. As a result, current flows in a path including terminal 35, transistor 140, resistors 143 and 145 and ground. As a result, the voltage level on the output of transistor 140 goes sufficiently positive to initiate conduction of SCR 144, thereby causing current to flow from junction X through coil 146 and SCR 144 to ground. This actuates the door latch 23 associated with coil 146.

Note that an AC voltage is supplied at junction X; this voltage effectively is rectified by SCR 144 to provide unfiltered DC through coil 146. As long as the signal on line 75 is TRUE, the voltage on line 77 will remain positive, and SCR 144 will remain on during alternate halves of the AC cycle.

At the end of the time delay provided by circuit 58, flip-flop 18 is reset to the state, AND-gate 53 is disabled, and the output from AND-gate 62 goes FALSE. At this time, the base of transistor 140 becomes clamped to ground, causing its output line to go to ground potential and removing the control signal from SCR 144. On the next half-cycle of the AC, SCR 144 will turn off, ten'ninating the latch-actuation signal.

A different embodiment of control circuitry 15 is shown in FIGS. and 6. Referring first to FIG. 5, pushbuttons 12 provide the inputs to a set of active memory elements 150, which in a preferred embodiment comprise silicon-controlled rectifiers. If an appropriate subset of pushbuttons 12 are depressed in the correct order, memory elements 150 will provide simultaneous inputs to an AND-gate 151, thereby producing asignal on a line 152 to a driver circuit 153. Unless inhibited as described below, driver circuit 153 in turn will provide a latch actuation signal along a line 22' to operate a utilization device such as a door latch 23'.

If any of the subset of pushbuttons 12 associated with active memory are depressed out of order, an input will be provided to an OR-gate 154. The output of OR-gate 154 in turn will be supplied via a line 155 to operate an inhibit circuit 156 which prevents operation of driver 153. Thus, if the cor rect subset of pushbuttons 12' is depressed, but in the wrong order, driver 153 will not provide a signal to operate door latch 23'. The output of OR-gate 154 also is provided to an alarm 157 which indicates that an erroneous attempt has been made to operate the lock.

If others of pushbuttons 12' not associated with memory elements 150 are depressed, a signal also will be produced on line 155 so as to operate inhibit circuit 156 and prevent driver 153 from activating door latch 23'. Such a signal on line 155 also will energize alarm 157.

The control circuitry of FIG. 5 also may utilize a key in place of or in addition to pushbuttons 12'.

A typical embodiment of the control circuitry of FIG. 5 is shown schematically in FIG. 6. Referring thereto, it may be seen that pushbuttons 12' comprise a plurality of normally open, momentary switches 161a, 161b...16ln, each having one contact connected to a common line 162. Common line 162 is connected via a resistor 163, a line 164 and a switch 165 to a source of positive voltage 166.

Each of pushbutton switches 161a through 161d is connected via a respective resistor 167 through 170 to the control electrode of a respective silicon-controlled rectifier (SCR) 171 through 174. The anode of each of SCRs 171 through 174 is connected directly to ground, while the control electrode of each SCR is connected to ground via a respective one of resistors 175 through 178. Voltage line 164 is connected to the cathodes of each of SCRs 171 through 174 via a respective one of resistors 181 through 184. SCRs 171 through 174 together with their associated resistors thus comprise active memory elements 150.

Still referring to FIG. 6, AND-gate 151 is'seen to comprise four resistors 185 through 188 having a common connection to the anode of a diode 190. Resistors 185 through 188 also are connected respectively to the cathodes of SCRs 171 through 174. The cathode of diode 190 is connected directly to the base of a bipolar transistor 191, and via a resistor 192 to ground. The emitter of transistor 191 is grounded, and the collector thereof is connected via line 152 to driver 153, and via a resistor 193 to positive voltage line 164.

Driver 153 itself comprises a unijunction transistor 195 the emitter of which is connected directly to line 152 and via a capacitor 196 to ground. The base 2 of transistor 195 is connected via line 157 to inhibit circuit 156, and also is connected via a resistor 197 to voltage line 164. The base 1 of transistor 195 is connected directly to the control electrode of a siliconcontrolled rectifier 198, and via a resistor 199 to ground. The cathode of SCR 198 is grounded, and the anode is connected to coil 201 of door latch 23'. The other end of coil 201 is connected to voltage line 164.

Inhibit circuit 156 itself comprises a silicon-controlled rectifier (SCR) 202 having a grounded cathode and an anode which is directly connected to line 157. The control electrode of SCR 202 is connected via a resistor 203 to line 155, and via a resistor 204 to ground.

The signal on line 155 is supplied from OR-gate 154 which in the embodiment of FIG. 6 comprises diodes 205, 206 and 207 the cathodes of which are connected to line 155. The anodes of diodes 205 through 207 are connected directly to the collectors of respective transistors 208 through 210, and via resistors 211 through 213 to the anodes of respective SCRs 171 through 173. The emitters of each of transistors 208 through 210 are grounded, and the bases thereof are connected via respective resistors 214 through 216 to the anodes of respective SCRs 172 through 174.

Still referring to FIG. 6, alarm circuit 157 comprises a silicon-controlled rectifier 220 the cathode of which is grounded and the control electrode of which is connected to line 155 via a resistor 221, and to ground via a resistor 222. The anode of SCR 220 is connected to a coil 224, the other end of which is connected to voltage line 164. Coil 224 may comprise the coil of an alarm bell, a relay adapted to provide a remote alarm signal, or thelike.

Operation of the circuitry of FIG. 6 now will be described. With all of pushbuttons 12' open, the control electrodes of SCR 171 through 174 are held substantially at ground potential via respective resistors 175 through 178. Accordingly, SCR's I71 through 174 are not conducting, and a positive voltage is supplied via resistors 185 through 188 and diode 190 to bias transistor 191 on. As a result, the gate of transistor 195 is grounded via transistor 191, transistor 195 is off, and the control electrodeof SCR 198 is held at ground potential. This prevents SCR 198 from conducting.

When all of switches 161a through 161d are closed in the correct order, each of SCRs 171 through 174 goes into conduction, and the voltage at the inputs to all of resistors 185 through 188 drops to ground. As a result, transistor 191 goes off, and capacitor 196 begins to charge via resistor 193. After a period of time determined by the RC time constant of resistor 193 and capacitor 196, the voltage level at the emitter of unijunction transistor 195 is sufficiently high so as to cause conduction of unijunction transistor 195. Accordingly, unless inhibited by circuit 156, the voltage level at base 1 of unijunction transistor 195 goes sufficiently positive to turn on SCR 198. When this happens, current flows through coil 201, actuating door latch 23.

Actuation of door latch 23' is prevented by inhibit circuit 156 if any of switches 161a through 161d are depressed out of order, or if any other of pushbuttons 12' also are depressed. This inhibit operation will now be described.

Transistors 208 through 210 and OR-gate 154 cooperate to insure that door latch 23' is actuated only when switches 161a through 161d are depressed in a corresponding, sequential order. Initially, with all of switches 16111 through 161d open, a positive voltage is supplied via respective resistors 214 through 216 to the bases of transistors 208 through 210, turning these transistors on. As a result, the anodes of diodes 205 through 207 all initially are at ground potential and no inhibit signal appears on line 155. If, as required to operate the lock, switch 161a is closed before switch 161b, SCR 171 will go on before SCR 172 goes on. The anode of diode 205 then will be clamped to ground (via resistor 211 and SCR 171) before transistor 208 goes off as a result of conduction of SCR 172. Accordingly, the output of diode 205, will remain at ground potential, and no inhibit signal will be supplied on line 155.

On the other hand, suppose that switch 161b is closed before switch 161a. As soon as switch 16112 is closed, SCR 172 will begin to conduct, the voltage level at the base of transistor 208 will drop to ground, and transistor 208 will turn off. Since switch 16lais still open, a positive voltage will be supplied via resistor 211 to diode 205. This positive voltage will be conducted through diode 205 to provide an inhibit signal on line 155. This positive signal on line 155 will turn on SCR 202 so as to inhibit operationof driver 153.

When SCR 202 goes into conduction, current flows through resistor 197 and SCR 202, clamping the base 2 of unijunction transistor 195 to ground. Accordingly, even though unijunction transistor 195 may be turned on by occurrence of a signal on line 152, the base 1 of transistor 195 will remain at ground potential, SCR 198 will remain ofi', and no current will flow through coil 201; door latch 23' will not be actuated. Moreover, the voltage on line 155 also will be directed via resistor 221 to turn on SCR 220. As a result, current will flow through coil 224 causing an alarm bell or signal to indicate that an erroneous attempt has been made to operate the lock.

Transistor 209 and diode 206 operate in line manner to insure that switch 161k is closed prior to switch 161e, and transistor 210 and diode 207 operate to insure that switch l61c is closed before switch 161d. Thus 0R-gate154 provides a control signal to inhibit circuit 156..whenever any of pushbutton switches 151a through :16ld are depressed out of order.

switch 16ln. This signal on line 155 again causes conduction of SCR 202, thereby preventing driver 156 from energizing.

coil 201 ofdoor latch 23.

Although not specifically illustrated in FIG. 6,-a set of patch plugs and sockets may be usedin conjunction with pushbuttons 12' to allow selection of whichparticular pushbuttons will be operative as in the previous embodiment of theinvention, in conjunction with SCRs 171 through 174,.'to operate 1 the lock. Moreover, any of switches 161a through-161d may be replaced by a circuit which is closed when a key (such-as key 70 of FIG. 2)is inserted in an appropriate receptacle. 1. Further in this regard, the circuitry generallydesignated 2275- in FIG. 6 may be employed to accomplish door latch actuation only when both the correctpushbuttons 12'{ have been depressed and when an appropriate key is inserted -in a key receptacle such as receptacle 10K'of FIG. 2.

Referring to FIG. 6, the block designated 22.7 encompasses circuitry modifications designed to facilitate combined pushbutton and key operation. For suchoperation, resistor l93 is disconnected from line 152 at junction 228.,Further, switch 165 is omitted, the connections thereto beingdirected to a pair of key receptacle contacts 229 and 23,0. Contacts 229 and 230 are associated with the pair of busconnected terminals .72

and 73 of key 70 (see FIG. 2). Further, 'circ'uitry 227 includes a plurality of key receptacle contacts .231 through 234 for, receiving the coded terminals 75, 74 of key 70. Terminals 231 and 232 are connected to line 152 via respective diodes 237,

240 and to ground via respective resistors 235, 236. Terminals 233 and 234 are connected to line 155 via-respective diodes 238, 239 and to ground via respective resistors 241, 242.

In operation, key 70 (FIG. 2) is insertedin the receptacle 1 (not shown) associated with circuitry 227.-,The busconnected terminals 104, of key 70 close the circuit between con tacts 229 and 230, so as to provide a positive voltage on-line 164 for operation of the circuitryof FIG. 6.

When pushbuttons 161a through 161d have been depressed in the proper order, transistor 191 becomes nonconducting as described hereinabove. Now, capacitor 196 is not charged via resistor 193, since that resistor is disconnectedfrom junction- 228. However, if the inserted key 70 includes a busconnected terminal 107 associated with either of contacts 231 or 232, a current path will be providedfrom +V terminal 166 to line 152 via contact 229, bus 103 of key 70, terminal 231 or 232, and diode 237 or 240. Current supplied along this path then will charge capacitor 196, initiating operation of driver l53as described hereinabove.

If the inserted key 70 includes a busconnected terminal 107 associated with either of contacts 233 or 234,'a positive voltage will be supplied to line via such terminal and the associated one of diodes 238 and 239. This positive voltage will cause SCR 202 to turn on; inhibit circuit 156 then will prevent driver 153 from operating door latch 23.

Thus, for combined pushbutton and key operation of the arrangement of FIG. 6, pushbuttons 161a through 161d must be depressed in the appropriate order, and the correct key must be inserted in a receptacle associated with circuitry 227. Specifically, the inserted key must have no. busconnected terminals associated with contacts 233 or 234, and must have at least one bus-connected terminal associated with contact 231 or 232. In such instance, door latch 23 will be actuated. Note that removal of key 70 will electrically disconnect terminal 229 from terminal 230, thereby opening the current through door latch coil 201 and terminating conduction of SCR 198':

What is claimed is:

1. Apparatus for operating a controlled device through the generation of a plurality of coded signals in a preselected sequence comprising means for sequentially generating a plurality of coded signals,

control apparatus connected to be responsive to the coded signals and operative in response to. the sequential generation of a preselected combination of the coded signals,

said control apparatus including alann means connected for providing an alarm in response to a preselected coded signal derived from said generating means,

and means connected to said generating means for coupling the preselected coded signal to said alarm means for operating same and to the control apparatus to cause the operation of the control apparatus in response to the preselected combination of coded signals less one of the coded signals and including said preselected signal.

2. Apparatus for operating a controlled device as defined in claim 1 including triggerable time delay means connected to be responsive to signals from the generating means other than the signals comprising the preselected combination of signals for inhibiting the operation of the control apparatus for a preselected time period in response to at least one of said other signals or the generation of the preselected signals in other than the correct sequence.

3. Apparatus for operating a controlled device as defined in claim 2 including means for coupling the signals for operating the time delay means to said alarm means for operating same in response thereto.

4. Apparatus for operating a controlled device through the generation of a plurality of coded signals comprising means for sequentially generating a plurality of coded signals,

a controllable device,

control means coupled to said generating means for operating said device, said control means including circuit means for detecting the coded signals and operating the device only when a preselected combination of signals are generated in a preselected sequence and in a predetermined time interval,

further circuit means for detecting the generation of a signal other than the signals of the preselected combination or the generation of the preselected signals in other than the preselected sequence to prevent the operation of said device, time delay means connected to be responsive to the generation of the first generated signal from the generating means and operative after a preselected interval to provide a signal to said further circuit means for preventing the operation of the controllable device in response to the first generated signal and the subsequently generated signals after a preselected time interval after the receipt of the first generated signal and further time delay means responsive to the generation of said preselected combination of signals in said preselected sequence for preventing the operation of the controllable device upon the generation of a wrong signal subsequent to the generation of said preselected combination of signals in said preselected sequence.

5. Apparatus for operating a controllable'ldevice comprising means for sequentially generating a plurality of binary coded signals,

a corresponding plurality of bistable elements connected to be responsive to the generation of one of the signals of a preselected combination of signals being switchable in response to the coupling of the individual signal thereto for providing an output indication thereof,

error circuit switching means for detecting the sequence of operation of the bistable elements and switchably responsive thereto for providing an output indication upon the generation of the signals in other than a preselected sequence,

time delay means connected to be responsive to the switchin of the bistable element responsive to the first signal 0 the preselected combination and provldmg a switching signal to each of the elements after a preselected time interval for resetting the states thereof to their initial states and to the error circuit means for resetting same,

a controller,

controller-actuating circuit means coupled to be responsive to the switching of the bistable elements in the correct preselected sequence and within the time interval of the time delay means for operating the controller, said actuating circuit means including a circuit connection to the error circuit means for preventing the actuation of the controller by the actuating circuit in response to a signal derived therefrom, said controller-actuating circuit means including further time delay means for preventing the operation of said controlled device after the generation of said preselected combination of signals in said preselected sequence upon the generation of a wrong signal during a preselected time interval after the correct combination of signals is generated,

and wrong-signal-detecting means coupled to be responsive to the generated signals other than the signals of the preselected combination for providing an output indication in response thereto to said error-switching circuit means. I

6. Apparatus as defined in claim 5, wherein the signalgenerating means comprises independently operable electrical switches for providing electrical signals in response to the operation thereof and includes a plug board connected to the switch and connected to the bistable elements in a predetermined fashion for defining the preselected operable combination of signals and the sequential order required for operating the controller.

7. Apparatus as defined in claim 6 including alarm means connected to be responsive to the output indication from the error circuit means.

8. Apparatus as defined in claim 7 including circuit means connected to be responsive to one of the generated signals other than the signals of the preselected combination for switching the state of one of the bistable elements in the correct sequence for operating the controller and connected for actuating said alarm means.

9. Apparatus as defined in claim 8 wherein the signalgenerating means includes electrical key-operated means for generating the coded signals.

10. Apparatus as defined in claim 9 including mode-selection-switching means for selecting the mode of generating the coded signals either by means of the electrical switches alone, the key means alone or a combination of both the switches and the key means.

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WO1999035621A1 *Dec 30, 1998Jul 15, 1999Grp Des Cartes BancairesMethod and device for processing confidential codes
WO2000054195A1 *Mar 7, 2000Sep 14, 2000Allen I RubensteinDual pin number silent alarm for atm machines
Classifications
U.S. Classification340/5.22, 361/172, 340/5.54, 340/5.6, 340/5.28, 70/278.1
International ClassificationG07C9/00
Cooperative ClassificationG07C9/00039, G07C9/00722, G07C9/00706, G07C9/0069
European ClassificationG07C9/00B6B, G07C9/00E12D, G07C9/00E12G, G07C9/00E12C4