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Publication numberUS3638196 A
Publication typeGrant
Publication dateJan 25, 1972
Filing dateJul 13, 1970
Priority dateJul 14, 1969
Also published asDE2034683A1, DE2034683B2, DE2034683C3
Publication numberUS 3638196 A, US 3638196A, US-A-3638196, US3638196 A, US3638196A
InventorsNishiyama Akira, Yamaguchi Tetsuo, Yoshida Tomio, Yoshino Hirokazu
Original AssigneeMatsushita Electric Ind Co Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Learning machine
US 3638196 A
Abstract
A learning machine in which threshold values corresponding to the desired output conditions and having a dead zone therebetween are used during the learning process for the discrimination of the output from a memory storing a plurality of standard pattern information, and this discriminating faculty is utilized for the discrimination of input pattern information with respect to a single threshold value having no dead zone. Thus, the precision of discrimination can be remarkably improved due to the fact that the threshold values having a dead zone are used during the learning process, and the learning can be digitally and automatically carried out.
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Description  (OCR text may contain errors)

C United States Patent [1 1 3,638,196 Nishiyama et al. 51 Jan. 25, 1972 [54] LEARNING MACHINE 3,293,609 l2/l966 Martin 340 1725 3,311,895 3/1967 Clapper ..340/l72.5 [72] Inventors: Akirn Nlshiyama; Hirokazu Yoshino; 3'309 674 3/1967 Lemay n "340M725 Tomi 'f 'f of Osaka; 3,408.62? 10/1968 Kettleretalv. 340/1725 vflmfluch"HmkaaaMUaPa" 3,446,950 5/1969 King. Jr.et al ..340/172.5 [73] Assignee: Matsushita Electric Industrial Co.. Ltd.,

Osaka Japan Pnmary Examiner-Gareth D. Shaw 7 Assistant Examiner Paul R. Woods i i Flledl 1970 ArmmeyStevens, Davis, Miller& Mosher 57] ABSTRACT A learning machine in which threshold values corresponding 30 F l n A licati Priorlt Data 1 ores pp on y to the desired output conditions and having a dead zone J y I969 J p 44/545642 therehetween are used during the learning process for the dis Ju y 1969 Japan 44/ crimination of the output from a memory storing a plurality of standard pattern information, and this discriminating faculty is l i v l a s a ..34 /l72-5 utilized for the discrimination of input pattern information [5 l] Int. Cl. ,,..G06f15/18 with respect to a single threshold value having no dead zone, [58] Fi l sell h 4 Thus, the precision of discrimination can be remarkably improved due to the fact that the threshold values having a dead [56] References Cited zone are used during the learning process, and the learning can be digitally and automatically carried out UNITED STATES PATENTS 3,267,413 1 8/l966 Greenberg et al ..340/172.5 8 9 Dmmg 3,267,439 8/l966 Bonner 340/1725 4 Wnawr M670? sascmz? a/smeLf 1 7 MUL r/ /5 /6 2 i /7 515mm,? 8 X 0505mm 1 MULT/ 9 W9 CIRCUIT a 7 f 3 L SUM/N6 THRESHOLD BISTABLE W MULT/ CIRCUIT 9; SELECTOR :2: LEARN/N6 55m 1 43 l2 TRIGGER ,5

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INVENTOR ATTORNEY V PATENTEB JANZSIEYZ sum 5 or 7 PATENTEMmsmz mum-1 9/7/nnnn47/ /A PATENTS) M825 m2 FIG 6 LEARNING MACHINE This invention relates to learning machines and more particularly to a learning machine of the kind having such a learning faculty that a set of given input conditions and a set of output conditions given for the input conditions are simultaneously stored in a memory so as to derive any desired output condition therefrom.

Learning machines of this kind are generally provided with an adaptive logic circuit which has such a learning faculty that an output satisfying the desired condition can be obtained for each input condition so that a correct output response can be provided for each input condition after learning. In addition to the above, retraining can be done as required so as to deliver a new output response for a new input condition.

Referring to FIG. 1 showing the basic structure ofa learning machine of this kind, it comprises a plurality of weight elements A, B, C, having respective weight factors W,, W W which may, for example, be a voltage, a summing circuit D, a decision circuit B, an output terminal F, a terminal G to which a desired output is applied, and a learning control cir cuit H. A plurality of input signals X,, X X are applied to the respective weight elements A, B, C, and a threshold value W is applied to the decision circuit E. The inputs X,, X,, X may be one ofa set of l and or one ofa set of+l and -l." The inputs X,, X X are multiplied by the weights W,, W W of the respective weight elements A, B, C, and the products are summed up in the summing circuit D. The sum is compared with the threshold value W; in the decision circuit E, and the output delivered from the decision circuit E is "+1" and 0" respectively when the sum is larger and smaller than the threshold value W; in the embodiment of the present invention described hereinbelow.

In the learning machine having a structure as described above, when the actual output for a certain input condition is +1 and the desired output is "0," the learning control circuit H adjusts the weight factors until they are decreased to give the actual output 0" The above procedure is repeated for all the input patterns each consisting of a set of numerals so that all the input patterns can be classified into two categories consisting ofa class 1 and a class 2.

However, such a system has been defective in that man must participate in the discriminating faculty in the course of learning and thus an extremely extended period of time is required for the learning. Further, due to the fact that the decision circuit E acts as a one-out-of-two decision element during the learning process, there is a problem that correct decision can not be expected during the stage of discrimination when an input pattern differs slightly from a standard pattern.

The present invention contempla es the provision of a learning machine which is free front the above problem by virtue of the fact that it is provided with a memory for storing a plurality of standard patterns and a decision circuit acting as a one'out-of-three decision element during the learning process so as to cooperate with threshold values having a dead zone therebetween.

It is an object of the present invention to provide a learning machine which is provided with a memory and an automatic learning circuit so that a plurality of standard pattern information written previously in the memory can be automatically derived so as to effect discrimination within a short period of time,

Another object of the present invention is to provide a learning machine in which the classification of standard patterns in a decision circuit during the learning process is carried out on the basis of threshold values having a dead zone therebetween and the discrimination is effected on the basis on only one threshold value as heretofore so as to enhance the precision ofdiscrimination.

The above and other objects, features and advantages of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

FlG, l is a block diagram showing the basic structure ofa learning machine;

FIG. 2 is a block diagram showing the structure of an improved learning machine according to the present invention;

FIGS. 3 through 6 and 8 are circuit diagrams showing the detail of parts of the learning machine shown in FIG. 2; and

FIGS. 7a and 7b are charts showing the operation of parts of the structure shown in FIG. 6.

Referring to FIG. 2, a plurality of inputs are applied to respective input terminals 1, 2 and 3 and are held in respective circuits 4, 5 and 6 for any desired period of time. The circuits 4, 5 and 6 may be bistable multivibrators. A plurality of weight factor selective circuits 7, 8 and 9 include weight elements for multiplying the outputs from the bistable multivibrators 4, S and 6 by respective weight factors W,, W, and 1,. Although there are actually n input terminals, n bistable multivibrators and n weight factor selective circuits, only three of them are shown herein for the sake of simplicity. The input signals applied to the input terminals 1, 2 and 3 are either l or "0," and these signals are multiplied by the respective weight factors W W, and W, so that the products appear at the output sides of the respective weight factor selective circuits 7, 8 and 9.

A memory 10 stores successively the outputs from the bistable multivibrators 4, 5 and 6, and at the same time, stores successively expected outputs for standard patterns applied from a terminal 11. A trigger pulse generator 12 controls the writing and reading of input patterns into and out of the memory 10 during the learning process, depending on a signal applied thereto from a manual signal input terminal 13 or an output signal delivered from a learning pulse generator 14 having a function which will be described later.

A summing circuit 15 sums up the weighted values delivered from the weight factor selective circuits 7, 8 and 9, A decision circuit 16 compares the output from the summing circuit 15 with a threshold value We. Thus, an output "+1" appears at an output terminal 17 when the sum is larger than the threshold value W and an output "0" appears at the output terminal 17 when the sum is smaller than the threshold value W A threshold value selection circuit 18 supplies to the decision circuit 16 the threshold value W; corresponding to a desired output which may be H or "0" appearing at an output terminal 101 of the memory 10 during learning, while a threshold value W" applied to the selection circuit 18 from an input terminal thereof is directly supplied to the decision circuit 16 during discrimination.

The learning pulse generator 14 compares the actual output appearing at the terminal 17 during the learning process with the desired output appearing at the output terminal 101 of the memory 10 and sends a series of learning pulses to the weight factor selective circuits 7, 8 and 9 to vary their weight factors only when the actual output does not coincide with the desired output. A weight factor decrement control signal, a weight factor increment control signal and a learning pulse signal appear at respective output terminals 141, 142 and 143 (FIG. 5) of the learning pulse generator 14.

The practical structure of the memory 10, trigger pulse generator 12, learning pulse generator 14, summing circuit 15, decision circuit 16, threshold value selection circuit 18, and weight factor selective circuits 7, 8 and 9 which are the prin cipal components of the learning machine according to the present invention will be described in detail.

The practical structure of the memory 10 is shown in H6. 3. The function of the memory 10 is to store standard patterns and output signals desired for the patterns as described above. In storing the standard patterns and the desired outputs therefor, a switch S, is thrown to the side of the terminals 0 and b to apply a voltage of E volts to the gates of gating transistors 6,, G G and G, so as to urge these transistors to conduct. The desired output supplied from the terminal 1 l is written in a memory means such as a shift register SR, through the transistor 0,, while the components constituting the standard pattern supplied from the bistable multivibrators 4, 5 and 6 are written in memory means such as shift registers SR,, SR, and SR through the transistors 0,, G and 0,,

In reading out the contents written in the shift registers SR,, SR,, SR, and SR,, the switch S, is thrown to the side of the contacts c and d so that the shift registers SR,, SR SR, and SR, are connected in a ring with respective transistors G G G and G On the other hand, the gates of the transistors G,, 6,, G and G are grounded and these transistors are cut off. The contents stored in the shift registers SR,, SR SR, and SR, are read out by the pulse supplied from the trigger pulse generator 12 and are rewritten in the shift registers SR,, SR SR and SR, through the respective transistors 6 G G and G The outputs appearing at terminals 101, I02, 103 and [04 are applied to the learning pulse generator 14 and the threshold value selection circuit 18, and to the bistable mul tivibrators 4, 5 and 6, respectively,

The practical structure of the trigger pulse generator 12 is shown in FIG. 4. A manual signal is applied from the terminal 13 to a pulse generator PG, in the case of the writing of the standard pattern in the memory 10. The pulse generator PG, is thereby energized to generate clock pulses. During the learning process, the output from the learning pulse generator 14 is applied to the pulse generator PG, which therefore generates clock pulses. A bistable multivibrator BS, is provided so as to stop the operation of the learning pulse generator 14 during the transient period of time in which the standard pattern stored in the memory is being read out. More precisely. the state of the bistable multivibrator BS, is inverted by the pulse supplied from the pulse generator PO, to stop the operation of the learning pulse generator 14 and the bistable multivibrator BS, is restored to the original state by a signal applied thereto through a delay means DE, and a monostable multivibrator M5,.

FIG. 5 shows the practical structure of the learning pulse generator 14 which functions to supply the learning pulses to the weight factor selective circuits 7, 8 and 9 when the standard pattern information stored in the memory 10 is successively read out from the memory 10 for the necessity oflearning.

The relation among a desired output for a standard pattern, an actual output or output from the decision circuit 16, necessity of learning, and an increase or decrease in weights due to the requirement for learning is tabulated in Table I.

In the table, +l represents a high level at +5 volts and 0" represents a low level at 0 volts.

Suppose, for example, that the conditions of the case I or IV are satisfied for a standard pattern, then it is apparent that any change in the weight factors of the weight elements in the weight factor selective circuits 7, 8 and 9 is unnecessary. More precisely, the inputs applied to an AND-gate A, include the actual output and the desired output which is passed through an invertor I,, while the inputs applied to a NAND-gate NA, include the desired output and the actual output which is passed through an invertor 1,. Thus, one of the three input signals applied to the AND-gate A, and NAND-gate NA, is in the low level and the two input signals applied to a NAND- gate NA remain in their high level with the result that a bista ble multivibrator BS, is not actuated and no learning pulse is generated. In the case II, the desired output is in the low level and the actual output is in the high level. Therefore, all the input signals applied to the AND-gate A, are in the high level. and a bistable multivibrator 58,, a monostable multivibrator MS, and the NAND-gate NA, are operated. When the monostable multivibrator MS, generates one pulse, the bistable multivibrator generates a plurality of pulses, for example, five pulses the number of which is equal to the number of variable stages of the weight factors, and thus five learning pulses are supplied to the weight factor selective circuits 7, 8 and 9. In this case, a negative voltage pulse of pulse width including the first pulse delivered from the bistable multivibra tor BS, appears at the decrement control signal output terminal 141. In the case III, the desired output is in the high level and the actual output is in the low level. Therefore, all the input signals applied to the NAND-gate NA, are in the high level so that the bistable multivibrator BS; and the monostable multivibrator MS, are operated to supply one learning pulse to the weight factor selective circuits 7, 8 and 9 from the terminal 143. In the meantime, a negative voltage at -10 volts appears at the increment control signal output terminal 142. B, and B, are buffer circuits. When the actual output coincides with the desired output in the course of the above opera tion, a signal is delivered from an AND-gate A, to drive the trigger pulse generator I2 so that the same operation is repeated for the next standard pattern. When no coincidence is reached between the actual output and the desired output, the operation described above is repeated.

FIG. 6 shows the practical structure of the summing circuit 15, the decision circuit 16 and the threshold value selection circuit 18. The summing circuit 15 includes an operational amplifier OP, and sums up the outputs from the weight factor seiective circuits 7, B and 9. The threshold value selection circuit I8 delivers an output W which is supplied to the decision circuit 16 as the threshold value. An operational amplifier OP, in the decision circuit 16 delivers +1 and 0" respectively when the output from the summing circuit 15 is larger and smaller than the threshold value W During learning, the threshold value selection circuit 18 supplies to the decision circuit 16 threshold values having a dead zone therebetween, while during discrimination, it supplies a threshold value having no dead zone. The threshold value selection circuit 18 has thus a function of selecting its output depending on the desired output. When, for example, a desired output +l" appearing at the output terminal 101 of the memory I0 is applied to the threshold value selection circuit 18, it delivers an output +01, while when a desired output "0 is applied thereto, it delivers an output m, These outputs +0) and to provide the threshold values employed in the decision circuit 16.

Therefore, the necessity of learning is concerned with the magnitude of the output from the summing circuit 15 relative to the magnitude of the threshold value +tu or w corresponding to the desired output "+1 or In the case I in Table l, there is no necessity for learning and any increase or decrease in the weight factors of the weight factor selective circuits 7, 8 and 9 is unnecessary since the output from the decision circuit 16 coincides with the desired output. This applies also to the case IV. In the case II, the output from the decision circuit 16 is +l whereas the desired output is 0. In this case, the following relation exists between the output from the summing circuit 15 and the threshold value m:

However, actually the following relation must hold between the output from the summing circuit 15 and the threshold value -w: n

In order to satisfy the above condition, the weight factors W W, and W, of the respective weight elements in the weight factor selective circuits 7, 8 and 9 must be decreased to reduce the output from the summing circuit 15. The situation is opposite in the case Ill. That is, the weight factors W W and W, must be increased, and the learning is completed when the output from the summing circuit 15 exceeds the threshold value +w. By the above manner of learning process, the case II is shifted to the case IV, while the case III is shifted to the case I.

Since the desired output is applied to the threshold value selection circuit 18 during learning to determine the corresponding threshold value in the manner described above, a dead zone exists between the threshold values +11: and corresponding to the desired outputs +1 and 0" as shown in FIG. 70. Thus, the decision circuit I6 has a function of a oneout-of-three decision element. In FIGS. 70 and 7b, the horizontal axis represents the output from the summing circuit 15, and the vertical axis represents the output from the decision circuit I6.

Referring to FIG. 6 again, a switch 8, in the threshold value selection circuit 18 is thrown to the side of the terminal a in the case of the learning and to the side of the terminal b in the case of the discrimination. When the switch S is thrown to the side of the terminal a to connect an operation amplifier OR, to the decision circuit I6, the threshold value W supplied from the threshold value selection circuit I8 to the decision circuit 16 corresponds to the desired output "+1" or 0" stored in the memory 10, while when the switch S is thrown to the side of the terminal b, the threshold value W. supplied from the threshold value selection circuit 18 to the decision circuit 16 is proportional to the threshold value We In the case of the discrimination, the decision circuit 16 acts as a conventional one out-ofltwo decision element because there is only one threshold value as seen in FIG. 7b.

FIG. 8 shows the practical structure of the weight factor selective circuit 7 including the weight element. The remaining weight factor selective circuit 8 and 9 have the same structure as the selective circuit 7. The weight factor of the weight element is variable over five levels which are +2 volts, +l volts, 0 volts, l volts and 2 volts.

Five bistable multivibrators BS BS BS BS; and 85,, have the function of selecting the weight factor and the outputs from the respective bistable multivibrators control the conduction and cutoff of five gating transistors 6 G G G and G More precisely, when anyone of the bistable multivibrators BS BS B8,, BS and BS delivers an output l at a level of-IO volts (herein, the negative logic is applied), the voltage at the drain electrode of the transistor connected to the output of the specific bistable multivibrator appears at its source electrode. Suppose that the input signal is applied from the bistable multivibrator 4, which sets the potential of the gate electrode of a transistor G at a level of 0 volts, this transistor G is cut off and the voltage appearing at the source electrode of the specific transistor is supplied to the summing circuit as the weight. Since two or more outputs of the bistable multivibrators B5,, B8,, BS BS, and B8,, cannot simultaneously take the value 1, only one of the five voltages representing the respective weights should appear as the weight. Gating transistors G 0,, and G,,, are cut off when their gate voltage is 0 volts. Only when all of these three transistors G G and G are in their cutoff state, the learning pulses are applied from the terminal I43 of the learning pulse generator 14 to the bistable multivibrators B8,, B8,, BS BS, and BS via a point A to shift the same. As soon as the first one of the live learning pulses arrives from the terminal 143 of the learning pulse generator 14, a decrement control signal of negative voltage is supplied from the terminal I of the learning pulse generator 14. Thus, a negative potential appears at the gate of the transistor (3,, provided that one of the bistable multivibrators BS 88,, B5,, B5, and BS, is delivering I ."As a result, the transistor (3,. conducts to short circuit the point A to ground and the first one of the five learning pulses cannot reach the bistable multivibrators B5,, B8,, 88,, BS, and BS A decrement control signal of 0 volts is applied as soon as the second one of the five Ieaming pulses appears, and the transistor G is thereby cut off so that the remaining four learning pulses are applied to the bistable multivibrators B5,, BS B5 and BS Consequently, the position of the output 1" from the bistable multivibrators B8,, B5,, B5 B5, and BS is shifted to the lower place, and this is followed by stepdown of the weight level by one step. When the bistable multivibrator BS, is delivering I," the transistor 0,, is cut off due to the fact that 0 volts is applied to the gate thereof, and all of the five learning pulses pass through the point A to shift the position of l until it returns to the bistable multivibrator BS again so that no shift can substantially occur. Similarly, an increment control signal of negative voltage appears as soon as the learning pulses are supplied from the terminal [43 of the learning pulse generator 14, and since the transistor 0,, is cut off unless the bistable multivibrator B8,, is delivering l the position of the output "1 is shifted to the higher place in response to the learning pulses.

The learning machine having a structure as described above operates in a manner as described below. Input pattern information supplied from the terminals I, 2 and 3 is stored in the bistable multivibrators 4, 5 and 6, and at the same time, written in the memory 10. The desired outputs for the input pat terns are also written in the memory 10 from the terminal I]. This operation is repeated for standard input patterns following the above-described input patterns so that the information of all the standard patterns is stored in the memory 10. When it is desired to make automatic learning on the basis of this information so as to obtain the desired output condition, the switch S, in FIG. 3 is switched over to urge the transistors 6,, G G and G to conduct and to cut off the transistors 0,, G G and (3,. Each time the clock pulse is supplied from the trigger pulse generator 12 to the memory 10, the stored information is supplied to the learning pulse generator 14 and the bistable multivibrators 4, 5 and 6 from the respective output terminals 101, 102, 103 and 104 of the memory 10. The information supplied to the bistable multivibrators 4, 5 and 6 is weighted by the weight factor selective circuits 7, 8 and 9, and is passed through the summing circuit I5 to be applied to the decision circuit 16 wherein the sum is compared with the threshold value W and the result appears at the output terminal 17 as an output +l or "0." In this process, the switch S in the threshold value selection circuit 18 is connected to the output terminal 101 of the memory 10 so that the threshold value W corresponds to the value +l or Thus, the decision circuit 16 has a function similar to the fu nction of a one-outof-three decision element for the threshold values having a dead zone therebetween and the output therefrom is classified under a severe condition compared with the classification by a one-out-of-two decision element. The actual output and the desired output are compared with each other in the learning pulse generator 14. When the actual output does not coincide with the desired output, the learning pulses and control signals are supplied to the weight factor selective circuits 7, 8 and 9 so as to bring coincidence therebetween, whereby the learning can proceed in the manner of error correction. When the learning proves that the actual output coincides with the desired output, the trigger pulse generator 12 is actuated to draw out the next information from the memory 10 by the clock pulse and a similar operation is carried out. As the above operation is repeated, the actual output becomes to always coincide with the desired output thereby completing the learning. When discriminating any input pattern after the learning is completed, the switch S in the threshold value selection circuit 18 is switched over to the side giving the threshold value W, so that the decision circuit 16 acts as a conventional one-out-of-two decision element.

What is claimed is:

l. A learning machine comprising a memory for storing a plurality of standard pattern information, a plurality of weight elements connected to respective weight selective circuits for applying a variable weight factor, selecting means for selecting the output from said memory and input pattern information to be discriminated, a threshold value selection circuit, a decision circuit for generating an output corresponding to the relative magnitude of the sum of outputs from said weight elements and an output supplied from said threshold value selection circuit, and a learning pulse generator for supplying learning pulses to said weight selective circuits thereby varying the weight factors of said weight elements when the output from said decision circuit does not coincide with a desired output and driving said memory for deriving the next standard pattern information when the output from said decision circuit coincides with the desired output, whereby the standard pat tern information can be successively learned for the discrimination of input pattern information.

2. A learning machine as claimed in claim 1, in which said memory comprises a plurality of shift registers, first gate means connected across the input and output terminals of said shift registers, second gate means interposed between signal input terminals and the input terminals of said shift registers, and common selectively conducting means for causing one of the groups of said first and second gate means to conduct while cutting off the other group, so that said first gate means are cut oh and said second gate means are urged to conduct by said selectively conducting means so as to successively write the standard pattern information supplied from said signal input terminals in said shift registers, and at the completion of the writing, said second gate means are cut off and said first gate means are urged to conduct by said selectively conducting means so as to successively supply the standard pattern information stored in said shift registers to said weight elements, and at the same time, to circulate same through said first gate means.

3. A learning machine as claimed in claim I, in which each said weight selective circuit comprises a plurality of bistable multivibrators connected in cascade, first gate means for gating the output from said learning pulse generator and supplying a trigger pulse to said bistable multivibrators and a plurality of second gate means applied with different voltages representative of weight factors, so that one of said second gate means is selected by the output from said bistable multivibrators connected in cascade.

4. A learning machine as claimed in claim 1, in which each said weight element comprises gate means which controls the passage of the voltage representative of the weight factor supplied from said weight selective circuit in response to the standard pattern information supplied from said memory or the externally supplied input pattern information to be discriminated.

5. A learning machine as claimed in claim 1, in which said learning pulse generator comprises two inverse coincidence circuits to which the output from said decision circuit and the desired output are applied as inputs, first pulse-generating means connected to one of said inverse coincidence circuits, weight factor decrement control signal generating means connected to said first pulse-generating means for controlling the decrement of the weight factor, weight factor increment control signal generating means receiving the output from the other said inverse coincidence circuit for controlling the increment of the weight factor, second pulse-generating means receiving the output from the other said inverse coincidence circuit and the output from said first pulse-generating means for responding to the logical sum of the inputs thereto for generating at least one learning pulse, and third pulse-generating means for reading out another standard'pattern informatlon stored In said memory upon detection 0 the coincidence between the two inputs applied to said inverse coincidence circuits,

6. A learning machine as claimed in claim 1, in which said threshold value selection circuit comprises selecting means for selecting one of a set of a desired output and a threshold value, and the desired output is selected during learning so that it is supplied as the threshold value.

7. A learning machine as claimed in claim 1, in which said threshold value selection circuit comprises means for selecting one of means generating a threshold value representative of a desired output and means generating a single threshold value and supplying the output from the selected means to said decision circuit 8. A learning machine as claimed in claim 1, further comprising a trigger pulse generator having pulse-generating means for generating a pulse in response to an output pulse supplied from said learning pulse generator, and means for stopping the operation of said learning pulse generator for a predetermined period of time in response to the output from said pulse-generating means.

i 18 i i

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3267431 *Apr 29, 1963Aug 16, 1966IbmAdaptive computing system capable of being trained to recognize patterns
US3267439 *Apr 26, 1963Aug 16, 1966IbmPattern recognition and prediction system
US3293609 *Aug 28, 1961Dec 20, 1966Rca CorpInformation processing apparatus
US3309674 *Apr 11, 1963Mar 14, 1967Emi LtdPattern recognition devices
US3311895 *Dec 30, 1963Mar 28, 1967IbmAdaptive logic system with artificial weighting of output signals for enhanced learning
US3408627 *Dec 28, 1964Oct 29, 1968Texas Instruments IncTraining adjusted decision system using spatial storage with energy beam scanned read-out
US3446950 *Dec 31, 1963May 27, 1969IbmAdaptive categorizer
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3934231 *Feb 28, 1974Jan 20, 1976Dendronic Decisions LimitedAdaptive boolean logic element
US4326259 *Mar 27, 1980Apr 20, 1982Nestor AssociatesSelf organizing general pattern class separator and identifier
US4518866 *Sep 28, 1982May 21, 1985Psychologics, Inc.Method of and circuit for simulating neurons
US4593367 *Jan 16, 1984Jun 3, 1986Itt CorporationProbabilistic learning element
US4599692 *Jan 16, 1984Jul 8, 1986Itt CorporationProbabilistic learning element employing context drive searching
US4599693 *Jan 16, 1984Jul 8, 1986Itt CorporationProbabilistic learning system
US4620286 *Jan 16, 1984Oct 28, 1986Itt CorporationProbabilistic learning element
US4751673 *Oct 28, 1987Jun 14, 1988The Babcock & Wilcox CompanySystem for direct comparison and selective transmission of a plurality of discrete incoming data
US4876731 *Feb 19, 1988Oct 24, 1989Nynex CorporationNeural network model in pattern recognition using probabilistic contextual information
US5040214 *Mar 8, 1989Aug 13, 1991Boston UniversityPattern learning and recognition apparatus in a computer system
US5060277 *Apr 25, 1988Oct 22, 1991Palantir CorporationPattern classification means using feature vector regions preconstructed from reference data
US5077807 *Feb 26, 1990Dec 31, 1991Palantir Corp.Preprocessing means for use in a pattern classification system
US5101361 *Sep 29, 1989Mar 31, 1992The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationAnalog hardware for delta-backpropagation neural networks
US5140538 *Dec 27, 1988Aug 18, 1992University Of ArkansasHybrid digital-analog computer parallel processor
US5263122 *Apr 22, 1991Nov 16, 1993Hughes Missile Systems CompanyNeural network architecture
US5293459 *Oct 23, 1991Mar 8, 1994U.S. Philips CorporationNeural integrated circuit comprising learning means
US5347595 *Aug 23, 1991Sep 13, 1994Palantir Corporation (Calera Recognition Systems)Preprocessing means for use in a pattern classification system
US5355438 *Apr 26, 1993Oct 11, 1994Ezel, Inc.Weighting and thresholding circuit for a neural network
US5361328 *May 7, 1993Nov 1, 1994Ezel, Inc.Data processing system using a neural network
US5416850 *Mar 18, 1993May 16, 1995Ezel, IncorporatedAssociative pattern conversion system and adaption method thereof
US5479574 *Apr 1, 1993Dec 26, 1995Nestor, Inc.Method and apparatus for adaptive classification
US5479575 *Oct 31, 1994Dec 26, 1995Mitsubishi Denki Kabushiki KaishaSelf-organizing neural network for pattern classification
US5506915 *Sep 16, 1994Apr 9, 1996Ezel IncorporatedAssociative pattern conversion system and adaptation method thereof
US5517667 *Jun 14, 1993May 14, 1996Motorola, Inc.Neural network that does not require repetitive training
US5555439 *Jun 9, 1992Sep 10, 1996Hitachi, Ltd.Learning system and a learning pattern showing method for a neural network
US5574827 *Apr 17, 1995Nov 12, 1996Motorola, Inc.Method of operating a neural network
US5633988 *Dec 10, 1992May 27, 1997Yozan Inc.Adaptation method for data processing system
US5720002 *Apr 17, 1995Feb 17, 1998Motorola Inc.Neural network and method of using same
US5742740 *Jan 15, 1993Apr 21, 1998Atlantic Richfield CompanyAdaptive network for automated first break picking of seismic refraction events and method of operating the same
US5781701 *Apr 17, 1995Jul 14, 1998Motorola, Inc.Neural network and method of using same
US6625588 *Mar 23, 1998Sep 23, 2003Nokia OyjAssociative neuron in an artificial neural network
US6652283Dec 30, 1999Nov 25, 2003Cerego, LlcSystem apparatus and method for maximizing effectiveness and efficiency of learning retaining and retrieving knowledge and skills
US6995702Apr 2, 2001Feb 7, 2006Biosgroup Inc.Automatic evolution of mixed analog and digital electronic circuits
Classifications
U.S. Classification706/34, 192/113.1
International ClassificationG06K9/62, G06F7/02
Cooperative ClassificationG06F7/023
European ClassificationG06F7/02A