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Publication numberUS3644758 A
Publication typeGrant
Publication dateFeb 22, 1972
Filing dateJul 11, 1969
Priority dateJul 15, 1968
Publication numberUS 3644758 A, US 3644758A, US-A-3644758, US3644758 A, US3644758A
InventorsMatsue Shigeki
Original AssigneeNippon Electric Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Flip-flop circuit
US 3644758 A
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Description  (OCR text may contain errors)

I United States Patent [15] 3,644,758 Matsue Feb. 22, 1972 [54] FLIP-FLOP CIRCUIT Primary Examiner-Donald D. Porter [72] Inventor shlsekl MflueTokyohm Assistant Examiner-R. C. Woodbridge [73] Assignee: Nippon Electric Company, Limited, y-i l p and Calimafde Minato-ku, Tokyo, Japan [22] Filed: July 11,1969 [57] n ABS CT A App No: 841,064 flip op circuit having a plurality of input signal terminals and a plurality of current terminals corresponding to the input signal terminals on a one-to-one basis (corresponding on a one-to-one basis is defined in this application to mean they are equal in number and the relationship being described ex- July 15, 1968 Japan Ail/50128 ists between the [n]th terminal of one and the [nlth terminal of the other; the [n-l ]th the terminal of one and the [n-l ]th [52] U.S.Cl .307/291, 328/206 terminal of the other; and so on), and a further current ter- [51] Int. Cl. ..H03k 3/12 minal. The output is responsive to the input signal applied to [58] Fi ld of Search..... ....307/289, 291; 328/206 the input signal terminal corresponding to that one of the current terminals having current flow; the output being the same [56] R f en e Cited as that generated just previously when the current flow is to said further current terminal. A plurality of synchronizing UNITED STATES PATENTS signal terminals corresponding to the plurality of current terrninals supplies a current to an associated one of the plurality f Ealvmen "328/206 X of current terminals during the time when the synchronizing "307/289 X signal at that synchronizing signal terminal is at a first value, 3'424928 H1969 Pne] ct "307/289 x and supplying a current to said further current terminal when 3437840 4,1969 Mlmay et "307/291 x all the synchronizing signals are at a second value. 3,440,449 4/1969 Pnel et a1 ..307/29l 3,446,989 5/1969 Allen et al ..307/29l X 1 Claims, 4 Drawing Figures 51 S2 Vcc C2 Cl V'SQ PATENTEBFEB 22 I972 SHEET 2 [IF 3 NOE INVENTOR Shigeki Moisue PATENTEDFEBZZ I972 3,644,758

SHEET 3 BF 3 Timing i 2 3 4 5 6 7 8 9 io W iiiiiiiiii Information I K Input 2| Information Synchronizing Signal synchronizinqgg Signal Internal Terminal INVENTOR Shigeki Moisue by M,

ATTORN; S.

FLIP-FLOP CIRCUIT BACKGROUND OF THE INVENTION This invention relates to an improved information processor and more particularly to an improved flip-flop circuit employed in such processors.

information processors such as electronic computers, and electronic exchanges have made remarkable progress in recent years and have gradually become larger and larger systems. With this tendency towards size, it has become impossible to adequately process the inspection and trouble shooting of these systems manually. For this reason, it has become the general practice to automatically perform the inspection and trouble-shooting of a complex system by means of an electronic computer. This, however, has resulted in the requirement of an extremely large computing time for the inspection of the system even though the computer is of the ultra-high-speed type where the system under inspection has a conventional composition and,'therefore, an extremely large number of inspection items.

OBJECTS OF THE INVENTION Accordingly, it is the object of this invention to provide means which simplify the inspection of processors.

It is another object of this invention to modify the composition of the information processing system so as to allow for the easy inspection of components.

It is a further object of this invention to provide a novel flipflop circuit to be used in an information processor.

It is a still further object of this invention to provide a flipflop circuit with a plurality of information transmission paths or systems.

SUMMARY OF THE INVENTION Briefly, the invention is predicated upon a flip-flop circuit having a plurality of input signal terminals and a plurality of current terminals corresponding to the input signal terminals on a one-to-one basis (corresponding on a one-to-one basis is defined in this application to mean they are equal in number and the relationship being described exists between the [n]th terminal of one and the [n]th terminal of the other; the [n-llth terminal of one and the ln-llth terminal of the other, and so on), and a further current terminal. The output is responsive to the input signal applied to the input signal terminal corresponding to that one of the current terminals having current flow; the output being the same as that generated just previously when the current flow is to said further current terminals. A plurality of synchronizing signal terminals corresponding to the plurality of current terminals supplies a current to an associated one of the plurality of current terminals during the time when the synchronizing signal at that synchronizing signal terminal is at a first value, and supplying a current to said further current terminals when all the synchronizing signals are at a second value.

It is a feature of this invention to provide such flip-flop circuits connected in cascade.

The above mentioned and other features and objects of this invention and the manner of attaining them will become more apparent and the invention itself will best be understood by DETAILED DESCRIPTION OF THE INVENTION Referring now to FIG. 1, thereis shown a flip-flop circuit embodying this invention. In the figure, terminals V and V are biased so that terminal V provides a potential several volts higher than terminal V Terminals l and 2 denote the information input terminals, terminal V the threshold potential supply terminal, and terminals C1 and C2 the synchronizing signal terminals. Terminals I, and I are the current supply terminals associated with the information input terminals and terminal 1;, is the other current supply terminal. Transistor Q12, resistor R6, transistor Q13 and resistor R7 form a circuit for shifting the level of the synchronizing signal. Terminal V is the threshold potential supply terminal for the synchronizing signal, and terminals 3 and 4 are the information output terminals.

The circuit shown in FIG. 1 includes four current switching circuits. The first current switching circuit, comprising transistors Q1, Q2, and Q3 turns transistor Q1 on when synchronizing signal Cl is at a high level (hereinafter referred to as l to allow current to flow through current supply terminal I, and, if synchronizing signal C2 is 1, turns transistor Q2 on to allow current to flow through current supply terminal I When synchronizing signals C1 and C2 are both at a low level (hereinafter referred to as O), the circuit turns transistor Q3 on to allow current to flow through the further current supply terminal I The second current switching circuit consists of transistors Q8 and Q9 with their commonemitter terminals connected via current supply terminal I, to the collector of transistor 01 so that transistors 08 and Q9 act as the current switching circuit only when transistor 01 is on and, if transistor Q] is off, are both turned off, irrespective of the input voltage to terminal l.

The third current switching circuit consists of transistors Q10 and Q11 with their common emitter terminals connected via current supply terminal l to the collector of transistor Q2, so that transistors Q10 and Q11 act as the current switching circuit only when transistor 02 is on and, if transistor 02 is off, are both turned off, irrespective of the input voltage to terminal 2.

The fourth switching circuit is composed of transistors Q6 and 07 with their common emitter terminals connected via current supply terminal I, to the collector of transistor Q3, so that transistors Q6 and Q7 act as the current switching circuit only when transistor Q3 is on and, if transistor O3 is off, are both turned off.

These second, third and fourth current switching circuits employ in common the same output terminals 3 and 4 as their output terminals. The input end of the fourth switching circuit, i.e., the bases of transistors Q6 and Q7, are directly connected to output terminals 3 and 4', this makes the output signals appearing at output terminals 3 and 4 the input information signals to the fourth switching circuit.

Accordingly, if the synchronizing signal appearing at synchronizing terminal C1 is 1 the second current switching circuit operates and information signals 1 O") and (0, l appear on output terminals 3 and 4 in response to input signal (1", 0) on information input terminal 1, respectively. And, if the synchronizing signal appearing at synchronizing signal terminal C2 is 1", then the third current switching circuit operates and the output at output terminals 3 and 4 are (l, 0) and (0", l in response to the input signal (1", 0") on information input terminal 2, respectively. Further, if the synchronizing signals appearing at synchronizing terminals Cl and C2 are both 0", the fourth current switching circuit operates, but the output terminals hold their outputs existing just before transistor Q3 turns on since the input end of this switching circuit is connected to output terminals 3 and 4.

Summarizing the above, the flip-flop circuit shown in FIG. 1

operates and delivers the output by receiving the information input from input terminal 1 if synchronizing signal Cl is 1" and the information input appearing at input terminal 2 if synchronizing signal C2 is 1". If synchronizing signals C1 and C2 are both said fiip-fiop circuit operates so as to keep itself in the condition existing at that time.

If now an information processor includes the flip-flop circuits shown in FIG. 1 and the first input information system comprising the circuit from input terminal 1 to synchronizing information terminal Cl is used to process an ordinary data fiow and the second input information system consisting of the circuit from input terminal 2 to synchronizing information terminal C2 is used to process other work such as the inspection of the system of the information processor, the resultant easy performance of the inspection of the system is achieved.

While in FIG. 1 a flip-flop circuit with two input terminals and two synchronizing signal circuits is shown, it will be appreciated by those skilled in the art that a fiip-fiop circuit having more than two information terminals and more than two synchronizing signal terminals may be similarly constructed.

Referring now to FIG. 2, there is presented a composite flipflop circuit which is composed of two stages of the flip-flop circuit of this invention connected in cascade. In this figure, S1 is the former stage flip-flop circuit having the same circuit construction as the circuit shown in FIG. 1 and including transistors 01 through Q13 and resistors R1 through R7.

The second stage flip flop circuit S2 has the first current switching circuit comprising transistors Q21, Q22 and Q23, the second current switching circuit consisting of transistors Q28 and Q29, and the third current switching circuit comprising transistors Q26 and Q27. The emitters of transistors Q21, Q22 and Q23 in the first current switching circuit are connected to common resistor R21. The bases of these transistors Q21 and Q22 employ synchronizing signal terminals C1 and C2 and the synchronizing signal shift circuit comprising transistors Q12 and Q13 of the first stage flip-flop circuit S1 commonly and are connected with connecting lines L3 and L4 to the emitters oftransistors Q12 and Q13 respectively.

The second current switching circuit is provided with input terminal 11 and threshold potential supply terminal V with the emitters of its transistors Q28 and Q29 commonly connected to the collector of transistor Q23 via current supply terminal I,,. Input terminal 11 is connected by connecting line L1 to output terminal 3 of former stage flip-flop circuit S1 and terminal V to output terminal 4 of the initial flip-flop circuit via connecting line L2.

The third current switching circuit consists of transistors Q26 and Q27 of which the emitters are connected to the collectors of transistors via current supply terminals 1, and I used commonly for said emitters.

The second and third current switching circuits have the same output terminals 5 and 6 which are connected to the input end of the third current switching circuit, i.e., the bases oftransistors Q26 and Q27.

A description will now be given concerning the operation of the composite flip-flop circuit consisting of flip-flop circuits S1 and S2. If the synchronizing signal appearing at the synchronizing signal terminal Cl is l and the synchronizing signal appearing at synchronizing terminal C2 is 0", the current switching circuit comprising transistors Q8 and Q9 operates as described previously and allows information signals (1", 0") and ("0, I to appear at terminals 3 and 4 in response to information input l 0") applied to input terminal 1, respectively.

Under the above condition, the synchronizing signal appearing at synchronizing signal input terminal C1 is applied to transistor Q21 in the second stage flip-flop circuit S2, turning transistor Q21 on. As a result, the current switching circuit comprising transistors Q26 and Q27 is actuated. Since the input end of this current switching circuit is connected to output terminals 5 and 6, the outputs at output terminals are held as they are.

When the synchronizing signal at synchronizing information terminal C1 changes from I to 0", transistor O3 in the first stage flip-flop circuit S1 turns on to allow the current switching circuit comprising transistors 06 and O7 to operate and hold the outputs appearing at output terminals 3 and 4 as they are.

Under the above condition transistor Q23 turns on in the second stage flip-flop circuit S2 and this causes the current switching circuit comprising transistors Q28 and Q29 to operate and allow outputs (1", O") and (0' l to appear at information output terminals 5 and 6 in response to information input (1", O) appearing at terminal 1 just before the output of the first stage flip-flop, i.e., the synchronizing signal at synchronizing signal input terminal Cl turns 0".

When the synchronizing signal at synchronizing signal input terminal C1 turns again from 0" to I transistor Q21 in the second stage flip-flop circuit turns on and allows the current switching circuit comprising transistors Q26 and Q27 to operate. This permits the outputs appearing at output terminals 5 and 6 to remain as they are in their previous conditions regardless of the output of the first stage flip-flop circuit S1. While under the above condition transistor Q1 turns on in the first stage flip-flop circuit and causes the current switching circuit consisting of transistors Q8 and O9 to operate and allow the output informations corresponding to the information at the input terminal 1 to appear at output terminals 3 and 4.

A still more detailed description of the flip-flop circuit shown in FIG. 2 will be given while making reference to the waveform diagram shown in FIG. 3.

As seen from the diagram, at time T2 the information output of 1" appears at output terminal 3 of the first stage flipfiop circuit S1 in response to input information l of input terminal 1 during the period when synchronizing signal input C1 is assuming a 1", while output terminal 5 of the second stage flip-flop circuit holds its output in the previous condition, i.e., 0".

Then, when the time passes to time T4 and synchronizing signal C1 turns 0, the information signal appearing at output terminal 3 of the first stage flip-flop circuit continues to be in the condition existing just before the synchronizing signal changed to 0", while the output appearing at output terminal 5 of the second stage flip-flop circuit S2 changes to I in response to output information I of the first stage flip-flop circuit S1.

At time T7 the synchronizing signal C1 is placed in the 0" condition and synchronizing signal C2 changes to The output appearing at the output terminal of the first stage flipfiop circuit changes to 0" in response to the input information 0" appearing at input terminal -2 and the output at output terminal 5 ofthe second stage flip-flop circuit continues its l condition existingjust before the synchronizing signal C2 changes to 1".

When the time further passes to time T8 at which time synchronizing signal C2 changes to the output at the output terminal of the first stage flip-flop circuit S1 holds its output information 0" existing just before synchronizing signal C2 changes to 0, while the output at output terminal 5 of the second stage flip-flop circuit changes to 0" in response to the output information 0" at output terminal 3 of the first stage flip-flop circuit S1.

As is evident from the description given above, the first stage flip-flop circuit S1 of the circuit shown in FIG. 2 (i.e., the flip-flop circuit shown in FIG. 1) changes its output in coincidence with the rising edge of the synchronizing signal in contrast with the composite flip-flop circuit of FIG. 2 ofwhich the output is changed in coincidence with the falling edge of the synchronizing signal.

A flip-flop circuit which changes its output in coincidence with only the falling or rising edge of a synchronizing signal as mentioned above is quite advantageous for a single-phase synchronizing system operation circuit. Also, if the flip-flop circuit is provided with two input information systems (one system comprising the circuit extending from input terminal 1 to synchronizing signal terminal Cl and another system comprising the circuit extending from input terminal 2 to synchronizing signal terminal C2) as .described above, then it becomes possible to compose an ordinary information processing system through the use of the first input information system and to perform processing of a system inspection and the like through the use of the second input information system, thereby expanding the facilities of the system further.

It is also evident that the second stage flip-flop circuit S2 can be used independently as a flip-flop circuit.

In the above case, output informations (1", and (0?, l") will appear at output terminals and 6 respectively in response to the information (1", 0) impressed on input terminal 11 only when synchronizing signals C1 and C2 are both If either of synchronizing signals Cl and C2 is 1, output terminals 5 and 6 continue to hold their previous outputs.

FIG. 4 is a block diagram indicating an example of the composition of a system formed using a flip-flop circuit embodying the present invention. Terminal C1 is the synchronizing signal terminal and corresponds to either one of the synchronizing signal terminals of the flip-flop circuit of the present invention, for instance terminal C1 of the circuit shown in FIG. 1. Terminal C2 is another synchronizing signal terminal of the flip-flop circuit of the present invention and corresponds to, for example, terminal C2 of the circuit shown in FIG. 1.

Fl through F4 represent the flip-flop circuits embodying the present invention and terminals all through a4 provided for the flip-flops respectively are the second information input terminals and correspond to, for example, terminal 2 of the circuit shown in FIG. 1.

Flip-flop circuits Fl through F4 operate from the synchronizing signal normally entering from terminal C1. But, if a second synchronizing signal enters the flip-flop circuits from terminal C2 under a condition where the synchronizing signal from terminal Cl is interrupted, the flip-flop circuits operate in accordance with the input signals entered from information terminals al through a4 for the second synchronizing signal regardless of the ordinary input signal.

Terminal Al is the external terminal connected to the second input information terminal a4 of flip-flop circuit F4. The output of flip-flop circuit F4 is connected to the second information input terminal a3 of flip-flop circuit F3. The output of flip-flop circuit F3 is connected to'the second information input terminal a2 of flip-flop circuit F2. The output of flip-flop circuit F2 is connected to the second information input terminal al of flip-flop circuit F1, and the output of flipflop circuit F1 is connected to the output terminal A2 of the system. As a result, it follows that flip-flop circuits F4, F3, F2 and F1, operating in conjunction with the second information transmission system consisting of the second synchronizing signal terminal C2 and the second information input signal terminals al through a4, composing one shift register.

If a system is constructed in accordance with the above, then it becomes possible to set any information into flip-flops F1, F2, F3 and F4 by means of input terminal A1, output terminal A2, and the second synchronizing signal terminal C2 or to read out the conditions of these flip-flops F1, F2, F3 and F4 at any time.

As mentioned above, the flip-flop embodying the present invention provides means for setting any information to all flipflop circuits involved in a system as well as externally reading the informations of all flip-flops within the system, thereby greatly facilitating the inspection and trouble shooting of the system. In general, if it is intended to realize the result achieved here with a conventional system, the output terminals and internal wiring of the system will become extremely complex. But, use of the flip-flop circuits of the present invention will make it possible to provide said facilities merely by equipping the system with an additional three sets of input and output terminals as mentioned above.

It should be noted that the flip-flop circuits described above employ the NPN-transistors but may be operable using PNP- or MOS-transistors in lieu of the NPN-transistors. Further, it should be noted that no description is given to the bias supply in the flip-flop circuits mentioned above. This, however, may

be easily achieved by designing the system so as to self-contain a bias supply or by providing a bias voltage terminal to which a bias voltage may be connected externally.

While the principles of the invention have been described in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of the invention.

What is claimed is:

1. In combination, a flip-flop circuit comprising plural first transistor circuit means each comprising two differentially connected transistors in pairs thereof, a first input terminal for receiving a threshold potential, a second input terminal for receiving input information, a first driving circuit, a current input terminal to which a driving current is applied from said first driving circuit, said first driving circuit producing driving current responsive to a plurality of synchronizing signals which are nonsynchronous with respect to one another, and a pair of output terminals through which a pair of binary current output signals consisting of information similar and opposite to the input information applied to said second input terminal are produced upon application of a corresponding one of said driving currents produced by high-level signal values for said synchronizing signals to said current input terminal, each of said plural first transistor circuit means being independent from one another;

a first transistor output pair circuit means having a pair of input terminals which are connected to said pair ofoutput terminals of each of said plural first transistor circuit means, a synchronizing signal input terminal and a pair of output terminals through which a pair of outputs is produced upon application of a pair of binary current output signals to said pair of input terminals from either one of said plurality of first transistor circuit means in synchronization with a high-level signal of said synchronizing signals to be applied to said synchronizing signal input terminal; first flip-flop circuit means comprising two transistors, emitters of which are connected in common, a pair of input terminals to which a pair of outputs of said first transistor output pair circuit means are coupled, an input terminal through which a driving current is applied from said first driving circuit, said driving current being produced at the change of all of said synchronizing signals into low-level signals, and means responsive to the application of said driving current to said input terminal for maintaining the information previously obtaining at said pair of outputs;

a second transistor circuit means comprising two transistors differentially connected in pairs, a pair of input terminals coupled to said pair of outputs of said first transistor output pair circuit means, a current input terminal to which driving currents are applied from a second driving circuit which is independent from said first driving circuit and produces driving currents by the application of said plurality of synchronizing signals, and a pair of output terminals through which a pair of binary current output signals consisting of information similar to said pair of outputs of said first transistor output pair circuit means is produced upon application of one of said driving currents produced at a change of all ofsaid synchronizing signals into low-level signals to said current input terminal;

a second transistor output pair circuit having a pair of input terminals which is coupled to said pair of outputs of said second transistor circuit means, a synchronizing signal input terminal and a pair of output terminals through which a pair of outputs are produced upon application of said pair of outputs to said pair of input terminals from said second transistor circuits in synchronization with said one of driving currents produced at change of all said synchronizing signals into low-level signals;

a second flip-flop circuit means comprising two transistors, emitters of which are connected in common, a pair of input terminals to which a pair of outputs of said second ing signals to said input terminal means for maintaining transistor output pair circuit means are coupled, input said pair of outputs at the previous information values terminal means through which driving currents are apthefcfofiand plied from said second driving circuit, and means responterminal means Coupled to saifj PF of Outputs of Said sive to the application of either one of said driving cur- Second transistor P" P meansrents produced by high level signals for said synchroniz-

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4237387 *Feb 21, 1978Dec 2, 1980Hughes Aircraft CompanyHigh speed latching comparator
US4309625 *Oct 31, 1979Jan 5, 1982Nippon Electric Co., Ltd.Flip-flop circuit
DE2929148A1 *Jul 19, 1979Feb 14, 1980Philips NvFlankengetriggertes flipflop
Classifications
U.S. Classification327/219
International ClassificationG11C19/28, G11C19/00, H03K3/286, H03K3/00
Cooperative ClassificationH03K3/286, G11C19/28
European ClassificationH03K3/286, G11C19/28