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Publication numberUS3644894 A
Publication typeGrant
Publication dateFeb 22, 1972
Filing dateNov 24, 1969
Priority dateNov 24, 1969
Publication numberUS 3644894 A, US 3644894A, US-A-3644894, US3644894 A, US3644894A
InventorsMccrea Alan F
Original AssigneeRobertshaw Controls Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Supervisory control system having alternate scanning
US 3644894 A
Abstract  available in
Images(10)
Previous page
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Claims  available in
Description  (OCR text may contain errors)

I United States Patent 51 3,644,894 McCrea Feb. 22, 1972 [54] SUPERVISORY CONTROL SYSTEM Primary ExaminerHar0ld I. Pitts HAVING ALTERNATE SCANNING Attorney-Auzville Jackson, Jr., Robert L, Marben and Anthony A. O'Brien [72] lnventor: Alan F. McCrea, Richmond, Va. [73] Assignee: Robertshavv Controls Company, ABSIRACT Richmond A supervisory control system including a plurality of remote [22] Filed: Nov. 24, I969 stations each having a hundreds address, a group of field points associated with each remote station, each field point Appl 879'403 having a units address, and a central control station communicating simultaneously with all of the remote stations and [52] US. CL ..340/ 163, 340/147 generating alarm-scanning signals and control signals in 1 1 Illtq sequential alternation with each signal including a two digit bi- [If nary coded decimal address such that two alarm canning r control signals are required to address an individual field point [56] Re'em CM at a remote station whereby alarm scanning and control function operation may be continuously carried out without inter- UNITED STATES PATENTS ference therebetween. The system detects off-normal condi- 3,110,013 I l/l953 Breese ..340/l63 tions at the field points by scanning groups until a group hav .4 3/l964 Silllmafln 340/163 ing an off-normal condition is detected at which time the in- 3,244,805 4/ I966 Evans 3 0/ 3 X dividual field points of the group are scanned to locate the 3 ,41 3,606 1 111968 Chtcanowrca. ..340/ l 63 fi ld point having the fiL l condition 3,444,521 5/1969 Breese ..340/l63 20 Claims, 12 Drawing Figures I000 I002 22 2O I LOCAL ggflggt I REMOTE REMOTE POINT 2 STATION STATION I GROUP 24 (H62) (F G 3) I000 I002 I004 REMOTE REMOTE STATION POINT (FIGB) GROUP I000 I002 REMOTE IOJ4 REMOTE STATION POINT (FIG. 3) GROUP PATENTEUFB22 I972 3. 644.894

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F l I I I l I I I I IIL SUPERVISORY CONTROL SYSTEM HAVING ALTERNATE SCANNING BACKGROUND OF THE INVENTION I Field of the Invention The present invention pertains to supervisory control systems, and more particularly, to such systems for use in controlling and acquiring data from a plurality of remote field points arranged in groups.

2. Description of the Prior Art With the increase in complexity of industrial and commer cial processes, centralized control systems capable of supervising a great number of field points from a central station have become a necessity. In order to increase the capacity of such systems and to fully provide centralization for an entire process, many times it is required that field points located at considerable distances from the central control station be included in the control system; however, the control systems must be capable of simple and inexpensive expansion and modification to accommodate changes in operation for equipment. Such control systems must also be capable of providing the functions of alarm scanning for rapid discovery of off-non mal conditions at the field points, indication and logging of contact status and analog values at the field points and manual or automatic control of equipment at the remote points.

Conventional supervisory control systems capable of providing the above-mentioned functions normally have the disadvantage of requiring either a great number of wires or communication channels between the field points and the central control station thereby limiting the total field point capacity of the system and rendering system modification and expansion an expensive and difficult task. The use of multiplex systems to provide the above functions has the disadvantage of slow system response. Other disadvantages inherent in conventional supervisory control systems are the great amount of time required to complete an alarm scan and the interference of alarm scanning with other basic control functions of the system.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to construct a supervisory control system that is simple and inexpensively modified and provides fast alarm scanning without interference with basic control functions.

The present invention is summarized in a supervisory control system having a plurality of remote stations coupled with a central control station and a group of field points associated with each remote station, the central control station including an alarm-scanning signal generator providing a plurality of alarm-scanning signals for interrogating the remote stations for off-normal conditions at the groups of field points, a control signal generator providing a plurality of control signals for operating field points at the remote stations, a transmitter communicating the alarm scanning and control signals to the remote stations. and sequencing means alternating the transmitting of each of the alarm scanning and control signals whereby the transmitter communicates the alarm scanning and control signals to the remote stations in sequential alternation to permit continuous, noninterfering alarm and control operation.

Another object of the present invention is to communicate with a virtually unlimited number of remotely located field points over a small number of signal transmission channels.

A further object of the present invention is to provide continuous alarm scanning for off-normal conditions at field points such that the off-normal conditions are identified within a short period of time after their initial occurrence.

The present invention has another object in that alarm scanning and control operation may be simultaneously obtained without interference.

Some of the advantages of the present invention over the prior art are that the number of signal channels are reduced, each word generated at the central control station includes only two address digits thereby permitting the use of words having a reduced number of BITs without sacrificing functional operation, and alarm and control operations are alternated to permit continuity of both without interference.

Further objects and advantages of the present invention will become apparent from the following description of a preferred embodiment taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a schematic diagram of the supervisory control system of the present invention.

FIG. 2 is a schematic diagram of the central control station of FIG. I.

FIG. 3 is a schematic diagram of a typical remote station of FIG. 1.

FIG. 4 is a schematic diagram of the sequence control circuit of FIG. 2.

FIG. 5 is a schematic diagram of the clock and sequence select circuit of FIG. 4.

FIG. 6 is a schematic diagram of the alarm scan hundreds addressing circuit of FIG. 4.

FIG. 7 is a schematic diagram of the alarm scan units addressing circuit of FIG. 4.

FIG. 8 is a schematic diagram of the control function hundreds addressing circuit of FIG. 4.

FIG. 9 is a schematic diagram of the control function units addressing circuit of FIG. 4.

FIG. 10 is a schematic diagram of the data transmission register circuit of FIG. 4.

FIG. 11 is a schematic diagram of the remote point interface of FIG. 3.

FIG. 12 is a timing chart of the basic signals utilized in the operation of the supervisory control system of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A supervisory control system according to the present invention is illustrated in block diagrams in FIG. I and includes a central control station and a plurality of remote stations I000 interconnected by a telephone line 20. Telephone line 20 is a standard voice-grade telecommunication link capable of transmitting frequency multiplexed digital information in a full duplex mode. Telephone line 20 is connected with remote stations 1000 such that signals generated by central control station 100 or any of remote stations 1000 are received simultaneously at the inputs of all stations. The telephone line 20 is shown for exemplary purposes only, and any other communication medium capable of transmitting the required information may be utilized with the present invention.

A group of local points 22 are connected with central control station 100 through a multiconductor cable 24 such that direct current digital and analog signals may be communicated between central control station 100 and local points 22. Normally, local points 22 are located in close proximity to central control station I00 to eliminate the requirement of a telecommunication link such as telephone line 20.

Stations 1000 are located at positions distantly remote from central control station 100. Each remote station 1000 has associated therewith a group of remote points 1002, and remote points 1002 are interconnected with each remote station I000 through a multiconductor cable I004.

The central control station 100 is illustrated in block diagrams in FIG. 2. The entire operation of the supervisory control system is coordinated by a sequence control circuit 102 which receives an input through a multiconductor cable 104 from manual point selection equipment I06. Equipment I06 is utilized to provide an operator at central control station I00 with direct access to any individual field point; and, accordingly, may be constructed in any conventional manner such as by the use of pushbuttons, thumbwheel switches, or the like capable of generating coded address signals compati ble with sequence control circuit 102. An input to sequence control circuit 102 is also received on a multiconductor cable 108 from manual control function equipment 110 which may be constructed in any conventional manner such as by the use of pushbuttons, toggle switches or the like capable of generat ing signals corresponding to such functions as the starting or stopping of a motor or the changing of the set point of an analog controller at a field point, for example. A control scan address generator 112 provides compatible address and function signals for automatically performing a sequence of functions such as, for example, programmed motor control. The signals from control scan address generator 1 12 are applied to sequence control circuit 102 through a multiconductor cable 114. Equipment 106 and 110 and generator 112 comprise a signal source 115 for providing control, address and function signals to sequence and control circuit 102.

Peripheral annunciation equipment 116 includes conventional display, recording and logging apparatus such as pilot lamps, typewriters or any other means for displaying to the operator information with respect to conditions at the field points. Signals corresponding to addresses and controls for the peripheral annunciation equipment 116 are received through a multiconductor cable 118 from sequence control circuit 102, and digital data corresponding to the status of contacts at the field points is transmitted to peripheral annunciation equipment 116 through a multiconductor cable 120 from an eight-BIT scanner-receiver 122 and local points 22. Peripheral annunciation equipment 116 supplies hold signals to sequence control circuit 102 on a lead 124.

Peripheral analog indication equipment 126 includes a combination of indicators, recorders and the like used to measure analog signals such as voltages or currents which are representative of remote analog variations such as temperature, pressure and humidity. The peripheral analog indication equipment 126 receives analog signals from an analog telemetry receiver 128 on a lead 130 and from analog transducers 132 for local points 22 through a lead 134. Input signals to peripheral analog indication equipment 126 are received from scanner-receiver 122 on a multiconductor cable 136 and local points 22 on a multiconductor cable 138 which input signals correspond to a range select" code that is transmitted simultaneously with the analog values from analog telemetry receiver 128 and analog transducer 132 such that when a plurality of analog ranges are utilized the proper range may be selected to accurately indicate the analog values at peripheral analog indication equipment 126. Peripheral analog indication equipment 126 also receives an input indicating "in-scan status of a remote station or the local points 22 from a local point interface 140 and scanner-receiver 122 on leads 142 and 144, respectively, which input is also supplied to equipment 106 and 110, generator 112 and peripheral analog equipment 1 16.

A l6-B1T scanner-transmitter 146 receives inputs from sequence control circuit 102 on multiconductor cables 148, 150 and 152 which correspond to word-type, function and address information, respectively. These signals are also applied to local point interface 140 through multiconductor cables 154, 156 and 158, respectively. Scanner-transmitter 146 interrogates sequentially the plurality of digital inputs on cables 148, 150 and 152 and transmits serially the true or false character of these inputs as mark and space keying signals, respectively, to a frequency shift, keyed audio tone trans mitter 160 on a lead 162. The output of tone transmitter 160 is applied to telephone line 20 for communication to remote sta tions 1000. A wide range of transmission rates may be utilized; for example, 160 bits per second for a nominal word rate of l6-BlT words per second. At the beginning of the transmission of each word, scanner-transmitter 146 supplies a synch" pulse to sequence control circuit 102 on a lead 164 to synchronize the operation of sequence control circuit 102.

A tone receiver 166 receives an input from telephone line 20 and supplies an alarm output on a lead 168 to sequence control circuit 102. In similar fashion an alarm output is received by sequence control circuit 102 on a lead 170 from local point interface 140. A tone receiver 172 receives an input from telephone line 20 and supplies an output to scanner-receiver 122 on a lead 174. Scanner-receiver 122 receives signals in a serial fashion and converts the signals to eight-BIT words in parallel fashion for representing "contact status," range select" and in-scan information on mul ticonductor cables and 136 and lead 144, respectively.

A tone receiver 176 receives an input from telephone line 20 and supplies an output to analog telemetry receiver 128 on a lead 178. As is conventional, analog signals may be transmitted from the field by variance of the frequency of alternations between mark and space; and, the alternating signals are supplied to analog telemetry receiver 128 where they are converted into a current signal representative of the original analog signal.

Tone transmitter and tone receivers 166, 172 and 176 each operate on a preassigned carrier frequency channel, and the channels are frequency multiplexed on telephone line 20 thereby requiring relatively few frequency channels for the system.

Scanner-transmitter 146, scanner-receiver 122, analog telemetry receiver 128, tone transmitter 160 and tone receivers 166, 172 and 176 are all conventional equipment which need not be specifically described in detail for the pur pose of the present invention. The above equipment is commercially available as model numbers QST-lb, QSR-8, QATR-lO, QT-SO and 011-30, respectively, manufactured by Quindar Electronics.

A typical remote station 1000 is illustrated in block diagrams in FIG. 3. Telephone line 20 is connected to supply an input to a tone receiver 1006 and to receive outputs from tone transmitters 1008, 1010 and 1012. Tone receiver 1006 receives sequential data from central control station 100 cor responding to word-type, function and address information, and the data is supplied to a l6-BIT scanner-receiver 1014 through a lead 1016. Scanner-receiver 1014 converts the sequential data to a l6-B1T parallel output word such that word-type information is supplied on a multiconductor cable 1018, function information is supplied on a multiconductor cable 1020 and address information is supplied on a multiconductor cable 1022 to a remote point interface 1024.

An alarm enable" output 1026 from remote point interface 1024 controls a pair of contacts 1028 which are in series between the output 1030 of tone transmitter 1008 and telephone line 20. An alarm output 1032 from remote point interface 1024 supplies an input to tone transmitter 1008. A control enable output 1034 from remote point interface 1024 controls a pair of contacts 1036 which are in series between the output 1038 of tone transmitter 1010 and telephone line 20. An in-scan output 1040 from remote point interface 1024 is supplied as an input to an eight-BIT scanner-transmitter 1042, which has an output 1044 connected with tone transmitter 1010. Function and address information are supplied from remote point interface 1024 to remote points 1002 on multiconductor cables 1046 and 1048, respectively, and "scan initiation and field alarm input signals are supplied to remote point interface 1024 from remote points 1002 on leads 1050 and 1052, respectively.

An analog signal output 1054 from remote points 1002 is supplied to analog transducers 1056, and a range select out put 1058 from remote points 1002 is supplied as an input to analog transducers 1056 and scanner-transmitter 1042. A contact status" output 1060 from remote points 1002 is supplied as an input to scanner-transmitter 1042.

The analog transducers 1056, which are well known and commercially available, convert analog signals on output 1054 for compatibility with an analog telemetry transmitter 1062 which receives an output 1064 from analog transducer circuit 1056. Analog telemetry transmitter 1062 produces mark and space signals having a frequency of alternations proportional to the analog signals from analog transducers 1056, and mark and space alternations are supplied to tone transmitter 1012 on an output 1066. An output 1068 of tone transmitter 1012 is connected with telephone line through a pair of series contacts 1070 under the control of control enable output 1034.

Tone receiver 1006, scanner-receiver 1014, scannertransmitter 1042, analog telemetry transmitter 1062 and tone transmitters 1008, 1010 and 1012 are all well known and commercially available as model numbers QR-SO, QSR-16, 0ST- 8, GATT-l0 and QT-30, respectively, manufactured by Quin dar Electronics. As previously mentioned with respect to scanner-receiver 122 and scanner-transmitter 146 at central control station 100, the scanner-receiver 1014 and the scannentransmitter 1042 operate to convert infonnation from serial to parallel and from parallel to serial, respectively.

A brief description of the operation of the present invention as thus far described will be presented at this time in order to facilitate an understanding of the more detailed structure of central control station 100 and remote stations 1000.

The equipment at central control station 100 generates signals to remote stations 1000 by means of telephone line 20 and receives, simultaneously, information from remote stations 1000 by means of telephone line 20 or information from local points 22 by means of cable 24. The equipment at central control station 100 is adapted to display, annunciate, log or otherwise communicate information received from the field points, which encompass local points 22 and remote points 1002, to an operator at the central control station.

The equipment at each remote station 1000 receives signals from central control station 100 through telephone line 20 and transmits selectively and as necessary the signals from central control 100 to remote points 1002 through multiconductor cables 1004. Remote stations 1000 receive digital and analog information from remote points 1002 and condition and transmit these signals to central control station 100 by means of telephone line 20.

Activation of any remote station 1000 is accomplished by a uniquely coded address signal generated at central control station 100 and transmitted to all remote stations 1000 simultaneously. Decoding circuitry at each remote station 1000 is responsive only to preassigned address codes; and, thus, it may be seen that the only restriction on the number of remote stations 1000 is the limit of available remote station address codes. Remote points 1002 are selectively referenced by unique individual point address signals generated at central control station 100 and each individual remote point is assigned a unique address within the operating scope of its associated remote station 1000. An individual remote point cannot be referenced unless its associated remote station 1000 has been activated by a previously transmitted remote station address signal from central control station 100.

In a similar manner, local points 22 are selectively referenced by transmission of unique point addresses generated at central control station 100 and each individual local point is selected only if the entire group of local points 22 has been previously activated by transmission of a unique station address code preassigned to local points 22. Both groups of local points 22 and remote points 1002 are a collection of individual field points, and the total number of such field points within each group is limited only by the total number of available field point address codes. The function of each field point may be of any nature as required by monitoring or controlling operations to be performed in the field. For example, some points may transmit analog information such as temperature, pressure, humidity or the like while other points may transmit digital data corresponding to contact closure of off-normal status of equipment such as motor failure or the exceeding of highor low condition limits. Still other points may provide on-off or incremental control of the operation of motors or other equipment. The manner in which information is provided to and acquired from the field points is well known in the art and will not be described in detail.

Information signals from central control station 100 are transmitted in two distinct phases which are referred to as the alarm phase (phase A) and the control phase (phase C). Phase A provides continuous alarm scanning. and phase C controls all other functions of the system, such as analog indication, contact status and control. Central control station continuously transmits blocks of information which will hereafter be referred to as words, each word being alternately associated with phase A or C.

Phases A and C each operate in two distinct sequences which are designated sequence 0 and l, and each sequence transmits half of the complete address of a field point. Sequence 0, which is the hundreds sequence, transmits the address of a remote station 1000. Sequence 1, which is the units sequence, transmits the address of individual points associated with the remote station. Thus, sequence 0 contains the most significant half of the complete address and sequence 1 contains the least significant half of the complete address. It: the preferred embodiment the complete address of a field point includes four binary coded decimal digits of which the two least significant represent the individual point address and the two most significant represent the remote station address. Accordingly, it is desirable to arrange the field points in groups of one hundred for association with remote stations 1000; and, for purposes of ease of description, the remote stations are limited to one hundred in number such that the system can supervise 10,000 field points. Of course, if so desired, the system can be expanded by increasing either the number of field points within a group, the total number of remote stations, or both while increasing the number of binary coded decimal digits in a complete address. The system may also be easily expanded by increasing the address coding system capacity such as by utilizing a pure binary code.

Phase C alternates between sequence 0 and sequence 1 such that each successive word transmitted is of alternate sequences. Since the system alternates between phases, it is seen that the transmission of a complete phase C address requires three word transmissions. That is, a phase C sequence 0 word is transmitted containing the two most significant digits of a point address. There follows the transmission of a phase A word; and, thereafter a phase C, sequence 1 word is transmitted containing the least two significant digits of the point address thereby completing the address.

Phase A does not alternate sequences but normally operates in a sequence 0 mode to transmit a new remote station address with each alarm word transmitted. Thus, the alarm operation of the system is such that the field points at remote stations 1000 and local point group 22 are interrogated as groups for the presence ofa new alarm existing therein. Upon detecting a new alarm, phase A switches to sequence 1 operation and scans all of the field points in the group. Thereafter phase A returns to sequence 0 and continues to interrogate successive remote stations.

It should be noted that with the system of the present invention control phase operations may occur simultaneously with alarm phase operations at different remote stations. However, a phase A, sequence 1 scan at a remote station prohibits control phase operations at that remote station. 11' so desired, control phase and alarm phase operation at individual field points at the same station can be accomplished by separating the field points into subgroups with respect to alarm and control functions.

The words transmitted from central control station 100 are alternated from phase A to phase C, as previously mentioned, such that a continuous scan of the remote stations is provided for alarm conditions. When a remote station being interrogated has a new alarm, tone transmitter 1008 receives an alarm signal from remote point interface 1024 on output 1032 and generates a signal on output 1030 which is supplied to telephone line 20 through contacts 1028 which are closed by an alarm enable signal on output 1026 from remote point interface 1024 when a phase A word is received. A new alarm at a field point supplies a "scan initiation" pulse to remote point interface 1024 on lead 1050 for storage thereat to provide the alarm signal on output 1032 when the remote station is addressed. The alarm signal from tone transmitter 1008 is received at central control station 100 by tone receiver 166 to indicate that an alarm or off-normal condition exists at the remote station. The phase A operation will then be changed to provide phase A, sequence 1 operation to detect the precise field point exhibiting the new alarm by a field alarm" signal on lead 1052 when the field point is addressed.

While alarm scanning is continuously provided, any control operation may be provided during the alternating phase C words. For instance, points may be manually selected at equipment 106 such that an analog value at a specific field point may be interrogated. The phase C sequence word will address the correct remote station, and the phase C sequence 1 word will select the specific field point 1002, whereupon a signal will be provided on telephone line from analog transducers 1056. analog telemetry equipment transmitter 1062 and tone transmitter 1012, which signal is received at central control station 100 by tone receiver 176 and applied to peripheral analog indication equipment 126 through analog telemetry receiver 128. At the same time, a range select signal will be provided at remote points 1002 and supplied to analog transducers 1056 to permit proper response to signals on lead 1054. The range select" signal is transmitted to central control station 100 through scanner-transmitter 1042 and tone transmitter 1010, and is received by tone receiver 172 and applied to peripheral analog indication equipment 126. In a similar fashion any point may be operated in accordance with a program through control scan address generator 112.

Control functions at remote points 1002 may be operated by manually selecting a point at point selection equipment 106 and a function at control function equipment 110 such that a phase C, sequence 0 word transmitted by central control station [00 addresses the remote station 1000 containing the selected remote point. The phase C, sequence 1 word contains the address of the selected point and also function information to start or stop a motor, increase or decrease the speed of a motor, or otherwise operate equipment at the remote point.

In order to determine the status of any selected points or all points in the system, signals may be transmitted at central control station 100 in the manner previously described such that the status of a pair of contacts associated with the points can be determined from output 1060 from remote points 1002 through scanner-transmitter 1042 and tone transmitter 1010 at remote stations I000. The contact status signals are received at central control station 100 by tone receiver 172 and transmitted through scannevreceiver 122 to peripheral annunciation equipment 116.

SEQUENCE CONTROL CIRCUIT The sequence control circuit 102 at central control station 100 is illustrated in FIG. 4 and includes a clock and sequence select circuit 200 which receives synch pulses on lead 164 from scanner-transmitter 146. Clock and sequence select circm! 200 prmides outputs on four multiconductor cables 202, 204. 206 and 208 corresponding to phase A, sequence 0, phase A. sequence 1, phase C, sequence 0 and phase C, sequence 1 signals, respectively.

Multiconductor cable 202 supplies phase A, sequence 0 signals to a sequence logic circuit 300 for alarm hundreds, and sequence logic circuit 300 provides an output 302 to a transmission register circuit 700 on a multiconductor data bus 702 and an output 304 to an input 210 of clock and sequence select circuit 200 indicating a change of sequence. Muticonductor cable 204 supplies phase A, sequence 1 signals to a sequence logic circuit 400 for alarm units, and sequence logic circuit 400 supplies an output 402 to transmission register circuit 700 on data bus 702 and an output 404 to input 210 of clock and sequence select circuit 200 indicating a change of sequence Alarm signals on leads 168 and 170 are supplied to sequence logic circuits 300 and 400 at inputs 306 and 406, respectively. Cable 118 supplies an output from sequence logic circuit 400 to peripheral annunciation equipment 116.

Multiconductor cable 206 supplies phase C, sequence 0 signals to a sequence logic circuit 500 for control hundreds,

and sequence logic circuit 500 supplies an output 502 to transmission register circuit 700 on data bus 702. Sequence logic circuit 500 also receives signals corresponding to address hundreds and functions on inputs 504 and 506, respectively, from control. address and function signal source 115. Source receives in-scan" signals on leads 142 and 144 from local point interface and scanner-receiver 122, respectively. Multiconductor cable 208 supplies phase C. sequence 1 signals to a sequence logic circuit 600 for control units, and sequence logic circuit 600 supplies an output 602 via data bus 702 to transmission register circuit 700. Sequence logic circuit 600 receives signals from source 115 on inputs 604 and 606 corresponding to address units and functions, respectively.

Transmission register circuit 700 supplies word-type, function and address information on cables 148 and 154, 150 and 156, and 152 and 158 to scannertransmitter 146 and remote point interface 140, respectively.

The basic circuit elements shown in the remaining drawings will not be described in detail since they are well known in the art and a brief description thereof is presented at this time to facilitate an understanding of the present invention. The AND gates produce a true output only when all inputs are true. The NAND gates produce a false output only when all inputs are true. The OR gates produce a true output when any input is true. The set-reset flip-flops are bistable multivibrators requiring false switching inputs. The JK flip-flops are bistable multivibrators which require false control inputs but which do not change state until after application and removal of a gating pulse. The toggle flip-flops are bistable multivibrators which change state each time a gating pulse is removed therefrom. A small circle at the input of any of the basic circuit elements above described indicates inversion of the input applied thereat.

The clock and sequence select circuit 200 is illustrated in FIG. 5 and includes a toggle flip-flop T1 having an input 212 receiving synch signals on lead 164. A first output 214 from flip-flop TI supplies phase A signals as inputs to three-input AND-gates A1 and A2 A second output 216 from flip-flop T1 supplies phase C signals as inputs to three-input AND-gates A3 and A4 as well as to an input 218 ofa toggle flipflop T2. A first output 220 of flip-flop T2 supplies phase C, sequence 0 signals as an input to gate A3, and a second output 222 supplies phase C, sequence 1 signals as an input to gate A4. A toggle flip-flop T3 receives sequence change" signals on input 210 from outputs 304 and 404 of sequence logic circuits 300 and 400, respectively, and has an output 224 providing phase A, sequence 0 signals to gate A1 and an output 226 supplying phase A, sequence 1 signals to gate A2. The third input to gates Al, A2. A3 and A4 is received from a common lead 228.

The synch signals on lead 164 are also supplied to a delay circuit 230, which may include two monostable multivibrators connected in series to delay the synch pulses for a period of time sufficient to allow for the transmission of an alarm signal from any one of the remote stations 1000 to central control station 100. The output of delay circuit 230 is supplied as one input of a two-input AND-gate A5 which receives its second input from an output 232 of an astable multivibrator 234.

The output from gate A5 is connected with a gate input 236 of a JK flip-flop 1K1 Flip-tlop 1K1 also receives synch" signals from lead 164 on a gate input 238 and receives cornplementary inputs 240 and 242 on a lead 244. An output 246 of flip-flop 1K1 is supplied as one input to a two-input AND gate A6 which receives a second input from the output 232 of astable multivibrator 234. The output of gate A6 provides clock signals to lead 228 and an input 248 of a binary counter 250. The output of gate A6 is also connected to a gate input 252 offlip-flop .lKl.

Binary counter 250 includes three toggle flip-flops T4, T5 and T6, each of which receives synch" signals from lead 164 at resetting gate inputs 254, 256, and 258, respectively. A first output 260 of flip-flop T4 is connected with a binary-to-octal converter 262, and a second output 264 of flip-flop T4 is connected with converter 262 and as an input to flip-flop T5. Outputs 266 and 268 of flip-flop T5 supply inputs to converter 262, and output 268 further provides an input to flipflop T6. Outputs 270 and 272 of flip-flop T6 supply inputs to converter 262. Converter 262 has eight outputs 274, 276, 278, 280, 282, 284, 286 and 288 which receive pulses from converter 262 corresponding to operation cycles through 7, respectively. Each of the outputs 274 through 288 provides an input to each of transfer gates 290, 292, 294 and 296.

Transfer gates 290, 292, 294 and 296 are identical; and, accordingly, only the structure of gate 290 is illustrated and described hereafter. Transfer gate 290 includes eight twoinput ANDgates A7, A8, A9, A10, A11, A12, A13 and A14 which receive as one of their inputs the cycle signals on outputs 274, 276, 278, 280, 282, 284, 286 and 288, respectively. The other inputs to each of the AND gates in transfer gate 290 receive the output of gate A]. In a similar fashion the cycle 0 through cycle 7 signals are applied to each of the two-input AND gates in transfer gates 292, 294 and 296, and the second input to the AND gates in each of transfer gates 292, 294 and 296 are received from the outputs of gates A2, A3 and A4, respectively. The outputs from the AND gates in transfer gate 290 correspond to phase A, sequence 1 signals coinciding with cycles 0 through 7 and are applied to sequence logic circuit 300 on cable 202 as shown in FIG. 4. The outputs from transfer gate 292 correspond to phase A, sequence 1 signals coinciding with cycles 0 through 7 and are applied to sequence logic circuit 400 on cable 204. Similarly, the outputs from transfer gate 294 provide phase C, sequence 0 signals coinciding with cycles 0 through 7 and are applied to sequence logic circuit 500 on cable 206, and the outputs from transfer gate 296 provide phase C, sequence 1 signals coinciding with cycles 0 through 7 and are applied to sequence logic circuit 600 on cable 208. For purposes of simplicity, the individual outputs from transfer gates 290, 292, 294 and 296 are identified by phase, sequence and cycle indicia in that order. For instance, the output from gate A12 is indicated A-0-5; that is, phase A, sequence 0, cycle 5.

Sequence logic circuit 300 which receives phase A, sequence 0 cycle signals on cable 202 from transfer gate 290 in clock and sequence select circuit 200 is illustrated in FIG. 6. Alarm signals from leads 168 and 170 are received at input 306 and are applied in complementary fashion to inputs 308 and 310 of a JK flip-flop JK2 which has a gate input 312 receiving output A0-5 from transfer gate 290. If an alarm signal is received at input 306, a true signal appears on input 308 to change the state of (2 to provide a true output at 314 when gate input 312 receives the A-05 signal. The output 314 is supplied as one input of a two-input AND-gate A15 which receives a second input from the A-0-6 output from transfer gate 290, The complementary output 316 of flip-flop JK2 is supplied as one input to a two-input AND-gate A16 which receives a second input from the A-0-6 output from transfer gate 290. Thus, an alarm signal from the field is detected during cycle and is passed by gate A after receipt of output A- 0-6 to provide a sequence change" output on lead 304 which is returned to flip-flop T3 at clock and sequence select circuit 200, as shown in FIG, 5. If no alarm signal is present, a true signal on output 316 of flip-flop JK2 is passed by gate A16 to an input 318 ofa counter 320 upon receipt ofoutput A-0-6.

Counter 320 includes two decimal counter stages 322 and 324, each of which provides four outputs 326, 328, 330 and 332, and 334, 336, 338 and 340, respectively, with output 332 of stage 322 providing an input 342 to stage 324 such that the outputs indicate two binary coded decimal digits corresponding to the most significant half of the address of a field point. That is, the outputs from counter 320 provide the address ofa remote station 1000 in hundreds.

A plurality of two-input AND-gates A17-A31 each receive a first input from output A-0-7 from transfer gate 290. Gates A17. A18 and A19 have second inputs 344, 346 and 348 cor responding to word-type parity, phase and sequence, respectively. The word-type data on inputs 344, 346 and 348 does not change; and, accordingly. the inputs may be selectively grounded such that phase A is indicated by a false, sequence 0 is indicated by a false and word-type parity is indicated by a true. Gates A20, A21, A22 and A23 have second inputs 350, 352, 354 and 356 corresponding to function data with input 350 providing function parity. The function data may be utilized in any desirable manner during phase A operation since it is not required for alarm scanning. Gates A24, A25, A26, A27, A28, A29, A30 and A31 receive outputs 326, 328, 330, 332, 334, 336, 338 and 340 from counter 320, respectively, corresponding to the address of a remote station 1000. The outputs of gates Al7-A31 provide data for forming BlTs 0-6, and 8-15 of a word to be forwarded to transmission register circuit 700 via data bus 702; and, to facilitate an understanding of the present invention, the outputs ofgates A17-A31 are identified by BIT numbers.

Sequence logic circuit 400 is illustrated in FIG. 7 and receives phase A, sequence 1 cycle signals on cable 204 from transfer gate 292 of clock and sequence select circuit 200. The hold signals from peripheral annunciation equipment 116 on lead 124 are supplied in complementary fashion at inputs 408 and 410 of a JK flip-flop 1K3 which receives output A-1-0 from transfer gate 292 at a gate input 412. The "hold" signals are generated by the peripheral annunciation equipment in order to cause sequence logic circuit 400 to retransmit the previously transmitted word. The ho|d" signals are true such that when a hold signal is generated, flip-flop JK3 will place a false on output 414 thereof when gated by output A-1-0. Thus, "hold" signals are interrogated during cycle 0 of phase A, sequence 1 operation. Output 414 of flip-flop JK3 supplies an input to each of three-input AND-gates A32 and A33 and a four-input AND-gate A34, which input is true unless a hold signal is present on lead 124.

Alarm signals from leads 168 and 170 are received at input 406 and are supplied as one input of a two-input AND-gate A35 which has its output supplied in complementary fashion to inputs 416 and 418 of a JK flip-flop 1K4. Flip-flop 1K4 receives output A-l-l from transfer gate 292 at a gate input 420, and outputs 422 and 424 of flip-flop 1K4 supply inputs to gates A32, and A33 and A34, respectively. Thus, alarm signals are interrogated during cycle 1 of phase A, sequence 1 operation; and, if an alarm signal is present and the output 426 of a set-reset flip-flop RS1 is true, gate A35 generates a true signal to place a true on output 422 of flip-flop JK4 when output A- 1-1 is passed by transfer gate 292. Trues on outputs 414 and 422 of flip-flops JK3 and JK4, respectively, along with output A-1-2 from transfer gate 292 enable gate A32, and the output from gate A32 is supplied as an annunciation signal to peripheral annunciation equipment 116 through cable 118 and is inverted at an input 428 to flip-flop RS1,

Gate A33 receives as a third input output A-1-2 from transfer gate 292, and the output of gate A33 is inverted at an input 430 to flip-flop RS1 which has an output 432 providing an acknowledge pulse. The output of gate A33 is also supplied as an input 434 to a point address counter 436 including two decade counter stages 438 and 440 having binary outputs 442, 444, 446 and 448, and binary outputs 450, 452, 454 and 456, respectively, corresponding to the two least significant decimal digits of the address of a field point. Output 448 of stage 438 supplies an input 458 to stage 440. Outputs 442, 444, 446, 448, 450, 452, 454 and 456 are inverted at the inputs of an eight-input AND-gate A36 such that gate A36 provides a true output in complementary fashion to inputs 460 and 462 of a JK flip-flop (5 when each of the counter outputs is false indicating the completion of a scan of the remote points 1002 at a remote station 1000.

Flip-flop (5 receives output A-1-3 from transfer gate 292 at a gate input 464 to interrogate the output from gate A36 and provide a true signal on output 466 when the output of gate A36 is true. Output 466 supplies an input to gate A34 which also receives an input from output A-l-4 from transfer gate 292 to interrogate point scan completion on cycle 4 of phase A, sequence 1 operation when the outputs 414 and 424 of flip-flops JK3 and 1K4, respectively, are true. The output of gate A34 supplies a sequence change" signal on output 404 to input 210 of clock and sequence select circuit 200.

A plurality of two-input AND-gates A37-A51 each receive a first input from output A-1-7 from transfer gate 292. Gates A37, A38 and A39 have second inputs 468, 470, and 472 corresponding to word-type parity, phase and sequence, respectively. Since the word-type data on inputs 468, 470 and 472 does not change, the inputs may be selectively grounded such that phase A is indicated by a false, sequence 1 is indicated by a true and word-type parity is indicated by a false. Gates A40 and A41 receive second inputs from outputs 426 and 432 of flip-flop RS1 corresponding to function parity and acknowledge function, respectively. Gates A42 and A43 have second inputs 474 and 476 receiving false function signals, respectively. Gates A44, A45, A46, A47, A48, A49, A50 and A51 receive outputs 442, 444, 446, 448, 450, 452, 454 and 456 from counter 436, respectively, corresponding to the address of an individual point at a remote station 1000. The outputs from gates A37-AS1, which are identified by BIT numbers, provide data for forming BITs -5 and 8-15 ofa word to be forwarded to transmission register circuit 700 via data bus 702.

Sequence logic circuit 500 is illustrated in FIG. 8 and includes a plurality of two-input AND-gates A52-A66 each of which receives an input from output C-0'7 from transfer gate 294 of clock and sequence select circuit 200. Gates A52, A53 and A54 have inputs 508, 510 and 512 corresponding to word-type parity, phase and sequence, respectively. Since the word-type data on inputs 508, 510 and 512 does not change, the inputs may be selectively grounded such as phase C is indicated by a true, sequence 0 is indicated by a false, wordtype parity is indicated by a false. Gates A55, A56, A57 and A58 have inputs 514, 516, 518 and 520 corresponding to functions with input 514 corresponding to function parity. Gates A59, A60, A61, A62, A63, A64, A65 and A66 have inputs 522, 524, 526, 528, 530, 532, 534 and 536, respectively, corresponding to the two most significant digits of an address of a field point; that is, the digits corresponding to a remote station 1000. The address inputs are received from source 115; and, similarly, functional data on inputs 514, 516, 518 and 520 are received from source 115. The outputs of gates A52-A66, which are indicated by BIT numbers, provide BITS 0-6 and 8-15 of a word to be forwarded to transmission register circuit 700 via data bus 702.

Sequence logic circuit 600 is illustrated in FIG. 9 and includes a three digit data register 608 having two-input NAND- gates N 1N6 each of which receives one input from the output of an OR gate 01. Gate N1 receives a second input from output 264 of cycle counter 250 of clock and sequence select cir cuit 200, and the output of gate N1 is supplied to a second input of gate N2 and to an input 610 of a set-reset flip-flop RS2 which has another input 612 receiving the output from gate N2. Gate N3 receives a second input from output 268 of cycle counter 250. and the output of gate N3 is supplied to a second input of gate N4 and to an input 614 ofa set-reset flipflop RS3 hich has another input 616 receiving the output from gate N4. Gate N receives a second input from output 272 of cycle counter 250. and the output of gate N5 is supplied to a second input ofgate N6 and to an input 618 ofa setreset flip-flop RS4 which has another input 620 receiving the output from gate N6.

Gate 01 receives inputs from output C-l-0 of transfer gate 296 and two-input AND-gates A67-A73. Gates A67, A68, A69. A70, A71, A72 and A73 receive inputs from outputs C- l-l, C-l-Z, C-1-3, C-l4,C-1-5,C-1-6, and C-1-7, respectively, and outputs 622, 624, 626, 628, 630, 632 and 634 from source 115, which outputs provide function data corresponding to control functions to be accomplished in the field.

A plurality of two-input AND-gates A74 through A88 each receive an input from output C-1-7 from transfer gate 296. Gates A74. A75 and A76 have inputs 636, 638 and 640 receiving word identification data corresponding to word-type parity. phase and sequence, respectively, all ofwhich are true.

Gates A77, A78, A79 and A80 have inputs 642, 644, 646 and 648, respectively; and inputs 644, 646 and 648 receive out puts 650, 652, and 654 from flip-flops RS2, RS3, and RS4, respectively. Outputs 650, 652 and 654 are also supplied as an input to a conventional parity generator 656 comprised of NAND gates, which parity generator has an output 658 supplying function parity information to input 642 of gate A77. Parity generator 656 receives information corresponding to functions on outputs 650, 652 and 654 and provides a pulse at output 658 such that the number of true signals in the function inputs provided to gates A77 through A80 is an odd number.

Gates A81, A82, A83, A84, A85, A86, A87 and A88 have inputs 660, 662, 664, 666, 668, 670, 672 and 674, respectively, for receiving address signals corresponding to individual points at a remote station 1000, which address signals are generated by source 115.

The output of data register 608 provides a code for a function to be transmitted and stores information gathered from gates A67-A73 as they sequentially interrogate inputs 622, 624, 626, 628, 630, 632 and 634 with cycle operation. That is, a true function signal is gated through gates A67-A73 and gate 01 to register 608 where it is stored. Register 608 is cleared during cycle 0 of phase C, sequence 1 operation.

Transmission register circuit 700 is illustrated in FIG. 10 and receives BITs 0-6 and 8-15 on data bus halves 702a and 702b, respectively, as transmitted from sequence logic circuits 300, 400, 500 and 600 during cycle 7 of either phase and sequence operation. Circuit 700 includes a next word register 704 and a current word register 706. Registers 704 and 706 are identical; and, accordingly, only register 704 will be described.

Register 704 includes set-reset flip-flops RSS-RS20 and two-input NAND-gates N7-N38 each of which receives a cycle 7 input on output 288 from converter 262 of clock and sequence select circuit 200. Gates N7, N9, N11, N13, N15, N17 and N19 have inputs connected with wires of data bus 702 corresponding to BITs 06, respectively; and gates N23, N25, N27, N29, N31, N33, N35 and N37 have inputs con nected with wires of data bus 702 corresponding to BlTs 8-15. The output of gate N7 is connected with an input to gate N8, and the outputs of gates N7 and N8 are connected with inputs of flip-flop RS5 which has an output 708 supplying BIT 0 data register 706. In a similar manner BIT 1 through BIT 15 information is supplied by outputs 710, 712, 714, 716, 718, 720, 722, 724, 726, 728, 730, 732, 734, 736 and 738 from flip-flops RS6-RS20, respectively, to corresponding stages of register 706.

The address data of BlTs 8-15 are supplied from bus 702 to conventional parity generator 740 comprised of NAND gates which produces an output at 742 to gate N21 assuring that the number oftrue signals in the nine-BlT address code is odd.

During cycle 7 of any phase and sequence, the information on data bus 702 is gated into flip-flops RS5RS20 of register 704 along with the address code parity of BIT 7. Upon the receipt of a "synch" pulse on lead 164 the information is transferred from register 704 to register 706 where the out puts corresponding to BITS 0 through 15 are scanned serially by scanner-transmitter 146 and applied through lead 162 to tone transmitter 160 for communication to the field through telephone line 20.

REMOTE AND LOCAL POINT INTERFACE A typical circuit for use as a remote point interface 1024 or local point interface is illustrated in FIG. 11. The information on telephone line 20 is received by tone receiver 1006 and supplied to scanner-receiver 1014 at remote stations 1000 such that the 16-BIT words are supplied to remote point interface 1024 in three groups, 1018, 1020 and 1022, correspond ing to word-type identification, function and address. Local point interface 140 receives signals corresponding to wordtype, function and address directly from sequence control circuit 102 on multiconductor cables 154, 156 and 158, respectively.

BlTs 0, 1 and 2 correspond to word-type identification and are supplied as inputs to a word decoder 1072 including threeinput AND-gates A89, A90, A91 and A92. BIT is inverted as applied to gates A90 and A91, and BIT 1 is inverted as applied to gates A89 and A91. BIT 2 is inverted as applied to gates A89 and A90, and gate A92 receives all three BlTs in noninverted fashion. The outputs 1074, 1076, 1078 and 1080 of AND gates A89 through A92, respectively, thus present a decoded indication of the word-type being transmitted.

BlTs 3, 4, 5 and 6 correspond to the function code and are decoded at a function decoder 1082 by application in selected inverted form to five-input AND-gates A93 through A99. The outputs of gates A93 through A99 represent the decoded function of the transmitted word and are applied to remote point 1002 on multiconductor cable 104-6.

BlTs eight through 15, which correspond to the address, are applied to a parity generator 1083 identical to parity generator 740 having an output 1084 which is applied as a first input to two-input NAND-gates N39 and N40. The other input of gate N39 receives address parity information on BIT 7, which information is also applied as a first-input of a two-input NAND-gate N41. The second inputs of gates N40 and N41 are received from the output of gate N39, and outputs of gates N40 and N41 are applied as an input to a nine-input address decoding AND-gate A100. The output of NAND-gates N40 and N41 is true only if the parity pulse of BIT 7 corresponds with BlTs 8 through such that an odd number of true pulses are presented. That is, parity BIT 7 must be the same as the output 1084 of parity generator 1083 to enable gate A100 and activate a given remote station 1000.

BlTs eight through 15 are applied as inputs to gate A100 and inverted in such a manner that gate A100 is enabled only when the unique address of that remote station is represented in the transmitted word. For example, gate A100, as illustrated, will be enabled only when the binary decimal address 76 is transmitted. The output of gate A100 is thus true only when the address code of BlTs eight through 15 matches the preassigned address code for that remote station and if parity BlT 7 matches the output 1084 of parity generator 1083.

Address BlTs eight through 15 are also supplied to a point address register 1086 which includes set-reset flip-flops R521 through R828. A plurality of two-input NAND-gates N42 through N57 are arranged in pairs to cooperate with flip-flops R521 through RS28 in the same manner as previously described with respect to register 704 of FIG. 10, and each of the gates N42 through N57 receives an input from a two-input AND-gate A101. The other inputs to gates N42, N44, N46, N48, N50, N52, N54 and N56 receive address BlTs 8 through 15, respectively. Outputs 1088, 1090, 1092, 1094, 1096, 1098, 1100 and 1102 from flip-flops R521 through RS213, respectively, represent the address of an individual point in binary code. If the remote points are arranged in matrices, it may be desired to convert the binary code to decimals as is well known in the art.

The output of gate A100 is supplied as one input to twoinput NAND-gates N58 and N59. A second input of NAND- gate N58 receives output 1078 of gate A91 of word decoder 1072, and a second input of gate N59 receives output 1074 of gate A89. A two-input NAND-gate N60 receives inputs from outputs 1078 of gate A91 and the output of gate N58 and supplied an output to an input 1104 of a set-reset flip-flop R829 which has an input 1106 receiving the output from gate N58 and an output 890 providing a control enable" signal on lead 1034 to control contacts 1036 and 1070.

A two-input NAND-gate N61 has a first input receiving output 1074 of gate A89 and a second input receiving the output of gate N59. The output of gate N61 is supplied to an input 1110 of a set-reset flip-flop R830 which has an input 1112 receiving the input of gate N59 and an output 1114 providing an alarm enable" signal on lead 1026 to control contacts 1028.

Output 11 14 of flip-flop R530 is supplied as a first input of a two-input AND-gate A102 which receives a second input from gate A90 of word decoder 1072. The output of gate A102 is supplied to a five-input AND-gate A103 which receives BlTs 3-6 as the other four inputs, and the output of gate A102 is inverted at an input 1116 of a set-reset flip-flop R531. Another input 1118 of flip-flop R831 inverts output 1074 of gate A89, and an output 1120 of flip-flop R831 provides an "in-scan signal on lead 1040 while an output 1122 supplies a signal to a three-input AND-gate A104. A second input to gate A104 is received from output 1108 of flip-flop RS29, and a third input to gate A104 receives output 1080 from gate A92 of word decoder 1072. The output of gate A104 is supplied as an input to each of gates A93 through A99 of function decoder 1082 and to a two-input OR-gate 02. The other input of gate 02 receives the output from gate A102. The output of gate 02 supplies an input to gate A101 which receives another input from the output of gates N40 and N41. A monostable multivibrator 1124 receives an "in-scan" input from output 1120 of flip-flop R831 and supplies an output to an input 1126 of a set-reset flip-flop RS 32 which has another input 1128 receiving a scan initiation signal on lead 1050 from remote points 1002. An output 1130 of flip-flop RS 32 supplies a first-input to a two-input NAND-gate N62 which receives its other input from output 1074 of gate A89 of word decoder 1072. The output of gate N62 is supplied to an input 1132 of a set-reset flip-flop RS33 along with the output from a three-input NAND-gate N63 which receives a first input from the output of gate A103, a second input from output 1076 of gate A and a third input receives "field alarm" signals from remote points 1002 on lead 1052. Two-input NAND-gates N64 and N65 each have their outputs connected to an input 1134 of flip-flop RS33. A first input of gate N64 receives output 1076 of gate A90, and the second input of gate N65 inverts the "field alarm" signal on lead 1052. An output 1136 of flip-flop RS33 provides an alarm" signal to tone transmitter 1008 on lead 1032.

OPERATION Operation of the supervisory control system of the present invention will be described with reference to FIG. 12 which is timing chart of basic signals generated during operation of the system.

A synch" pulse 1200 is generated at central control station by scanner-transmitter 146 at the beginning of the scan of a word in register 706 of transmission register circuit 700. The generation of each synch" pulse 1200 initiates operative cycles at times l,-t, since the synch" pulses synchronize the clock and sequence select circuit 200.

With reference to FIG. 5, the "synch" pulses 1200 are received at clock and sequence select circuit 200 on lead 164 and are supplied at input 212 to flip-flop T1 to cause it to change states with each synch" pulse 1200. The outputs 214 and 216 of flip-flop T1 correspond to phase A and phase C outputs indicated at 1202 and 1204 in FIG. 12, respectively; and gates A1 and A2, which control phase A hundreds and units operations, can be enabled only when output 214 of flipflop T1 is true. Similarly, gates A3 and A4, which control phase C hundreds and units operations, can be enabled only when output 216 of flip-flop T1 is true. Thus, phase A and phase C operations are sequentially alternated with the changing of states of flip-flop T1 in accordance with synch pulses 1200 such that the operative cycles beginning at times 1,, 1,, r, and r correspond to phase A operation and the operative cycles beginning at times r,, r, and 1 correspond to phase C operation.

"Synch" pulses 1200 are also supplied to gate A5 after sufi'lcient delay at 230 along with the output 232 of astable multivibrator 234 such that alter the delay gate A5 is enabled to supply a false after inversion to gate input 236 of flip-flop 1K1 to trigger the flip-flop and place a true on output 236 thereof. Gate A6 is thereby enabled to pass clock pulses 1206 which are supplied as inputs to gates A1, A2, A3 and A4. The clock pulses 1206 are also supplied to cycle counter 250 which supplies its binary outputs to converter 262 to provide cycle 0 cycle 7 signals indicated as 1208, 1210, 1214, 1216, 1218, 1220, 1222 and 1224, respectively. Cycle is normally true and is false only until counter 250 returns to its normal state after the eight clock pulses 1206. Cycle 7 signal 1224 is supplied to inputs 240 and 242 of flip-flop (I over lead 244 to return the flip-flop to its normal state on the trailing edge of the last clock pulse 1206 passed by gate A6 and applied to input 252 of flip-flop JK1. Flip-flop .lKl remains in its normal state with a false on output 246 until the next "synch" pulse 1200 is received after the delay at 230. Should a succeeding synch pulse 1200 be generated by scanner-transmitter 146 during cycle operation, the synch pulse will reset counter 250 at inputs 254, 256 and 258 and reset flip-flop JKl at input 238 such that sequence and control circuit 200 will proceed to generate cycle signals for the next word without finishing the word in progress. This reset action also assures that counter 250 and flip-flop JKl are reset after completion of normal cycle generating operation. 6

The cycle signals are each supplied to transfer gates 290, 292, 294 and 296 for transmission to sequence logic circuits 300, 400, 500 and 600 when gates Al, A2, A3 and A4 are enabled. Flip-flop T3 controls the enabling of gates A1 and A2 in accordance with sequence change signals on input 210 from outputs 304 and 404 of sequence logic circuits 300 and 400, respectively. In its normal state output 224 of flip-flop T3. which corresponds to phase A, sequence 0 signals 1226, is true such that gate A1 is enabled when output 214 of flip-flop T1 is true and clock pulses 1206 are passed by gate A6. Thus, phase A operation will be at sequence 0 to scan remote stations 1000 sequentially for the existence of a scan initiation signal indicating that a point in a remote point group has an alarm or off-normal condition. If a remote station 1000 has received a scan initiation signal, a "sequence change" signal will be generated by sequence logic circuit 300 to toggle flipflop T3 to place a true on output 226 thereof, which corresponds to phase A, sequence 1 signals 1228, to enable gate A2 during phase A operation to pass cycle signals through transfer gate 292 to sequence logic circuit 400 to scan the remote points at the remote station that received the scan initiation signal. Once the units scan is completed, sequence logic circuit 400 generates a "sequence change signal to toggle flip-flop T3 such that output 224 is true again.

Each phase C signal from output 216 of flip-flop T1 is received at input 218 of flip-flop T2 to toggle the flip-flop. Output 220 of flip-flop T2 corresponds to phase C, sequence 0 signals 1230 and enables gate A3 when true to permit transfer gate 294 to pass cycle signals to sequence logic circuit 500. Output 222 of flip-flop T2 corresponds to phase C, sequence 1 signals 1232 and enables gate A4 when true to permit transfer gate 296 to pass cycle signals to sequence logic circuit 600.

The cycle signals from transfer gate 290 are supplied to sequence logic circuit 300 on cable 204; and, while only signals A-O-S, A-ll-6 and A-0-7 are illustrated as utilized in FIG. 6, it is clear that the remaining cycle signals can be utilized to provide other functions as desired. [f alarm signals 1234 are present on input 306 from leads 168 and 170, flipflop JK2 will be triggered with a signal A-0-5 such that output 314, which is normally false in the absence of an alarm signal, will be true and output 316, which is normally true in the absence of an alarm signal, will be false. The true on output 314 enables gate A15 with signal A-(l-6 to provide a sequence change" signal on output 304 to flip-flop T3 in sequence and control circuit 200 to change from phase A, sequence 0 operation to phase A, sequence 1 operation as previously described. Counter 320 will not be pulsed if an alarm signal is received; and, consequently. once the phase A, sequence I scan is completed the next remote station 1000 will be interrogated with the next phase A, sequence 0 word. As may be seen from the operation cycle commencing at 6:, an alarm signal 1234 from the field is received within the delay provided at 230 to permit detection of the alarm signal during cycle operation at sequence logic circuit 300.

If no alarm signal is received prior to output A-0-5, the true on output 316 of flip-flop JK2 enables gate A16 with signal A- 0-6 to supply a pulse to input 318 of counter 320 and address the next remote station 1000. Constant word-type and function data is applied to gates Al7-A23 and the address data from counter 320 is applied to gates A24-A31. Upon receipt of signal A-0-7 Blls 0-6 and 0-15 of a word are formed by the enabling of gates A17-A31, and the word is received and stored in register 704 of transmission register circuit 700. Thus, during the alarm phase of operation remote stations 1000 are successively and continuously interrogated for alarm conditions existing at the group of remote points 1002 associated therewith; and, once a remote station having an alarm condition is detected, the individual field points at the remote station are scanned to determine the precise field point exhibiting the alarm condition.

Sequence logic circuit 400 provides phase A, sequence 1 words for scanning the individual field points at a remote station which has received a scan initiate signal and receives cycle signals from transfer gate 292 on cable 206. While only signals A-1-0, A-1-1, A-1-2, A-1-3, A44 and A-1-7 are illustrated as utilized in FIG. 7, it is clear that the remaining two cycle signals can be utilized to provide other functions as desired. If a "hold" signal is received from peripheral annunciation equipment 116 on lead 124, flip-flop (3 is triggered with signal A-1-0 to place a false on output 414 to inhibit operation of gates A32, A33 and A34 and cause the previously transmitted phase A, sequence 1 word to be retransmitted. If no "hold" signal is received, output 414 of flip-flop JK3 will remain true.

Alarm signals from leads 168 and 170 are received at input 406 to enable gate A35 when output 426 of flip-flop RS1 is true due to the lack of an annunciate signal applied to input 428 of the flip-flop. The alarm signal is passed by gate A35 to trigger flip-flop 1K4 with signal A-1-1 and place a true on output 422 and a false on output 424. The true on output 422 along with the true on output 414 of flip-flop (3 enables gate A32 with signal A-l-2 to provide an annunciate signal on cable 118 which is supplied to peripheral annunciation equipment 116. The annunciate signal at the output of gate A32 is supplied to flip-flop RS1 to cause output 426 thereof to be false and output 432 to be true to provide an acknowledge pulse for transmission to the remote stations as BlT4 of a hase A, sequence 1 word. The false on output 424 of flip-flop JK4 inhibits the operation of gates A33 and A34.

If no alarm or hold signals are received by sequence logic circuit 400, flip-flop JK4 will have a true on output 424 and a false on output 422 to inhibit annunciation gate A32. The true on output 424 and the true on output 414 of flip-flop JK3 enable gate A33 with signal A-1-2 to pulse counter 436 and to assure that flip-flop RS1 is set to remove any acknowledge signal therefrom. Counter 436 counts from 0 to 99 in binary coded decimal fashion such that the outputs thereof, when the counter returns to zero, enable gate A36 to trigger flip-flop JK5 with signal A-1-3. The output 466 of flip-flop JKS will be true along with output 414 of flip-flop JK3 and output 424 of flip-flop JK4 to enable gate A34 with signal A-l-4. Thus, sequence log'c circuit 400 functions to address each point in a group at a remote station sequentially while detecting an alarm condition at any of the points, Once a scan of the points is completed such that counter 436 returns to zero, gate A36 is enabled to enable gate A34 to provide a sequence change" signal on output 404 which is supplied to sequence and control circuit 200 at input 210 at cycle 4 to trigger flip-flop T3 and permit the formation of a phase A, sequence 0 word during cycles 5-7.

Constant word-type and function data is applied to gates A37-A43 with the exception of the presence of an acknowledge signal at gate A41, and the address data from counter 436 is applied to gates A44-A51. Upon receipt of signal A-1-7, BITs 0-6 and 8-15 of a phase A, sequence 1 word are formed by the enabling of gates A37-A51, and the word is received and stored in register 704 of transmission register circuit 700.

The cycle signals from transfer gate 294 are supplied to sequence logic circuit 500 on cable 206; and, while only signal C--7 is illustrated as utilized in FIG. 8, it is clear that the remaining cycle signals can be utilized to provide other functions as desired. Constant word-type data is applied to gates A52, A53 and A54, and function data is applied to gates ASS-A58 on lead 506 from source 115. Address data corresponding to the most significant half of the address of a point is applied to gates A59-A66 on cable 504 from source 115. Upon receipt of signal C-0-7, BlTs 0-6 and 8-15 of a phase C, sequence 0 word are formed by the enabling of gates A52-A66, and the word is received and stored in register 704 of transmission register circuit 700.

The cycle signals from transfer gate 296 are supplied to sequence logic circuit 600 on cable 208 to control the storage of function signals in register 608. Signal C-1-0 clears register 608, and function signals on input 606 from source 115 are supplied to inputs 622, 624, 626, 628, 630, 632 and 634 for gating to register 608 through gate 01 by gates A67-A73 which receive cycle signals C-1-1 through C-1-7. Outputs 264, 268 and 272 from counter 250 at clock and sequence select circuit 200 are supplied to register 608 to control the storage of function information therein. Constant word-type data is supplied to gates A74, A75 and A76, and function parity data is supplied to gates A77 from the output 658 of a parity generator 656 which receives inputs from the outputs 650, 652 and 654 of register 608. The function parity data will be such that the number of trues on function BlTs 3-6 is odd. Outputs 650, 652 and 654 of register 608 are also supplied to gates A78, A79 and A80 to complete the function data. Address data is supplied to gates A81-A88 on input 604 from source 115. Upon receipt of signal C-l-7 BlTs 0-6 and 8-15 of a phase C, sequence 1 word are formed by the enabling of gates A74-A88, and the word is received and stored in register 704 of transmission register circuit 700.

The words from sequence logic circuits 300, 400, 500 and 600 are supplied to transmission register circuit 700 on data bus 702 as illustrated in FIG. 10. The cycle 7 signal from converter 262 in clock and sequence circuit 200 is supplied to next word register 704 to gate the word on data bus 702 into register 704. A parity generator 740 supplies a parity output at 742 to gate N21 of register 704 to assure the number of trues in address BlTs 7-15 is odd. Upon receipt of a synch" signal on lead 164 from scanner-transmitter 146, the data in register 704 is transferred to current word register 706 for scanning by scanner-transmitter 146.

From the above, it can be seen that central control station 100 supplies control signals and alarm scanning signals in sequential alternation to continuously provide alarm scanning and control operation at remote stations 1000 and local points 22 without interference therebetween. Each word supplied to local point interface 140 and transmitted by scanner-transmitter 146 has 16 BlTs with BIT 0-2 corresponding to wordtype data, BlTs 3-6 corresponding to function data and BlTs 7-15 corresponding to address data. The word prepared by sequence logic circuit 300 contains the most significant half of the address of a field point such that each phase A, sequence 0 word addresses a remote station 1000 or local point interface 140. The word prepared by the sequence logic circuit 400 contains the least significant half of the address of a field point such that each phase A, sequence 1 word addresses an individual field point at a remote station or local points 22. Similarly, words prepared by sequence logic circuits 500 and 600 correspond to the most and the least significant halves of the address of a field point, respectively, such that the phase C, sequence 0 words address a remote station 1000 or iocal point interface 140 and phase C, sequence 1 word address an individual point at a remote station 1000 or at local points 22.

The words in transmission register circuit 700 are received at local point interface 140 and each remote point interface 1024 simultaneously and their utilization thereat will be described with reference to FIG. 11. The operation at interfaces 140 and 1024 is the same with the only difference between remote and local point operation being that no telecommunication link is required for the local points.

Word-type data on BIT s 0-2 is applied to word-type decoder 1072 in such a manner that a true on output 1074 from gate A89 indicated a phase A, sequence 0 word, a true on output 1076 from gate A90 indicated a phase C, sequence 0 word, a true on output 1078 from gate A91 indicated a phase A, sequence 1 word, and a true on output 1080 from gate A92 indicated a phase C, sequence 1 word. As can be seen from FIGS. 6, 7, 8 and 9, the constant phase, sequence and parity data on BlTs 0-2 is such that only one of gates A89-A92 can be enabled with each word received at the interface such that only one of outputs 1074, 1076, 1078 and 1080 is true at a single time.

Function data on BlTs 3-6 is supplied to function decoder 1082 and to acknowledge gate A103. Gate A103 requires BlTs 3-6 to be false, true, false and false, as is the case when flip-flop RS1 in sequence logic circuit 400 is reset such that output 432 is true to provide an acknowledge" signal during the preparation of a phase A, sequence 1 word. The other input required to enable acknowledge gate A103 is received from gate A102 which is enabled by a phase A, sequence 1 word, as will be described hereinafter.

Address data on BlTs 8-15 is supplied to parity generator 1083 such that the output 1084 thereof is true if the number of trues on BlTs 8-15 is even and false if the number of trues on BlTs 8-15 is odd in the same manner by which address parity B11" 7 is generated by parity generator 740 of transmission register circuit 700. Gates N39, N40 and N41 compare address parity BIT 7 with output 1084 from parity generator 108 such that when the parities are identical a true is supplied to address decoding gate A and point address enabling gate A101. Gate A100 receives BlTs 8-15 and is designed such that it is enabled only when the binary coded address of a word corresponds to the address of the remote station 1000 and when the address parities are identical. Address BlTs 8-15 are also supplied to point address register 1086 for storage when gate A101 is enabled.

Gate N58 receives the output of address decoding gate A100 and also receives output 1078 from word-type decoder 1072 corresponding to a phase C, sequence 0 word to set flipfiop R829 and provide a "control enable" signal on lead 1034 to close contacts 1036 and 1070. Thus, when a phase C, sequence 0 word containing the address of the remote station is received, flip-flop R829 is set and remains set to permit communication of analog, contact status, in scan and other control signals to central control station 100 until a succeeding phase C, sequence 0 word is transmitted at central control station 100. 1f the succeeding phase C, sequence 0 word does not contain the address of the remote station, the output of address decoding gate A100 will be false to enable gate N60 and place a false on the input 1104 of flip-flop R529 to reset the flip-flop and remove the "control enable" signal to open contacts 1036 and 1070.

The word following the phase C, sequence 0 word that sets flip-flop R529 will be a phase A word, and the next word will be a phase C, sequence 1 word containing the address of an individual field point at the remote station. Accordingly, gate A104 will receive a true on output 1080 from word-type decoder 1072 and a true from output 1108 of flip-flop R829. The third input to gate A104 receives output 1122 of flip-flop RS31 which is true when no alarm scan is in progress at the remote station and false when an alarm scan is in progress in a manner to be described hereinafter. Thus, if no alarm scan is in progress, gate A104 is enabled to place a true at each of gates A93-A99 of function decoder 1082 to pass decoded function data from BlTs 3-6 to the remote point group 1002 through cable 1046. The true output of gate A104 also enables gate 02 to enable gate A101 if the address parities are identical, and the true on the output of gate A101 places the address of the individual field point in point address register 1086 for selecting the point in conventional manner through cable 1048.

Dependent upon the function data of the word, contact status, analog and range select signals corresponding to the addressed point may be communicated to peripheral annun-

Referenced by
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Classifications
U.S. Classification340/3.51, 340/3.61, 340/3.43
International ClassificationH04Q9/14
Cooperative ClassificationH04Q9/14
European ClassificationH04Q9/14