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Publication numberUS3646371 A
Publication typeGrant
Publication dateFeb 29, 1972
Filing dateJul 25, 1969
Priority dateJul 25, 1969
Also published asCA933606A, CA933606A1
Publication numberUS 3646371 A, US 3646371A, US-A-3646371, US3646371 A, US3646371A
InventorsFlad Friedrich W
Original AssigneeUs Army
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated timer with nonvolatile memory
US 3646371 A
Abstract
A remote settable electronic circuit timer system is described using an integrated MOS counter supplemented by an integrated programmable decoder consisting of MNOS transistors. Charge storage in the dielectric of the MNOS transistors is used to achieve memory without power. The setting information is counted into the counter at an accelerated rate and then transferred into the decoder, which serves as a memory. At the start of the timing operation, the counter is reset to zero. Then the counter counts up and when coincidence with the number stored in the decoder is achieved, an output signal is generated. The system automatically adjusts the setting for deviations of the oscillator frequency from its nominal value. Also, during the setting operation, all circuits of the timer are checked for proper functioning.
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[ 1 Feb. 29, 1972 INTEGRATED TIMER WITH NONVOLATILE MEMORY Friedrich W. Flad, Rockville, Md.

The United States of America as represented by the Secretary of the Army July 25, 1969 Inventor:

Assignee:

Filed:

Appl. No.:

References Cited UNITED STATES PATENTS 6/1964 Clapper ..328/37 X 6/1965 Weimer ..307/221 12/1968 Marcus .307/238 X 7/1969 Norman et al. ..307/221 12/ 1962 Euker et al ..102/70.2 R 3/ 1970 Ambrosini ..102/70.2 R

SETTER POWER 26 AUTOMATIC :2 RESET OTHER PUBLICATIONS Pub. 1 Electronics Review in Electronics, Vol. 41 No. 22, dated Oct. 28, 1968, pages 49- 50.

Primary Examiner-Stanley D. Miller, Jr. Attorney-I-larry M. Saragovitz, Edward J. Kelly, Herbert Berl and J. D. Edgerton A remote settable electronic circuit timer system is described using an integrated MOS counter supplemented by an integrated programmable decoder consisting of MNOS transistors. Charge storage in the dielectric of the MNOS transistors is used to achieve memory without power. The setting information is counted into the counter at an accelerated rate and then transferred into the decoder, which serves as a memory. At the start of the timing operation, the counter is reset to zero. Then the counter counts up and when coincidence with the number stored in the decoder is achieved, an output signal is generated. The system automatically adjusts the setting for deviations of the oscillator frequency from its nominal value. Also, during the setting operation, all circuits of the timer are checked for proper functioning.

ABSTRACT 3 Claims, 10 Drawing Figures V34 I0 FUZE POWER SCALE F I I T 1 T I I T T I T I 36\ SC GI R R R R R R R R R s o O 1 3 4 5 5 7 8 9 mom 3 2 2 2 2 2 2 z 2 2 I G7 5 2 2 E g5) 22 2% MAIN COUNTER IIIER111IE m R R R R R FIRING 0. 2I 2 23 4 5 s 1 s 9 10 2" CIRCUIT 5 5 5 5 5 5 5" 5 3 2'' MEMORY RESET 8. OUTPUT 0 2 3 4 5 5 7 B 9 l0 FEEDBACK LINE Z 2 2 2 2 2 2 2 2 2 2 CIRCUIT MEMORY SET8 F I CONTROL LINE 30 PULSE SEPARATION PROGRAMMABLE DECODERIS) 32 OUTPUT PATENTEDFEBZS I972 3,646,371

SHEET 2 [IF 5 46\ 48 4O P 44 T S ID VD --D FIG. 3fl

mvsemon FRIEDRICH W. FLAD ATTORNEYS PATENTEDFEB29 I972 3,646,371

SHEET II UF 5 POWER 0N AUTOM. RESET MEMORY RESET MEMORY RESET 0 I DELAY GEEEDBAEIFNE o MEMORY sETa b I CONTROL LINE C JIJWIHTIITTL JTITIIJT JULIIIL ATOR OUTPUT d INPUTTO MAIN COUNTER COUNT I 2 3 I023 I024 I025 I026 2046 2047 2048 e I DECODER GATE OUTPUT f 2 OUTPUT OF SCALER O 80 M EsE a YEMORYR T 0 M I I I I I I I I I I I I I I I I I I FEEDBACK LINE "*1 ILOW MEMORY SET MEMORY SET a O 1 I l ISTART SYNCHRONIZATION STOP| CONTROL LINE c TLTLITTLTI IT mmumrumr OUTPUT INPUTTO COUNT I 2 3 1-4 3 2 f MAIN COUNTER DECODER GATE OUTPUT 2 OUTPUT OF SCALER INVENTOR FRIEDRICH W. FLAD ATTORNEYS IAIENTEIIFEBZQ I972 3,646,371

SHEET 5 (IF 5 MEMORY RESET 8 I FEEDBACKLINE E MEMORY SET a CONTROL LINE I I I III I I FUZE OSCILLATOR OUTPUT INPUT TO COUNT I 2 3 4 254255 256 257 5IO 5II 5|2 SCALER I 2 OUTPUT OF SCALER MEMORY RESET 8 O I FEEDBACK LINE 0 MEMORY SET 8 b I CONTROL LINE d III IIT NPUTTO MAIN COUNTER COUNT I 2 3 4 r-s 1-4 T-3 T-2 H 1 84 0 2 OUTPUT e FROM SCALER O DECODER GATE f I I OUTPUT 8 INVENTOR FRIEDRICH W. FLAD ATTORNEYS INTEGRATED TIMER WITH NONVOLATILE MEMORY The present invention relates to a simplified and inexpensive timer which utilizes integrated circuitry. The timer can be set and reset an unlimited number of times and after setting it remembers the time setting without power being applied. During setting, the oscillator of the timer is calibrated and all circuits are checked for proper operation.

The timer of the present invention is constructed for use in time fuzes of artillery rounds. The fuze power supply is spin and setback activated. This means that no power is available to the timer prior to firing. For the setting operation, power is supplied by a setting box. After setting, the fuzeis disconnected from the setting box. This requires that the timer memory maintain its information without the application of power. To meet this requirement, the timer of the present invention employs a memory incorporating elements in the form of p-channel insulated gate field-effect transistors with silicon nitride as gate insulator and a thin silicon dioxide layer between the silicon surface and the nitride layer, hereafter referred to as MNOS transistors. These devices are capable of storage without power and are compatible with the integrated circuitry techniques used in manufacturing the more conventional MOS transistors.

Various timers have been proposed in the past but none has been found suited for use in time fuzes of artillery rounds. Timers utilizing magnetic core counters have the capability of memory without power but, because of their large size and bulk and their high cost of manufacture, they are not suited to fuze applications. Timers with fusible links as memory elements can be produced by integrated circuit techniques but have only a limited number of resets because the burning out of the fuze links is not reversible. Finally, timers with ferroelectric memories need polarization voltages of about 200 v. 'or more and thus require complicated and expensive interface between memory elements and counter.

The present invention avoids these and other difficulties by providing a small, lightweight, and inexpensive fuze timer which can be manufactured using more or less conventional integrated circuit techniques. The timer comprises integrated MOS counters supplemented by an integrated programmable decoder consisting of MNOS transistors. Charge storage in the dielectric of the MNOS transistors is used to achieve memory without power.

The setting information is counted into the counter of the present invention at an accelerated rate and then transferred into the decoder which serves as a memory. At the start of the timing operation, the counter is reset to zero. Then the counter counts up and when coincidence with the number stored in the decoder is achieved, an output signal is generated. The system automatically adjusts the setting for deviations of the oscillator frequency from its nominal value. Also, during the setting operation, all circuits of the timer are checked for proper functioning.

It is therefore one object of the present invention to provide an integrated circuit timer with a nonvolatile memory.

Another object of the present invention is to provide a remote resettable electronic timer.

Another object of the present invention is to provide an electronic timer utilizing integrated MOS counters supplemented by an integrated programmable decoder consisting of MNOS transistors.

Another object of the present invention is to provide a spin and setback activated timer particularly adapted for use in the time fuzes of artillery rounds.

Another object of the present invention is to provide a timing system which automatically adjusts the setting of the system for deviations of the oscillator frequency from its nominal value.

These and further objects and advantages of the invention will be more apparent upon reference to the following specification, claims, and appended drawings, wherein:

FIG. 1 is an overall block diagram of the resettable timer of the present invention;

FIG. 2A is a diagram of an MNOS transistor with the gate connected to the source electrode of the transistor;

FIG. 2B is a plot of the drain current as a function of the drain voltage with zero gate bias showing the on state and the off state of the transistor;

FIG. 3A is a diagram of an MNOS transistor with the gate connected to the drain electrode of the transistor;

FIG. 3B is a plot of drain current as a function of drain voltage for the MNOS transistor connection shown in FIG. 3A;

FIG. 4 is a detailed circuit diagram of the programmabie decoder forming a part of the timer of FIG. 1, showing an integrated circuit construction of MNOS transistors;

FIG. 5 is a plot of waveforms appearing in FIG. 1 during timer setting;

FIG. 6 is a similar plot of waveforms during later stages of the setting sequence;

FIG. 7 is a plot of voltage waveforms for FIG. 1 during the sequence of scaler checking; and

FIG. 8 is a plot of voltage waveforms for FIG. 1 for the timer setting check.

The digital timer of the present invention comprises a time base and an accumulator. In the preferred embodiment, the accumulator takes the form of a digital counter. This counter is advanced one count after each period of the time base. If at time t,,=0 the state of the counter was 0, the state of the counter at time t, represents the elapsed time between t and t, in units of time base periods. At time t, the timer produces an output signal which initiates a function such as activating a fuze firing circuit. This is achieved by a decoder in the timer which produces an output signal when the counter reaches the state which corresponds to t,. Alternatively, the timer may produce an output signal when the counter reaches its maximum corresponding to t,,,,,,. In order to obtain the output signal at t, and not at 2 the counter must start at t,,=0 from a state corresponding to the time complement t,,,,,,t,.

The time delay t, is variable and is programmed electrically by a setting box, requiring not more than four connections between the setting box and timer. The maximum number of connections eliminates the possibility of providing for parallel setting of the decoder or parallel resetting of the counter. In the present invention, the decoder is programmed by counting the number of pulses corresponding to t, into the counter and then transferring this number into the decoder in parallel. The decoder serves as memory and stores the information. Before the timing operation starts, the counter is reset to zero. During the timing operation, the counter counts up and when coincidence with the number stored in the decoder is achieved, an output signal is generated.

In the case of a preset counter, a number of pulses corresponding to the time complement t,, l, is counted into the counter. The counter itself serves as a memory. In the timing operation, the count is continued until the maximum count is reached. Then an output signal is generated.

FIG. 1 shows a preferred embodiment for the timer of the present invention in which the count is first inserted into a counter and then transferred to a decoder which serves as a memory. Referring to FIG. 1, the timer, generally indicated at 10, comprises a scaler 12, a main counter 14, and a programmable decoder 16. In addition to the ground terminal 18, the timer 10 includes a memory set and control line terminal 20, a memory reset and feedback line terminal 22, and a setter power terminal 24. Setter power is applied to scaler 12 through a gate 26 and automatic reset device 28 to the 10 stages of scaler 12 which take the form of integrated circuit flip-flops, preferably formed by insulated gate field-effect transistors or MOS transistors. Main counter M is made up of 12 flip-flop stages, again preferably formed from integrated MOS transistors. Programmable decoder 16 consists of II flip-flop stages using integrated MNOS transistors in addition to an input or pulse separation circuit 30 and an output circuit 32. The various elements of the timer are interconnected by a plurality of gates labeled G G as illustrated. A setback and spin activated fuze power supply is illustrated at 34 and the timer includes a fuze oscillator 36. preferably operating at a frequency of about 5.120 H2. Finally, an output signal from the timer is developed from the decoder 16 on lead 38 which is supplied to a fuze firing circuit (not shown).

The memory elements of the timer are virtually p-channel insulated gate field-effect transistors with silicon nitride as gate insulator and a thin silicon dioxide layer between the silicon surface and the nitride layer. In their original state. these devices perform very similar to MOS transistors. However. if a positive voltage with respect to the substrate is applied to the gate of a magnitude that produces a field in the oxide layer in excess of a critical value of approximately v./cm.. electrons can tunnel through the oxide. They are trapped in the nitride near the oxide-nitride interface. If the positive voltage is removed. these trapped charges produce a negative "builtin voltage in the dielectric. which decreases the threshold voltage of the device. The threshold voltage can virtually be made zero. The charges remain stored in the dielectric for a very long time without power being applied. Within the operating range of the timer. the effect is almost independent of temperature. If a negative voltage in excess of the critical value is applied to the gate. the process is reversed and the device is changed back to its original state. The critical voltage is well defined. If the supply voltage is chosen below the critical voltage, the device can be operated as a field-effect transistor without changing its threshold voltage.

FIGS. 2 and 3 illustrate the operation of such a device. FIG. ilA shows an MNOS transistor with the MNOS transistor 40 having a drain electrode 42. a source electrode 44. and a gate 46. In FIG. 2A. the gate is shown as connected to the source. FIG. 2B is a plot of drain voltage i as a function of drain voltage V with a zero gate voltage. Curve 48 in FIG. 2B shows the characteristic of the transistor in the on state whereas curve :50 shows the characteristic with the transistor in the off state. i.e.. a straight horizontal line. The horizontal divisions in FIG. 2B represent 1 v. per division whereas the vertical divisions are each indicative of a change in current of 0.2 ma.

FIG. 3A shows a similar MNOS transistor 52 having a drain :54. source 56. and gate 58. In FIG. 3A. the gate 58 is connected to drain 54. FIG. 3B is a similar plot of drain current i as a function of drain voltage V,, for the transistor connection shown in FIG. 3A. Curve 60 is a plot of the transistor characteristic when the transistor is turned on and curve 62 is a similar plot with the transistor turned off. As before. the horizontal divisions each represent a change in voltage of l v. and the vertical divisions a current change of 0.2 ma.

FIG. 4 is a detailed circuit diagram of the programmable decoder 16 of FIG. I. The decoder uses MNOS transistors as memory elements which act as insulated gate field-effect transistors with an electrically alterable threshold voltage. If a negative signal of about 45 v. with respect to the substrate is applied to the gate. the device is turned off." This means the device has a threshold greater than 0 v. If a positive signal of about 45 v. with respect to the substrate is applied to the gate. the device is turned on. This means its threshold voltage is 0 v. Hence. the transistor is conducting with no bias applied to the gate. A logical 0" is represented by a potential of approximately +25 v. and a logical l is represented by a potential close to ground. In F IG. 4. the four resistors 64. 66. 68. and 70 at the left-hand side of the circuit diagram. are discrete components. The remainder of the circuit in FIG. 4 is formed from integrated components. Dashed line boxes 72. 74. and 76 show three different N-regions used as substrates which regions are electrically isolated from each other. All of the active elements in the circuit of FIG. 4 are of the MNOS type. Those elements which actually perform a switching function are referred to as transistors. with the letter O and appropriate isubscript. Elements which only serve as a load resistor are identified as resistors with the letter R and appropriate subiicript. All diodes shown connect with their cathode to the N- iiubstrate. It is possible to implement them by diffusing P-regions into the Nsubstrate in the same stem with the source and drain region of the other elements.

FUNCTIONAL DESCRIPTION Following is a functional description illustrating the manner of operation of the circuit structure described above. particularly in reference to the overall timer of FIG. I.

The time base can be thought as an oscillator. The timer must be settable in increments of 0.1 second. This detennines the time base period to 0.1 second. An oscillator of this frequency requires rather large frequency determining components. In order to obtain better stability and to be able to use thick film techniques in manufacturing the oscillator. it is advantageous to choose a higher oscillator frequency. To obtain the required 0.1 second time base period. the oscillator frequency is divided by the MOS counter or scaler 12. So an oscillator frequency of 5.120 Hz. was selected. This frequency is divided by a nine-stage binary counter in the scaler.

The maximum number of connections to the setting box allows only serial setting of the timer. To obtain a short setting time. the timer has to be set at an accelerated rate. This is accomplished by bypassing the sealer and feeding the oscillator output signal directly into the counter 14. Using the fuze oscillator rather than an external pulse source to set the timer, makes it possible to compensate for deviations of the oscillator from its nominal frequency. The oscillator signal is fed to the counter through a gate. Opening and closing of the gate is controlled by an external precision timer. If the timer is to be set to I and the dividing factor of the scaler is N. the opening time of the gate t is The period of the fuze oscillator is T,,+AT, where T is the nominal period. The number of periods n counted by the counter during t is n=t,,/T,,+AT (2) in timing operation with the scaler in the circuit a time base period is N(T,,+AT) and the counter counts n periods until an output signal occurs. This gives a delay time t or with (2 to =t.,/T,,+AT T.,+AT)N or with l t,,=t, This is independent of the oscillator period. Since the counter can count only integer numbers. equation (2) contains an er- :ror. This error is a fraction of a period a( T,+AT). where a l. in timing operation. this error is multiplied by N but since the delay time also is multiplied by N. the relative error stays the same and depends only on the resolution of the counter.

in the setting procedure. only the oscillator 36 in the fuze is used as a time base. To be sure that the counter sees the correct time base frequency during timing operation. it is necessary to check the scaler for proper operation. As described previously, the setting information is first counted into the counter before it is transferred into the decoder 16. Therefore. the counter has to be checked for proper operation prior to this. These considerations led to the following sequence:

Step 1: Main counter is checked for correct reset and proper operation.

Step 2: Setting information is counted into main counter.

Step 3: information is transferred from counter into .lecoder.

Step 4: Scaler is checked for proper reset and operation.

Step 5: Counter is checked for proper setting.

Thus. a ready" signal after the setting sequence insures not only that the time has been set to the correct value. but also that all circuits are in operational condition.

The fuze power supply is spin and setback activated. Therefore. it is only in operation when the fuze is fired. For setting and checking operations. power is supplied externally by the setter. The firing circuit works only from the fuze power supply. Therefore, the timer can be driven through the firing point without setting off the detonator.

The fuze oscillator 36 provides a time base. A unique feature of the system is that the fuze oscillator requires no trimming. because in the setting sequence the fuze oscillator timer is calibrated against a precision oscillator in the setter. The scaler I2 is a binary counter consisting of IO flip-flops. Its

purpose is to divide the frequency of the fuze oscillator. Only the first nine stages of the sealer are used as a frequency divider, providing an output signal with a period of 100 msec, if the fuze oscillator is at its standard frequency. The 2 flip-flop of the sealer is used as a control flip-flop.

The main counter 14 consists of 12 flip-flops arranged to form a binary counter. Only the first ll flip-flops are used for counting, providing a count capability of 2047. The 2 flipflop of the main counter is used as a control flip-flop. The programmable decoder 16 contains a memory element for each of the flip-flops 2 through 2' of the main counter and is a simplified decoder, which compares the state of the main counter with the number stored in the memory. The memory elements are MNOS transistors. They are in the on state if they represent a and in the off state if they represent a l. A memory reset pulse switches all memory elements to the on state, that means to 0. if a memory set pulse is applied, all memory elements whose corresponding flip-flops in the main counter are in the l state are switched to the off state. The remaining memory elements remain unaltered in the 0 state. This means that the state of the main counter 14 is duplicated in the memory of decoder 16. The decoder compares each bit in the memory with its corresponding flipflop of the main counter. If a flip-flop represents a number which is equal to or greater than the corresponding memory bit, the gate associated with this bit gives an output. The output circuit of the decoder gives a low output signal on lead 38 if there is an output signal from each individual bit gate. This means if a low output signal from the decoder occurs, the number represented by the state of the main counter is equal to or greater than the number stored in the memory. If the main counter counts up starting from 0, the first output signal from the decoder occurs when the number represented by the state of the main counter equals the number stored in the memory.

The automatic reset circuit generates a signal whichresets all flip-flops of the sealer and of the main counter to the 0" state, when either fuze power or setter power is applied to the timer.

If the fuze power supply is on, the fuze oscillator feeds pulses through gates G, and G into the sealer. The signal from the a output is transmitted through gates G and G, to the input of the main counter. On the other hand, the positive voltage from the fuze power supply prevents any other signal from passing through gate G Thus, the sealer and the main counter work in series, as required for in-flight timing operation. For checking and setting operations, that is with the fuze power off, the sealer and the main counter can be cycled individually at the pulse rate of the fuze oscillator. The input signal is provided by the output of gate G Gate 6., is controlled by the setter over the control line. G puts out fuze oscillator pulses regardless of the state of the control line, if there is a low output signal from G Whether the output pulses from G are fed into the main counter or the sealer is determined by the state of the 2 flip-flop of the sealer. If this flipflop is in the 0 state; the pulses are fed into the sealer and if it is in the l state, the pulses are fed into the main counter. Besides setter power and ground, there are two signal lines, memory reset and feedback lines and memory set and control line, required from the setter to the fuze. Each of these two signal lines is shared by two different signals. The feedback signal and the control signal are at a high potential in'the 0" or no signal state. If they go low, it is interpreted as a 1" or a signal. The memory reset or memory set signal have an amplitude which is more positive than the 0" state of the signal with which they share the line. The circuits which separate the two signals are incorporated in the programmable decoder. The feedback signal is so composed that the information it supplies to the setter is sufficient for a decision about the operation condition and the setting of the timer. The feedback signal from the sealer is generated in gates G and G In order to get a low output signal from gate G it is necessary that the 2 flip-flop in the sealer is in the 0" state. This means that the output of G is connected to the input of the sealer. As long as the 2 flip-flop of the sealer is in the 0" state, the output signal of G consists of inverted clock pulses. When the 2 flip-flop of the sealer switches to the l state, the output of G goes high and stays high as long as the 2 flip-flop remains in the 1" state. When all flip-flops are reset to the 0" state, there will be an output signal consisting of fuze oscillator pulses G If the control line is actuated, gate G goes high, G, puts out pulses, which are counted in the sealer. When 256 pulses have been counted by the sealer, the 2 flip-flop switches to the 1" state. The output signal of G stays low until 512 pulses have occurred and the 2 flip-flop switches back to the 0 state. At the same time, the 2 flip-flop changes to the low state and gate G prevents further output signals.

The feedback signal from the main counter is generated in gates G and G In order to obtain a low output signal at 6 it is necessary that there is a low output signal from the decoder. When the timer is shipped from the manufacturer, all memory elements are set to the 1" state (memory transistor not conducting) and therefore corresponds to the maximum time capability of the counter. If the timer had been set previously, the number stored in the memory will be between 2.5 seconds (minimum time setting allowed by setter) and the maximum time. The memory will always contain at least one 1. Therefore, there will be no low output signal from the decoder prior to a memory reset pulse if the main counter has been reset to 0. This prevents a low output signal at gate 6, After a memory reset pulse, the output of the decoder goes low and G puts out pulses. The memory reset pulse also switches the 2 flip-flop of the sealer to the l state, which prevents oscillator pulses from G and connects the output of G to the input of the main counter. If the control line is now actuated, the control line input to G goes high, the main counter starts counting. At a count of 1024, the 2" flip-flop switches to the l state. Since the 2 flip-flop is still in the 0" state, the output of gate G goes negative and G is now latched independent of the control line and counting continues. Also, the output of G stays low as long as the 2 flipflop remains in the l state. The memory is still reset and its output is low. When the 2" flip-flop switches back to the 0 state, the output of 6,, goes high and the output of G changes back to oscillator pulses. If the main counter is cycled once more, there will be only feedback pulses throughout the cycle, since the 2 flip-flop is now in the l state.

If a number had been inserted into the memory and the main counter is reset to 0, there is no low output signal from the decoder. This prevents a feedback signal from the main counter. if the 2 flip-flop of the sealer is in the l state, there will be no feedback signal at the output of G With the control line actuated and the main counter counting, the first feedback signal will occur, when the state of the main counter matches the state of memory.

The setting and checking procedure is described as follows. As mentioned previously, four connecting wires between fuze and setter are required to set the timer. After these connections are made, setter power is applied to the timer. This generates an automatic reset.'After a short delay to allow the fuze oscillator to stabilize, a memory reset pulse is applied to the memory reset and feedback line as shown at 78 in MG. 5. This resets all memory elements to the 0" (on) state and the 2 flip-flop of the sealer is set to the l state.

The next step is a check of the main counter. After the memory elements have been reset to 0, the setter receives oscillator pulses as feedback signals through gates G 6, and G These pulses indicate that the oscillator is working and that a low output signal from the decoder is present. This also indicates that the memory has been reset. The pulses will allow the setter to operate G in the correct phase relationship with the fuze oscillator. If no pulses are received by the setter within a certain short time, or if the feedback signal stays low continuously, an error signal is displayed and the sequence is stopped. if the feedback signal is correct, the control line is actuated, goes low, the input to G, goes high, with the first negative going edge of the feedback signal. This allows the main counter to count. The output of G is high, because of its reset state oscillator pulses reach the counter through G G and 5,. At the same time, the setter counts the feedback pulses in parallel to the main counter via gates 12, 13. and 14. When the feedback signal changes from individual pulses to a con- :stant low level, this is detected in the setter. If this change occurs at a count other than I024, an error signal is generated and the sequence stops. If the change occurs at a count of i024, it indicates that the main counter had been reset and that it is counting correctly. At 1024, the output of G, goes low and G high. The output of the output circuit is still low and G goes high. Further, the number 1024 verifies that the feedback signal received by the setter was generated by the main counter and not from the sealer due to some error. The control line and the counter in the setter are reset after a slight delay after the count of 1024. Since the 2" flip-flop is in the ll state and the 2" flip-flop is in the 0" state, the output of G, is low. Thus, G provides a high input signal into G which maintains the count operation of the main counter until all flip-flops 2 through 2" are in the '0 state and the 2 flipt'lop is in the l" state. Then the output of G goes low and stops oscillator pulses into the counter. The feedback line was low between 1024 and 2048 because G was low. During the next phase, the desired time setting is inserted into the main counter. The waveforms are shown in FIG. 6. The waveforms m FIG. 6 overlap with the waveforms in FIG. 5. The broken line at 80 in FIG. 6 indicates the moment when the 2 flip-flop switches back to the 0" state. Before the 2048 fall time appeared, gate 12 was high due to the low input from G,,. When the 2048 fall time appears, 0,, goes high but simultaneously the clock signal goes low and G stays high until one-half a clock pulse later. The sealer and counter are both assumed to switch on the negative going edge of the clock pulses. With the first low going edge of the feedback signal, the control line goes low. This allows the main counter to count starting from 0. While the main counter is counting pulses from the fuze oscillator, the counter in the setter is counting pulses from the precision oscillator. When the counter in the setter reaches the state that represents the desired time, the control line goes high. Since the 2 flip-flop is in the l state, it cannot maintain fuze oscillator pulses to the main counter. The count stops when the control line goes high, regardless of the state of the .2" flip-flop is in the l state, it cannot maintain fuze oscillator pulses to the main counter. The count stops when the control line goes high, regardless of the state of the 2 flip-flop. Now a memory set pulse is applied to the memory set and control line. This duplicates the state of the main counter in the memory. This completes the setting sequence. Power to the t'uze can now be turned off.

The time interval during which the main counter was counting was determined by the precision oscillator and the counter in the setter. The main counter receives the number of pulses from the fuze oscillator that corresponds to the desired time setting regardless, within limits, of the fuze oscillator frequency. The start of the count interval was synchronized with the beginning of a fuze oscillator period. The counter in the setter has to count at a higher rate than the main counter to make the start error small. The stop of the count interval can occur anywhere within a period of the fuze oscillator. Under the assumption that the duty cycle of the fuze oscillator is $0 percent and that the main counter steps with the trailing edge of the clock pulse, a round off effect takes place. If the stop occurs during the first half of a cycle (low half cycle), the main counter remains on the last count. Should the stop take place during the positive half cycle of the clock, one count is added when the input signal is cut off, as shown at 82 in FIG. 6. If the start error of the counter in the setter can be neglected, the maximum setting error is half a period of the fuze oscillator. In use, the maximum error would be one-half a period of the output of the sealer.

The setting sequence is automatically followed by a check sequence, but a selector switch on the setting box will also allow a run through of the checking sequence alone.

The first step is a sealer check. The waveforms for this are shown in FIG. 7. When setter power is turned on, an automatic reset is generated. Gates G and G generate a feedback signal consisting of oscillator pulses. G,;, is blocked since no output from the decoder is present. 6,, is blocked by G which is blocked by the control line. After a short delay, the control line is actuated with a trailing edge of the feedback signal. Before the control line is activated (goes low), the setter tests for feedback oscillator pulses. If no low feedback signal is received by the setter within a certain time interval or if the feedback signal stays low constantly, an error signal is generated. The low signal on the control line enables the sealer to count. At the same time, the counter in the setter counts feedback pulses. At a count of 256, the feedback signal goes low and stays low because the 2 flip-flop of the sealer is in the l" state and G and G are activated. This change is detected by the setter. If it occurs at a count different from .256, an error signal is generated. A count of 256 indicates that the sealer had been reset and that it is working properly. It also verifies that the feedback signal was generated by the sealer.

In the next step, the setting of the timer is checked. The waveforms for the timer check are shown in FIG. 8. The control line is still low and the sealer is counting. Also, the feedback signal is still low because the 2 flip-flop of the sealer is in the l state. While the setter is waiting for the feedback signal to return to its 0" state, the counter in the setter is reset to 0. When the 2 flip-flop of the sealer switches from the l state to the 0" state, the 2 flip-flop of the sealer switches from the 0" state to the l state at count 512. This blocks G and no further feedback from the sealer occurs. At the same time, the count operation of the sealer is stopped by blocking G-, and the main counter starts counting because G is now conducting. The sealer state is now all 0" except the 2 flip-flop. When the feedback signal goes high, the counter in the setter starts counting pulses from the precision oscillator until its state represents the selected time. The feedback signal stays high until the number in the main counter equals the number stored in the memory. Then a low output signal from the decoder occurs and the feedback line goes low and feeds back oscillator pulses. This resets the control line. The time interval between coincidence of the setter counter with the selected time and the occurrence of a feedback signal or between feedback and coincidence, depending on the sequence of events, is measured in the setter. If this time interval exceeds 0.7 periods of the fuze oscillator at its standard frequency, an error signal is generated. If the time interval is within tolerance, a ready signal is displayed. Power is turned off and the fuze is ready for firing. It is assumed that the tolerance counter counts at 10 times the frequency of the fuze oscillator. The tolerance of 0.7 standard periods of fuze osciliator or seven counts of the tolerance counter allows an error of five counts in the main counter, one count for frequency variation of the fuze oscillator and one count start error of the setter counter.

When the control line goes high, the main counter is stopped if the time setting is smaller than 1024 counts. For a time setting of 1024 counts or longer, the main counter will continue to count as shown with dashed lines at 84 in FIG. 8 until the main counter reaches 2048 or setter power to the fuze is removed. But this has no effect on the operation of the setter since the first trailing edge of the feedback signal performs the switching.

The timing operation is described as follows: When the round is fired, spin and setback activate the fuze power supply. This results in an automatic reset signal. With fuze power on, G is conducting, G is not. The sealer starts counting. After 256 pulses, the 2 flip-flop of the sealer switches to the l state. Since G; is conducting, the main counter receives a positive signal. At a count of 512, the 2 flip-flop of the sealer switches back to the 0" state. This results in a negative step at the input of the main counter which advances the main counter by one step. This repeats every 512 pulses. The positive potential of the fume power supply blocks G and prevents oscillator pulses from getting to the main counter. If G, should transmit clock pulses, it does not affect the operation of the sealer, since the outputs of G, and G, are in phase. When the number represented by the state of the main counter equals the number stored in the memory, a low output signal from the decoder occurs, which triggers the firing circuit.

Resetting of the memory occurs as follows: Referring to FIG. 4, when power is applied to the decoder, diode D, clamps the substrate S, and the source of transistors 0, through Q,,, O and Q,,,, to +25 v. If there is no feedback signal, the gate of Q is closed to ground and Q is conducting. Therefore, the memory reset and feedback line is at approximately +25 v, which represents the 0 or no signal" state.

Source and gate of Q,,, are at approximately the same potential. Therefore Q,,, is turned off and its drain and the gates of all resistors on S, are at ground potential. The resistors are conducting. Also Q located on substrate 8,, is turned on. O clamps substrate S and the source of all transistors located on it to approximately +25 v. The memory set and control line is in the 0 or no signal state, that is, at +25 v. Q,,,, is turned off and the control line input to gate 6,, (FIG. 1) is'close to ground. Q,,,, is turned off. Therefore, all resistors on S are conducting.

The drain of transistor O and the source of resistor R are P-regions diffused into the N-substrate. Therefore, they represent diodes with their cathode connected to S,. If a positive memory reset pulse in excess of +25 v. is applied to the memory reset and feedback line, these diodes become forward biased. The potential of substrate S, rises to about the amplitude of the memory reset pulse. Since the source of transistors Q, through 0,, is connected to 8,, all these transistors are turned on regardless of the state of the counter and clamp the gates of the memory transistors Q12 through Q to the amplitude of the memory reset pulse. When the potential of S, rises, Q,,,, turns on. This turns off all resistors on S, to prevent excessive current and also turns off transistor 0 Therefore, substrate S is at ground potential. Thus, the memory transistors 0, through 0 experience the full amplitude of the memory reset pulse between gate and substrate. Therefore, they are all switched to the on -state, which represents 0.

When setting the memory, after the desired setting has been inserted into the main counter, a positive memory set pulse in excess of +25 v. is applied to the memory set and control line. Diode D clamps the source of O to about the amplitude of the memory set pulse. Since the gate of O is at ground, substrate S is clamped to the potential of the memory set pulse. 0 is turned on. This turns off all resistors on S, except R to prevent excessive current.

Depending on the state of the corresponding counter flipflops, transistors Q, through 0,, are turned on or turned off. As an example, let us consider stage 2. If the 2 flip-flop is in the 0 state, Q, is on. The, gate of 0, is therefore at +25 v. The voltage between gate of 0, and substrate is the difference between the amplitude of the memory set pulse and +25 v. This voltage is not sufficient to switch the state of 0, and it remains in the on state. If the 2 flip-flop is in the l state, Q, is off. The gate of 0, is close to ground and O experiences almost the full amplitude of the memory set pulse between gate and substrate. This switches 0,, from the on state to the off" state. The same is true for all remaining stages. Hence it follows that all memory transistors whose corresponding flip-flops are in the l state are switched to the off state, which represents a 1. The rest remain unchanged in the on or 0" state. Thus, the state of the main counter is duplicated in the memory.

For readout, power is applied to the timer. The main counter is reset to 0. All N-substrates and the source of the transistors located on them are at approximately +25 v.

If the main counter counts up, the following combinations occur in the 2 state:

From the above table it follows that O is turned off if the number in the 2 stage of the counter is greater than or equal to the number stored in the memory transistor 0, This is true for each bit. in order to obtain a low going output signal from the decoder, as required by the logic of FIG. 1, all transistors Q through Q have to be off. This means that the number represented by the state of the counter is equal to or greater than the number stored in the memory. Since the main counter is counting up from 0, the first low output signal occurs when the number in the counter equals the number stored in the memory. As the counter continues counting, the negative output signal may disappear. This is caused by the simplified design of the comparator. It only compares the individual bits without assigning a weight to them. Therefore, the output signal may disappear although the number in the counter is greater than the number in the memory if a low order 1" in the counter changes to 0" and a l is stored in the corresponding memory element. But since the timer only uses the first output signal, which represents an equality, the shape of the output signal after that is immaterial.

For isolation, the individual MNOS devices have to have a source to drain breakdown voltage which is higher than the switching voltage of the memories.

All MNOS devices with the exclusion of the memory transistors Q12 through Q22 have to perform like MOS devices. This means that they have to be in the off state. Therefore, the circuit is so designed that non of them experiences a high enough positive voltage between gate and substrate to change it to the on" state. A negative voltage which tends to turn the device off does not affect its performance.

Both signal lines from the setter are shared by two different signals. These signals have to be separated as they enter the decoder circuit.

The memory reset and feedback line is at +25 v. in its quiescent state. The signal more positive than +25 v. generates a memory reset signal. The output of the feedback gate 6,, connects to the gate of transistor 0,- and is therefore not affected by the memory reset pulse. If there is a feedback signal, gate 6,, puts out a signal that goes from ground to +25 v. This turns off transistor Qp Therefore, the memory reset and feedback line receives asignal that goes from +25 v. to ground, as shown.

The memory set and control line is at +25 v. in the 0" or no signal state. A positive signal in excess of +25 v. generates a memory set pulse. Transistor Q,,,; is off during that time. Therefore, the input to gate G remains close to ground, which keeps gate 6,, blocked. If the control line is actuated, a signal is applied that goes from +25 v. to ground. This turns on Q and the input signal to gate 0,, goes positive, as required to initiate a count operation.

Diode D, can be omitted if the signal for setting the 2 flipflop in the sealer feeds directly into the gate of a MOS transistor without any protective device between gate and substrate.

The potential of the gates of the memory transistors 0,, through Q 2 is determined by the voltage drop across D, and across the corresponding transistor on substrate 8,. The source potential of the memory transistors is determined by the voltage drop across D and 0 Since Q; has to carry a this may result in a positive bias of the memory transistors.

This may be avoided by adding two discrete diodes as shown ill 88 in F IG. 4 by dashed lines.

it is apparent from the above that the present invention provides an improved and simplified, inexpensive timer particularly adapted for operation in artillery projectile fuzes. Important features of the invention include the incorporation of MNOS devices in the decoder which act as memories without power and which may be formed by conventional integrated circuit techniques in a manner similar to the MOS transistors :making up the sealer and main counter. Because of the integrated circuit fabrication of the components, the timer may be of very small size and weight. The unit is completely resettable, and may be reset from a remote source and the system automatically adjusts the setting for deviations of the oscillator frequency from its nominal value.

What is claimed and desired to be secured by United States Letters Patent is:

l. A digital timer for fuzes and the like comprising a main counter and a decoder both formed from semiconductor iniiS tegrated circuits. said decoder including means for storing a count when power is removed, means coupled to said main counter for inserting a count into it, means coupling said counter and decoder for transferring said count to said decoder and responsive to a coincidence in the count in said counter and decoder for producing an output signal indicative of said coincidence, an oscillator, and means including a sealer formed from semiconductor integrated circuits coupling the output of said oscillator to said main counter, said means coupling the output of said oscillator to said main counter including means for bypassing said sealer.

2. A timer according to claim 1 wherein said sealer and main counter both comprise a plurality of MOS transistor flipflops and said decoder comprises a plurality of MNOS transistor flip-flops.

.3. A timer according to claim 2 including a setback and spin activated power supply coupled to said sealer, counter and decoder.

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Classifications
U.S. Classification327/279, 968/846, 377/39, 102/215, 377/52, 377/121
International ClassificationG04F10/00, G04F10/04, H03K5/135
Cooperative ClassificationG04F10/04, H03K5/135
European ClassificationH03K5/135, G04F10/04