|Publication number||US3648102 A|
|Publication date||Mar 7, 1972|
|Filing date||Aug 19, 1970|
|Priority date||Aug 19, 1969|
|Also published as||DE1942060A1, DE1942060B2|
|Publication number||US 3648102 A, US 3648102A, US-A-3648102, US3648102 A, US3648102A|
|Original Assignee||Olympia Werke Ag|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (7), Classifications (20)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Sttes ate Bettina ar. 7, 1972  NUMERICAL DISPLAY TUBES  References Cited CONTROLLED BY PULSES PRODUCED UNITED STA S PATENTS BY VOLTAGE INVERTER AND DIRECTED BY SWITCH DEVICE TO 3,493,957 2/1970 Brooks ..340/334 X EAQH TUBE KN SUCCESSHON 3,509,420 4/1970 Ogle ...3l5ll69 R X 3,522,471 8/1970 Somlyody ..340/324 R X  Inventor: Hubertus Bettin, Braunschweig, Germany Primary Examiner-Roy Lake 73 A 01 W 1: A h 1 Sslgnee ix? er a wllhelms Ger Assistant ExaminerS1egfried H. Grimm Attorney-Spencer & Kaye  Filed: Aug. 19, 1970 21 App1.No.: 64,944  ABSTRACT A circuit arrangement for controlling the operation of numeri- 30 F A P D a cal display glow tubes and including means for producing a 1 pp Ion "on y a train of pulses of sufficient voltage to operate such tubes and 19, 1969 Germany 19 42 0601 switching means connected between the voltage pulse producing means and the tubes for applying the pulses directly to [1.8. CI. R, R, each tube in uccession and also causing the pulses to directly 315/260, 315/315 340/324 340/344 control the switching operations of the switching means.  Int. Cl. ..H05b41/30  Field of Search ..315/84.6,169 TV, 169 R, 133,
315/145, 260, 315; 340/334, 339, 343, 344, 324 R, 166 EL; 307/222 R, 222 B, 223 R, 223 B; 328/37,
I do 0/ D/SPLAY MEMORY 7 Claims, 3 Drawing Figures Patented March 7, 1972 3 Sheets-Sheet 1 \ozmz $665 INVENTOR- Hubertus Be'mn BY I a 0' @a mom Y8.
Patented March 7, 1 972 3 Sheets-Sheet 2 INVENTOR; Huberrus Berrin BY E ATiORNEYS NUMERICAL DISPLAY TUBES CONTROLLED BY IULSES PRODUCED BY VOLTAGE INVERTER AND DIRECTED BY SWITCH DEVICE TO EACH TUBE IN SUCCESSION BACKGROUND OF THE INVENTION The present invention relates to a circuit arrangement for controlling multiple-cathode numerical display glow tubes, in particular for producing a high voltage to operate the numerical display tubes and for controlling the individual electrodes of the numerical display tubes.
Because of the relatively high direct voltages required to operate numerical display tubes, it has heretofore been the practice to control the electrodes of the numerical display tubes by special power amplifiers which can switch high voltages and which are controlled by counters or shift registers. As a result, known control circuits for this purpose are relatively complex and expensive.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit arrangement in which the controlling counter or the shift: register furnish a sufficiently high output to be able to directly control the electrodes of the numerical display tubes.
The present invention consists essentially in that an electronic direct voltage inverter whose output voltage is rectified in a known manner serves as a voltage supply for the numerical display tube and that the drive signals for the counter or the shift register are derived from the alternating-voltage pulses of the direct voltage inverter.
Advantageously, the counter or the shift register is built with thyristors since these components can support a sufficient voltage to be able to switch the high voltages required for the operation of numerical display tubes once they have been triggered by triggering pulses.
When a plurality of numerical display tubes are used, the cathodes associated with the same number are connected in parallel, as is generally known, and the anodes of the numerical display tubes sequentially are controlled by a shift register to excite the digit to be indicated.
In this case the anodes of the numerical display tubes are preferably controlled directly by the output pulses of the shift register and the shift pulses for the shift register are derived from the alternating voltage pulses with a direct voltage from the direct voltage inverter superposed thereon.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of a preferred embodiment of a circuit arrangement according to the present invention.
FIG. 2 is a schematic representation of several stages of one embodiment of a shift register for the control of the numerical display tubes in the circuit of FIG. 1.
FIG. 3 is a schematic representation of an embodiment of a memory and a switching arrangement for the control of the numerical display tubes in the circuit of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit arrangement for controlling, and supplying power to, a plurality of numerical display tubes 101, I02, 103, etc.
It is possible to operate a substantially higher number of numerical display tubes than illustrated with this circuit arrangement. When data which is delivered serially from the memory of a computer is to be displayed, the individual data words must be associated with the proper digital values and the resulting characters are to be readable on an indicator screen 100 consisting of the individual numerical display tubes 101, 102,103....
Numerical display tubes have an operating voltage of ap proximately 180-200 v. The voltage for controlling and operating the numerical display tubes is furnished by a known push-pull direct voltage inverter 7. The input side of the direct voltage inverter consists of the two terminals 71, 72, the two transistors T1 and T2 and the transformer primary winding 73.
The output side consists of the two secondary windings 74 and 75, of the transformer and the two rectifiers 76 and 77. At the output terminals 78 and 79 of the output side there are present direct voltages Ual and Ua2 over which alternating voltage pulses are superposed, the peak-to-peak amplitude of the alternating voltage being approximately 200 volts as compared to the direct voltage of approximately volts. The alternating voltage pulses serve as the shift signals for a shift register 50 consisting of a plurality of bit stages 51, 52, 53, 54, 55, 56,...,n and a memory 90, n being equal to the number of display tubes in the device. The memory 90 is connected to the terminal 79 of the push-pull inverter via a line 82 and is switched through the decades of the number to be displayed by the voltage pulses.
The information which is to be displayed by the tubes is stored in memory 90, this information having been delivered thereto from an external data source. The information is digitally interrogated by sequentially closing the contacts 00, 01, 02...09 of a memory interrogation switch 10 in synchronism with the readout from memory 90. Lines 61 lead from the contacts 00 to 09 of the memory interrogation switch to the respective cathodes 0 to 9 of the numerical display tube 101. The cathodes of the tubes which are associated with the same display number are connected in parallel by means of a line system 60. Cathode connection lines 61, 62, 63 lead from this line system 60 to the respective cathodes of the numerical display tubes. Since the cathodes for the same number are connected in parallel, one memory interrogation switch 10 is sufficient for all numerical display tubes.
The display of the memory contents in decades from tube to tube is controlled by the shift register 50 by shifting a pulse sequentially through its stages 51 to n. One stage of the shift register is provided for each numerical display tube.
Each of the combination voltages Ual and Ua2 applied to the output terminals 78 and 79 of the push-pull inverter is applied to the input of every other stage of the shift register, the stages connected to one terminal alternating with those connected to the other terminal.
To initiate a display, a starting pulse, indicated at 81, is delivered to the first stage 51 of the shift register from memory 90 over a line 80. This indicates that a series of digits is available for display by the tubes 101, 102, 103.... This first stage 51 is thus placed in a state to conduct voltage Ual to the anode 11 of the numerical display tube 101 and trigger it since, as already described, one of the cathodes 0-9 is suitably energized by the memory output through memory-interrogating switch 10.
The tube 102 similarly indicates the contents of the second decade of the memory. The subsequent tubes are switched on in decades by shifting pulses Ual and Ua2 which shift the shift register one stage at a time.
The interrogation process for memory 90 and the shifting of the shift register are automatically effected from decade to decade. After completion of the first display cycle, the display process is restarted by a new trigger pulse 81 so that the counter or shift register again begins to go through its operating cycle. With a sufficiently high display frequency, which is easily achieved, the observer will see a steady image.
FIG. 2 shows the circuit arrangement for several stages of a two-phase shift register 50. The combination voltages Ual and Ua2 of the direct voltage inverter, which are shifted in phase by with respect to one another, are applied from the output terminals 78 and 79 to stages 51-53 of the shift register. Because only one shift register stage is conductive at a time, only one numerical display tube is in a conductive state at any one time and the other tubes are extinguished. The starting pulse 81 turns the shift register on and renders the first stage 51 conductive. The shift register includes a thyristor Th for each stage and pulse 81 is applied to the triggering electrode of thyristor Th1 of stage 51 to render it conductive so that the anode 11 of tube 101 receives the then present positive pulse of the triggering voltage Ual. Tube 101 then triggers, after one of cathodes -9 has received a readout signal from the memory. To initiate operation of the device, pulse 81 must at least partially coincide with a positive pulse of voltage Ual.
FIG. 3 shows the memory interrogating switch of FIG. 2 in a more detailed manner. The memory consists preferably of four bistable circuits 85-88, connected with their inputs 91-98 to an external data source. The above mentioned line 82 is delivering impulses to the bistable circuits 85-88, whereupon information is taken over by the memory 90. At the same time new information is called for over a line 83. Line 83 and a line 84 for the supply of an impulse for the first information are connected over an AND-gate 89 to line 80. The outputs of the bistable circuits 85-88 are leading to the memory interrogating switch 10, consisting of a decoding matrix. The 10 outputs of the decoding matrix are each connected over a transistor 40-49 to the appropriate cathodes 61 62, 63 of the display tubes 101, 102, 103 by lines 60. The starting pulse 81, delivered by line 80 to the shift register 50, is synchronized with the impulses of line 82.
Thus, pulse 81 preferably occurs slightly before, or coincident with, the positive pulse of voltage Ual occurring, for example, during time period T designated in the waveform diagram associated with FIG. 2. The current flowing through thyristor Th1 after it has been rendered conductive and during the period T also charges capacitor C10 through diode D10, the final charge being determined in part by the value of resistor R10 connected in series with capacitor C10.
Capacitor C10 is connected to the triggering electrode of thyristor Th2 of stage 52 via a resistor R21 associated with a resistor R22 to form a voltage divider which determines the voltage applied to the triggering electrode upon discharge of capacitor C10. Capacitor C10 is connected to terminal 79 by a diode D21 poled to prevent the capacitor from discharging when voltage Ua2 has a zero, or at least a very low, value, as is the case during period T Then, at the beginning of the next pulse period T voltage Ual drops, permitting thyristor Th1 to return to its nonconducting state, and voltage Ua2 presents a positive pulse which permits capacitor C10 to discharge through resistor R21, thereby producing a triggering current which turns thyristor Th2 on. As a result, the positive pulse of voltage Ua2 is conducted to anode 21 of tube 102 to trigger that tube. At the same time the current flowing through thyristor Th2 charges capacitor C through diode D20 and resistor R20.
During period T memory 90 delivers information identifying the digit to be displayed by tube 102 while the contacts of switch 10 are sequentially closed to illuminate the selected tube cathode.
At the beginning of period T thyristor Th2 returns to its nonconductive state and the combined action of the positive pulse of voltage Ual and the charge on capacitor C20 renders thyristor Th3 of stage 53 conductive and place an operating potential on anode 31 of tube 103. Tube 101 can not then conduct because no triggering voltage is being applied to the triggering electrode of its thyristor Th1.
To illuminate the selected cathode of the tube whose anode is receiving a voltage pulse, memory 90 could be of a type which connects switch 10 to ground only when the contact associated with the desired number is closed. This could be achieved in any known way and simply requires the maintenance of the proper synchronism between the operation of switch 10 and the output signals from memory 90.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.
1. In a circuit device for controlling numerical display glow tubes and including means for producing a voltage sufficient to operate the tubes and switching means connected for applymg such voltage to each tube in succession, the improvement wherein said means for producing a voltage comprises an electronic inverter whose output is in the form of at least one train of spaced pulses and said switching means comprise control means connected for causing the pulses produced by said inverter to directly control the switching operations of said switching means.
2. An arrangement as defined in claim 1 wherein said switching means are constructed for applying the pulses produced by said inverter directly to each said tube in succes- 3. An arrangement as defined in claim 2 wherein said switching means comprise a plurality of thyristors each connected between said inverter and the anode of a respective one of said tubes.
4. An arrangement as defined in claim 1 wherein each said tube has a plurality of cathode connections each associated with a respective number and a single anode connection, and said switching means are arranged for applying the output pulses from said inverter directly to the anode of each said tube in succession and for switching the pulses from one said tube to the next under the direct control of the pulses produced by said inverter.
5. An arrangement as defined in claim 4 wherein said inverter is arranged for producing an output composed of an alternating square wave voltage and a superimposed direct voltage.
6. An arrangement as defined in claim 5 wherein said inverter is constituted by a push-pull direct voltage-altemating voltage inverter having two outputs each producing a signal composed of an alternating square wave voltage and a superimposed direct voltage, with the square wave component of one said output being shifted by with respect to that of the other output, and said switching means are connected to said outputs of said inverter for connecting one said output of said inverter only to every other one of said tubes and the other output of said inverter only to the intervening ones of said tubes.
7. An arrangement as defined in claim 5 wherein said switching means further comprises a plurality of trigger voltage generating elements each having an input connected to the anode of a respective one of said tubes and an output connected to the trigger electrode of the thyristor associated with the next succeeding one of said tubes for rendering the thyristor connected to the next succeeding one of said tubes conductive when an operating voltage pulse on said one of said tubes is terminated.
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|U.S. Classification||315/133, 315/260, 377/78, 315/315, 315/169.1, 377/54, 345/42, 377/112, 377/103|
|International Classification||H03K23/00, H03K21/00, G09G3/22, G09G3/04, H03K23/84, H03K21/08, G09G3/10|
|Cooperative Classification||H03K23/84, H03K21/08|
|European Classification||H03K21/08, H03K23/84|