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Publication numberUS3651489 A
Publication typeGrant
Publication dateMar 21, 1972
Filing dateJan 22, 1970
Priority dateJan 22, 1970
Publication numberUS 3651489 A, US 3651489A, US-A-3651489, US3651489 A, US3651489A
InventorsRobert C Beutel
Original AssigneeItt
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Secondary emission field effect charge storage system
US 3651489 A
Abstract
A secondary emission field effect charge storage system utilizing a combined NPN and P-channel field effect transistor device. The device includes a body of P-type semi-conductor material and a pair of bodies of N-type semi-conductor material respectively forming PN junctions with opposite sides of the P-type body in a first dimension thereby forming the NPN transistor, the P and N-type bodies forming the P-channel field effect transistor in a second dimension generally perpendicular to the first dimension. One of the N-type bodies has an outer surface having secondary emissive properties, and a collector electrode is provided for collecting secondary electrons emitted from that surface in response to electron bombardment thereof, with the surface thus having a positive charge stored thereon. A switching system is provided for respectively selectively making first, second and third electrical connections of the other of the pair of N-type bodies and the opposite ends of the P-channel transistor to predetermined potentials. The potentials are applied in the first connection to bias both the NPN transistor and the P-transistor to cut-off thereby to permit charge storage on the surface of the one N-type body. The potentials are applied in the second connection to bias the NPN transistor to cut-off and the P-channel transistor to below cut-off thereby to permit current flow in the P-channel, as modulated by the charge on the surface of the one N-type body to provide a read-out signal. The potentials are applied in the third connection to bias the NPN transistor into conduction and to bias the P-channel transistor to cut-off thereby to neutralize or erase the charge on the surface of the one N-type body.
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[451 Mar. 21, 1972 [54] SECONDARY EMISSION FIELD EFFECT CHARGE STORAGE SYSTEM Robert C. Beutel, Fort Wayne, Ind.

[73] Assignee: International Telephone and Telegraph Corporation, Nutley, NJ.

[22] Filed: Jan. 22, 1970 [21] Appl.No.: 5,024

[72] lnventor:

Primary Examiner-Stanley M. Urynowicz, Jr.

Attorney-C. Cornell Remsen, Jr., Walter J. Baum, Percy P. Lantzy, Philip M. Bolton, lsidore Togut, Charles L. Johnson, Jr. and Hood, Gust, Irish & Lundy [57] ABSTRACT A secondary emission field effect charge storage system utilizing a combined NPN and P-channel field effect transistor device. The device includes a body of P-type semi-conductor material and a pair of bodies of N-type semi-conductor material respectively forming PN junctions with opposite sides of the P-type body in a first dimension thereby forming the NPN transistor, the P and N-type bodies forming the P-channel field effect transistor in a second dimension generally perpendicular to the first dimension. One of the N-type bodies has an outer surface having secondary emissive properties,

' and a collector electrode is provided for collecting secondary electrons emitted from that surface in response to electron bombardment thereof, with the surface thus having a positive charge stored thereon. A switching system is provided for respectively selectively making first, second and third electrical connections of the other of the pair of N-type bodies and the opposite ends of the P-channel transistor to predetermined potentials. The potentials are applied in the first connection to bias both the NPN transistor and the P-transistor to cutoff thereby to permit charge storage on the surface of the one N- type body. The potentials are applied in the second connection to bias the NPN transistor to cut-off and the P-channel transistor to below cut-off thereby to permit current flow in the P-channel, as modulated by the charge on the surface of the one N-type body to provide a read-out signal. The potentials are applied in the third connection to bias the NPN transistor into conduction and to bias the P-channel transistor to cut-off thereby to neutralize or erase the charge on the surface of the one N-type body.

21 Claims, 12 Drawing Figures PATENTEDMARZI x972 3,651,489

SHEET 2 [IF 4 iNvENToR ROBERT c. BEUTEL BYX/mJ M,-M L M? ATTORNEYS SECONDARY EMISSION FIELD EFFECT CHARGE STORAGE SYSTEM I BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to charge storage systems of the type employed in image tubes, and more particularly to a secondary emission field effect charge storage system, and a secondary emission field effect charge storage element employed in such a system.

2. Description of the Prior Art readout,

Conventional storage-image tubes, such as the image orthicon which utilizes a multipled return electron beam readout employing a charge storage insulator which has a charge pattern formed thereon in response to impingement of an electron image from a photocathode, the insulator being scanned by an electron beam, the beam being returned to an electron multiplier which provides a time-based readout signal in response to the charge on each incremental portion of the insulator. Such scanning and electron beam return in the conventional image orthicon results in erasure of the charge pattern on the insulator, and further requires the usual deflection systems for the electron beam.

It is desirable toprovide a charge storage system usable in image tubes which provides readout without disturbing the charge pattern, and which further provides scanning without the necessity for generating and deflecting an electron beam.

SUMMARY OF THE INVENTION The invention basically provides semiconductor readout of electron images with scanning provided by solid state switching, eliminating the necessity for generating and deflecting an electron beam. The system improves the signal output over photodetectors, and does not require, other than the secondary emission bombardment on the image side, the high acceleration voltages of present readout systems.

In accordance with the broader aspects of the invention, a body of P-type semiconductor material is provided, and a pair of bodies of N-type semiconductor material are also provided respectively forming PN junctions with opposite sides of the P- type body in a first dimension thereby forming a NPN transistor, the P and N-type bodies forming a P-channel field effect transistor in a second dimension generally perpendicular to the first dimension. One of the N-type bodies has an outer surface having secondary emissive properties, and means are provided for collecting secondary electrons emitted from that surface in response to electron bombardment thereof, such as by the electron image from a photocathode, the surface of the one N-type body thus having a positive charge stored thereon. Switching means are provided for selectively making first, second and third electrical connections of the other of the pair of N-type bodies and the opposite ends of the P-channel transistor to predetermined potentials. The potentials are applied in the first connection to bias both the NPN transistor and the P-channel transistor to cutoff thereby to permit the charge storage. The potentials are applied in the second connection to bias the NPN transistor to cutoff and the P-transistor to below cutoff thereby to permit current flow in the P-channel, as modulated by the charge to provide a readout signal. The potentials are applied in the third connection to bias the NPN transistor into conduction and to bias the P-channel transistor to cutoff thereby to neutralize the charge on the surface of the one N-type body.

It is accordingly an object of the invention to provide a secondary emission field effect charge storage system.

Another object of the invention is to provide a solid state scanning device having storage capability.

A further object of the invention is to provide a combined NPN and P-channel field effect transistor device.

The above-mentioned and other feautres and objects of this invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of the embodiment of the invention taken in conjunction with the accompanying drawings, wherein:

v BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a fragmentary, cross-sectional, schematic view showing two of the charge storage devices of the invention together with the basic switching circuitry therefor;

FIG. 2 is a schematic diagram showing the equivalent circuit of one of the devices of FIG. 1 during the storage mode;

FIG. 3 is a schematic diagram similar to FIG. 2 showing the equivalent circuit during the readout mode;

FIG. 4 is a schematic diagram similar to FIG. 2 which shows the equivalent circuit during the erase or charge neutralization mode;

FIG. 5 is a cross-sectional view of an image tube incorporating the secondary emission field effect charge storage system of the invention;

FIG. 6 is a schematic view showing the secondary emission field effect mosaic with accompanying switching to provide raster scanning.

FIG. 7 is a schematic diagram showing diode matrices and pulse counting registers employed for performing the switching functions in the system of FIG. 6;

FIG. 8 is a fragmentary cross-sectional view similar to FIG. 1 but showing different means for making electrical contact to P and N elements;

FIG. 9 is a view diagrammatically showing a method of forming the P and N junctions to form the basic line elements;

FIG. 10 is a top view of the slice provided by the method shown in FIG. 9, view generally along the line 10-10;

FIG. 1 1 is a view showing a mask which may be employed in conjunction with the semiconductor slice of FIGS. 9 and 10 for diffusing the N gates; and

FIG. 12 is a view showing a mask which may be employed with the semiconductor slice of FIGS. 9 and 10 for depositing the ohmic contacts of FIG. 8 thereon.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1 of the drawings, there is shown a pair of secondary emission field effect charge storage elements 15 and 16. Each of the elements l5, 16 comprises a body 17 of P-type semiconductor material having parallel 0pposite sides 18, 19 which are spaced apart in a first dimension, as shown by the arrows 20. Body 17 has parallel opposite edges 22, 23 which are spaced apart in a second dimension perpendicular to dimension 20, as shown by the arrows 24.

A pair of N-type bodies 25 and 26 of semiconductor material are provided respectively forming PN junctions with the opposite sides 18, 19 of body 17 in the first dimension 20. In the illustrated embodiment, N-type bodies 25, 26 are diffused in the opposite sides 18, 19 of P-type body 17. As will hereinafter be more fully described, N-type bodies 25, 26 with portion 27 of the P-type body 17 therebetween form an NPN transistor in the first dimension 20. Further, N-type bodies 25, 26 and P- type body 17 form a P-channel field effect transistor in the second dimension 24, opposite edges 22, 23 of P-type body 17 forming the opposite ends of the P-channel.

A conductor 28-1 makes electrical contact with edge 22 of P-type body 17 of element 15, and has a lead 29-1 connected thereto. Lead 30-1 is connected to the lower N-type body 26. In this embodiment a third N-type body 32 of semiconductor material is provided forming a PN junction diode with edge 23 of P-type body 17 for preventing current flow in the P-channel in a direction opposite that of the load or readout current flow. Conductor 28-2 makes electrical contact with N-type body 32 and edge 22 of P-type body 17 of element 16, and has electrical lead 29-2 connected thereto. Lead 30-2 is electrically connected to the lower N-type body 26 of element 16, and conductor 28-3 having lead 29-3 connected thereto makes electrical contact with N-type body 32 of element 16 and edge 22 of P-type body 17 of an adjacent element 33.

The outer surface 34 of the upper N-type body is provided with secondary-emissive properties. In the illustrated embodiment upper surface 34 is shown as having a coating 35 of secondary emissive material thereon, such as magnesium oxide or silicon dioxide, however, it will be understood that the N-type material itself may have secondary-emissive properties.

A secondary electron collector electrode 36 is provided spaced from secondary emissive surfaces 35 and being adapted to be connected to a suitable source 37 of positive potential, such as 24 volts. Collector electrode 36 thus collects secondary electrons emitted from secondary-emissive surfaces 35 in response to electron bombardment thereof, such as by an extended area electron beam 38, thus leaving a positive charge on the secondary emissive surfaces 35, as shown.

Leads 29-1, 29-2 and 29-3 are respectively connected to the movable contact of double throw switches 39-1, 39-2 and 39- 3. Leads 30-1 and 30-2 are respectively connected to the movable element of double throw switches 40-1 and 40 2. Double throw switches 39 respectively have stationary contacts 42 and 43, and double throw switches 40 respectively have stationary contacts 44 and 45 as shown.

A source 46 of direct current potential is provided, shown in the illustrated embodiment as comprising batteries 47 and 48 having their positive and negative terminals, respectively, connected together and to ground 49, so that source 46 has a positive potential point 50, a negative potential point 52, a first intermediate potential point 53 (grounded in the illustrated embodiment). A second intermediate or reference potential point 54 is provided on battery 47 more negative than point 53. In a specific embodiment, batteries 47 and 48 may each provide twelve l 2) volts, thus providing a total of twenty-four (24) volts between positive potential point and negative potential point 52. In the specific embodiment, reference potential point 54 may be one and one-half (1%) volts below point 53.

A load resistor 55 is provided having one end connected to intermediate potential point 53 and its other end connected to stationary contacts 43 of switches 39, and to an output terminal 56. Negative potential point 52 is connected to stationary contacts 42 of switches 39, positive potential point 50 is connected to stationary contacts 45 of switches 40, and reference potential point 54 is connected to stationary contacts 44 of switches 40, as shown.

As is well known to those skilled in the art, by controlling the voltage applied to one or both of the N-regions of the P- channel field effect transistor, the current flow in the P-channel may be controlled down to the cutoff condition. Thus, and still referring to FIG. 1, assuming a positive charge, such as on the order of twenty (20) volts on the secondary emissive surface 35 and thus applied to the upper N-type region 25, and if the lower P-type region 26 or gate is held positive with respect to the potential applied to the upper N-type region 25, charge carriers in the P-channel will be pulled into the PN junction area leaving a depletion region of very high impedance, thus resulting in essentially zero current flow between the opposite ends 22, 23 of the P-channel. However, when the potential of the lower N-type body or gate 26 is reduced to a reference potential substantially lower than any charge potential applied to the upper N-type body or gate 25, the impedance of the P- channel is then controlled or modulated by the charge potential applied to the upper N-type gate 25, resulting in current flow through the P-channel between its opposite ends, that current flow in turn being modulated by the charge potential applied to the upper N-type gate.

In FIG. 1, the double pole switches 39 and 40 are shown in their respective positions for connecting the NPN and P-channel transistors in the storage mode. Considering element 15 and referring additionally to FIG. 2, it will be seen that switches 39-1 and 39-2 respectively connect the opposite ends of the P-channel to stationary contacts 42-1 and 42-2, and thus to the negative potential side 52 of source 46. Thus, both ends of the P-channel of element 15 are coupled to the same negative potential point 52 (the PN junction diode 32 is considered to be one end of the P-channel). Switch 40-1 connects lead 30-1 to stationary contact 45-1, thus connecting the lower N-gate 26 to the positive potential point 50.

Referring now to FIG. 2A, wherein the NPN transistor is schematically shown, it will be seen that the base, formed by the P-region 27, is negative, the emitter formed by the lower end-gate 26 is positive, there being a potential difference of 24 volts between the emitter and the base in the above-described specific embodiment, and thus that the NPN transistor is biased to cutoff with no emitter-to-base current flow therein, thus permitting the positive charge to accumulate on secondary emissive surface 35, which thus applies a positive potentia to the collector formed by the upper N-gate 25.

Referring to FIG. 2B, it will be seen that the two ends 22, 23 of the P-channel are at the same negative potential, thus making the P-channel 27 negative with respect to the N-gates 25, 26 which have a positive potential applied thereto, the P-channel current thus being cutoff.

In the readout mode, double throw switch 39-1 is moved to stationary contact 43-1 thereby to couple edge 22 of the P- channel to load resistor 55, double throw switch 40-1 is moved to stationary contact 44-1 thereby to couple the lower N-gate 26 to the reference potential point 54, and double throw switch 39-2 remains in contact with stationary contact 42-2 thus coupling the other ends 23 of P-channel to the negative potential point 52.

Referring additionally to FIG. 3A, it will be seen that the emitter of the NPN transistor is now connected to the slightly negative reference potential 54, a positive charge potential is still applied to the collector, and a negative potential (by reason of the voltage drop across load resistor 55) is applied to the base, thus resulting in the NPN transistor still being biased to cutofi' so that the charge on surface 35 is not drained off or neutralized. Referring to FIG. 38, with the potential applied to the lower N-gate 26 reduced to the reference potential 54 and with edge 22 of the P-channel now more positive than edge 23, current will flow in the P-channel through load resistor 55, that current being modulated by the charge applied to surface 35.

In the erase or charge neutralization mode, both double throw switches 39-1 and 39-2 contact stationary contacts 43- 1, thus coupling both ends 22, 23 of the P-channel to the load resistor 55, and double throw switch 40-] contacts stationary contact 44-1 to couple the 'lower N-gate 26 to the reference potential point 54. Referring now to FIG. 4A, it will be observed that with both ends 22, 23 of the P-channel connected to the same potential point, current flow through the P-channel will be cutoff and thus the potential applied to the P-channel will be essentially that of point 53, i.e., ground. The base of the NPN transistor is now biased positive with respect to the emitter so that the NPN transistor is biased into conduction or tumed-on so as to discharge or neutralize the charge on surface 35. Reference to FIG. 43 also shows this condition with zero current flow in the P-channel by virtue of connection of both ends 22, 23 to the same potential point 53 which is positive with respect to the lower N-gate 26.

It will now be seen that in the storage mode, a positive charge is accumulated on secondary emissive surface 35, that charge being proportional to the intensity of the incremental part of electron beam 38 impinging thereon. In the readout mode, current flows through the P-channel and through load resistor 55 which is modulated by the charge on secondary emissive surface 35, thus providing an output signal between output terminal 56 and ground 49 responsive to the magnitude of the charge. It will further be seen that during the readout mode, the charge pattern is not disturbed, thus permitting a number of readout operations. During the erase mode, the charge is neutralized thus permitting a new charge pattern to be applied to elements 15 and 16, and the other elements making up the complete secondary emission field effect mosaic to be hereinafter described.

Referring now to FIG. 5, a typical application for the secondary emission field effect charge storage elements abovedescribed is in an optical image sensor or image tube. Here, image type 57 is provided having an enclosing envelope 58 with spaced opposite ends 59 and 60. A matrix 62 of secondary emission field effect charge storage elements of the type above-described is supported on end 60 of envelope 58. A conventional photocathode 63 is deposited on end 59 and is connected to a suitable source of potential 64, such as ground. Secondary electron collector screen 36 is disposed in front of matrix 62, and a drift tube 65 extends generally between photocathode 63 and collector screen 36, drift tube 65 having an accelerating screen 66 extending across its end adjacent photocathode 63 and being connected to a suitable source of potential 67, such as plus 400 volts.

Photocathode 63 converts an input optical image to a corresponding electron image beam which is accelerated toward matrix 62 by accelerating screen 66. The electron image beam thus impinges upon secondary emissive surfaces 35 of the elements to matrix 62, the resultant secondary electrons being collected by collector screen 36 to provide the resultant charge pattern, as above-described. lmage tube 57 is thus similar to an image dissector, matrix 62 and the accompanying switching system as shown in schematic form in FIG. 1 and to be hereinafter more fully described, together with collector screen 36 replacing the apertured plate, electron multiplier and deflection yokes conventionally employed in an image dissector. It will be understood that a suitable focusing coil (not shown) will be required for focusing the electron image beam onto the matrix 62.

Referring now to FIG. 6, in order to form the matrix 62 of the secondary emission field effect charge storage elements as above-described, each of the P-type bodies is elongated in a third dimension mutually perpendicular to the first and second dimensions 20, 24, as shown by the arrows 72. Each of the elongated P-type bodies 17 has a plurality of pairs of upper and lower N-gates 25, 26 respectively forming PN junctions with its opposite sides 18, 19, the respective pairs being spaced-apart in the third dimension 72. Thus, P-channel 17-1 has upper N-gates -1, 25-2, 25-3, 25-n and corresponding lower N-gates 26, only the lower N-gate 26-1 being shown in H6. 6. Similarly, the adjacent P-type body 17-2 has upper N- gates 25-4, 25-5, 25-6,... 25-n thereon and corresponding lower N-gates, only N-gate 26-4 being shown. P-body 17-3 has upper N-gates 25-7, 25-8, 25-9, 25-n and corresponding lower N-gates 26, only N-gate 26-7 being shown. As will hereinafter be described, the corresponding pairs of upper and lower N-gates 25 and 26 form a row in each elongated P-type body 17, thus forming the line dimension for raster-type scanning, the pairs of N-gates 25, 26 also forming columns in adjacent P-type bodies 17, such as the pairs 25-1, and 26-1, 25-4 and 26-4, 25-7 and 26-7, 25-n and 26-n, thus forming the frame dimension for raster scanning. It will be seen that the contact elements 28-1, 28-2, 28-3, 28-4, 28!: are similarly elongated.

Here, the leads 30 extending from each lower N-gate 26 in the same column, such as leads 30-1, 30-4 and 30-7 of lower N-gates 26-1, 26-4 and 26-7 are connected together and to column leads 68, 69, 70, et seq.

Considering momentarily only common column lead 68, lead 68 is connected to the collectors of PNP transistor 72-1 and NPN transistor 73-1. The emitter of transistor 72-1 is connected to the positive point 50 of source 46, and the emitter of transistor 73-1 is connected to the reference potential point 54. Switch 40-1 selectively connects the positive potential point 50 and reference potential point 54 to resistors 74 and 75 which are respectively connected to the bases of transistors 72-1, 73-1. Lower N-gate column leads 69 and 70 are similarly respectively connected to transistors 72-2 and 73-2 and 72-3 and 73-3. With double throw switch 40-1 in the position shown connecting the reference potential source 54 to the bases of transistors 72-1 and 73-1, transistor 72-1 is biased into conduction or on and transistor 73-1 is biased out of conduction or off," thereby applying the positive potential 50 to the column of lower N-gates 26-1, 26-4, 26-7 to provide the storage connection thereto, as above-described. With switch 40-1 coupling the positive potential point 50 to the bases of transistors 72-1 and 73-1, transistor 72-1 is biased off and transistor 73-1 is biased on thereby applying the reference potential 54 to the column of lower N-gates 26-1, 26-4, 26-7, to provide the readout connection as described above.

Leads 29-1, 29-2 and 29-3 respectively coupled to the row or line contact elements 28-1, 28-2, and 28-3 are respectively coupled to the collectors of PNP and NPN transistors 76-1 and 77-1, 76-2 and 77-2, and 76-3 and 77-3, as shown. The emitters of PNP transistors 76-1, 76-2 and 76-3 are connected to load resistor 55, and the emitters of NPN transistors 77-1, 77-2 and 77-3 are connected to the negative potential point 52. Double throw switches 39-1, 39-2 and 39-3 selectively couple the intermediate or ground potential point 53 and the negative potential point 52 to resistors 78, 79 respectively connected to the bases of transistors 76 and 77, as shown. Considering only the line lead 29-1, with switch 39-1 coupled to the ground potential point 53, transistor 76-1 is biased off" and transistor 77-1 is biased on," thus coupling the negative potential point 52 to contact element 28-1, as in the storage connection above-described. With switch 39-1 connected to the negative lead 52, transistor 76-1 is biased on" and transistor 77-1 is biased off, thus connecting lead 29-] to the end of load resistor 55, as in the readout connection above-described.

Inspection of FIG. 6 will reveal that with switches 40-1 and 40-2 in the positions shown, the positive potential point 50 is coupled to the lower N-gates of the columns respectively connected to column leads 68, 69 thus providing the charge connection for all of the lower N-gates in those two columns.

With switches 39-1, 39-2 and 39-3 in the positions shown in FIG. 6, lead 29-1 and contact element 28-1 have the negative potential point 52 connected thereto, whereas lead 29-2 and contact element 28-2 has the end of load resistor 55 and thus the neutral point 53 connected thereto, ends 23 of the P-channels of the row of P-channel transistors formed in P-type body 17-1 thus being more positive than ends 22. However, provision of the PN diode 32 at end 23 prevents reverse current flow in the P-channels of row 17-1. Thus, by reason of the highly negative potential 52 applied to the bases of the NPN transistors in row 17-1, all of those transistors are biased to cutofi thereby being in the storage connection.

Referring now to the row defined by the P-type body 17-2, it will be observed that contact element 29-2 is coupled to the end of the load resistor 55 by virtue of the position of switch 39-2, while contact element 29-3 is coupled to the negative potential point 52 by virtue of the position of switch 39-3. Recalling now that the NPN transistors including upper N-gates 25-4 and 25-5 respectively have their lower N-gates 26 coupled to the positive potential source 50 by virtue of the positions of switches 40-1 and 40-2, those transistors are likewise still biased to cutoff and are thus in the charge storage connection. However, the lower N-gate 26-6 associated with the upper N-gate 25-6 is coupled to the reference potential point 54 by virtue of the position of switch 40-3 and thus, with contact element 29-2 being coupled to load resistor 55 and contact element 29-3 being coupled to the negative potential point 52, the P-channel associated with upper N-type body 25- 6 will be biased below cutoff thereby to provide a readout signal across load resistor 55 as modulated by the charge on surface 35 of the upper N-gate 25-6.

It will now be observed that for a given row 17 of charge storage elements, with the respective switches 40 in the position shown for switches 40-1 and 40-2, i.e., coupling the lower N-gates to the positive potential point 50, and with the respective switches 39 associated with the contact elements 28 at each end of the P-type body 17 in the positions shown for switch 39-1, i.e., with both contact elements 28-1 connected to the negative potential point 52, such elements will be biased so that the respective NPN and P-channel transistors are cutoff, the respective NPN and P-channel transistors in the given row 17 remaining cutoff despite the fact that the switch 39 associated with the contact element 28 which contacts the respective PN junction diode 32 is moved to the position shown for switch 39-2 in which contact element 28-2 is connected to load resistor 55. However, the readout connection is provided for a particular element when the switch 40 associated with a particular column of elements is moved to the position shown for switch 40-3 in which the lower N-gates 26 are connected to the reference potential 54, and the respective switches 39 associated with the contact elements 28 on either side of the particular charge storage element are in the positions shown for switches 39-2 and 39-3, i.e., coupling the contact element 28 which contacts edge 22 of the particular P-type body 17 to the load resistor and the contact element 28 contacting the other edge 23 (and the PN diode 32) to the negative potential point 52.

Finally, it will be observed that a particular charge storage element is connected for erasure when the switch 40 of its particular column is in the position shown for switch 40-3, i.e., connecting the lower N-gates 26 of that column to the reference potential 54, and when the switches 39 associated with the respective contact elements 28 are both in the positions shown for the switch 39-1, i.e., connecting both contact elements 28 to the load resistor 55 and thus to the neutral potential point 53.

it will now be readily seen that readout in raster scanning fashion may readily be provided for the matrix 62 by the switching system shown in FIG. 6. Thus, assuming that all of the switches 40 are normally positioned as shown for the switches 40-1 and 40-2 so as to connect all of the lower N- gates 26 of all of the columns to the positive potential point 50, and that all of the switches 39 are normally positioned as shown for the switches 39-1 and 39-3 thus connecting all of the contact elements 28 to the negative potential point 52, all of the charge storage elements comprising the matrix will be connected in the storage mode and may thus have a charge image impressed thereon. Now, if switch 39-1 is moved to its other position to connect contact element 28-] to the load resistor 55, with all of the other switches 39 remaining in their normal positions connecting their respective contact elements 28-2 to the negative potential point 52, the first row or line 17- 1 will be enabled. With this positioning of switches 39-1 and 39-2, sequential actuation of switches 40-1, 40-2, 40-3, et. seq., to the position shown for switch 40-3 in which the respective columns of lower N-gates 26 are sequentially connected to the reference potential point 54, the elements in the first line 17-1 will sequentially be connected in the readout mode thereby providing a sequential line-read-out signal across load resistor 55. When readout of the first line 17-1 has thus been accomplished and all of the switches 39 and 40 returned to their normal positions, moving switch 39-2 to its position shown in F IG. 6 thus to connect contact element 28-2 to load resistor 55 will enable the second row or line 17-2, and scanning of that line is accomplished in the same fashion by sequential actuation of the switches 40-1, 40-2, 40-3, et seq. It will thus be seen that sequential actuation of the switches 40 provides the line scanning function while sequential actuation of the switches 39 provides the frame scanning function.

- While manually actuated switches 39 and 40 have been shown in both FIGS. 1 and 6, it will be readily understood that solid state switching devices may be substituted therefor, and that the sequential actuation of the switches in the line and frame dimensions may be accomplished by a suitable pulse counting register.

Referring now to FIG. 7, a system is shown employing line and frame pulse counting registers 79 and 80 for providing the line and frame scanning sequences, and line and frame diode matrices 82 and 83 for respectively providing the switching functions of switches 40 and 39. A typical matrix 62 may include 512 line elements in 512 lines, i.e., 512 X 512. Line pulse counting register 79 is thus essentially a nine-bit binary counter comprising ten binary devices coupled in a binary counting chain, each device 85 having 1 and T outputs'86 and 87. A clock pulse generator 88 is coupled to the first binary device 85 in the chain for applying the actu ating clock pulses thereto. Diode matrix 83 couples the l and 1 outputs 86, 87 of the bistable devices 85 of the counter to the N-gates 84-1 through 84-512, each of the gates 84 comprising the transistors 72, 73 and the resistors 74, 75 above-described. It will thus be seen that the line pulse counting register 79 in conjunction with the diode matrix 82 will sequentially actuate gates 84 in response to the pulses provided by clock pulse generator 88, thus sequentially to apply the reference potential 54 to the lower N-gates 26 of the 512 columns of charge storage elements.

The 1 outputs 86 of the binary devices 85 of the line pulse counting register 79 are all coupled to an AND gate 89 which has its output circuit 90 coupled to the frame pulse pulse counting register 80. Thus, when the line pulse counting register 79 is full upon completion of a count of 5 l 2, all of the 1 output circuits 86 will have signals thereon resulting in the application of one clock pulse to frame pulse counting register 80. Thus upon completion of the scanning of one line by line pulse counting register 79 and diode matrix 82, frame pulse counting register 80 is advanced by one pulse thereby to enable the next line. 7

in order to initiate a readout scanning operation, recalling that all of the N and P gates 84 and 92 normally establish the storage connection, as above-described, it is necessary to apply one additional pulse to the frame pulse counting register 80 thereby to enable the first line. Thus, in order to initiate a readout scanning operation, a readout starting switch 93 couples a suitable source of potential 94 to enable clock pulse generator 88 and also to actuate one-shot multivibrator 95 to apply an initial pulse to the frame pulse counting register 80. Thereafter, so long as switch 93 is closed, the line and frame pulse counting register 79, 80 and their associated matrices 82, 83 will continue to scan the charge storage elements in raster fashion line after line and frame after frame.

If it is desired to provide for simultaneous erasure of all of the elements comprising the matrix 62, it is necessary to actuate each of the line and frame gates 84, 92 so as to connect all of the lower N-gates 26 in all of the columns to the reference potential 54, and all of the contact elements 28 of all of the lines to the load resistor 55. In order to accomplish this switching function, a plurality of AND gates 96 are respectively coupled to the crossbar lines 97 of matrix 82, a suitable.

source of potential 98 being applied to all of the gates 96. An erase switch 99 couples a suitable enabling signal source 100 to each of the AND gates 96, thereby applying to each of the matrix lines 97 a potential to bias transistor 72 off and transistor 73 on, thereby to apply the reference potential 54 to the respective lead 68. Frame matrix 82 includes comparable AND gates 96, erase switch 99 being coupled thereto by line 102 thereby to bias each of the transistors 76 on" and each of the transistors 77 off" so as to apply the neutral potential 53 to each of the contact elements 28.

Referring now to FIG 8, in which like elements are indicated by like reference numerals, it will be seen that the contact elements 28 of FIGS. 1 and 6 may take the form of line ohmic contacts 128, and that the common connections 68, 69,

70, et seq. to the lower N-gates 26 may likewise be provided by an ohmic contact 168 with suitable insulation 103 being provided to insulate the P-type body 17 and PN diode junctions 32 from the lower common contract 168.

Referring now to FIGS, 9 and 10, one method of forming a sheet 104 comprising the basic P and N bodies 17, 32 for the matrix 62 is shown. Here, a crystal 105 is formed by epitaxial deposition of P and N layers 106, 107, to form the basic line elements, one over the other, as shown, the requisite planar PN junctions'thus being maintained. The crystal 105 is then cut, as at 108, 109 to provide the sheet or slice 104 with its two sides or faces 18, 19.

In order to form the pairs ofipper and lower N-type bodies 25, 26, the opposite faces 18, 19 of the sheet 104 may be dyed to provide a duplicate picture of the surfaces, and a photo enlargement made, to whatever magnification is necessary, to provide a background upon which to draw masks which may be used to diffuse the N-gates and deposit the ohmic contacts 128. Such a mask 110 having portions 112 ultimately to provide the N-gates 25, 26 as shown in FIG. 11. After the mask 110 has been drawn upon the photo enlargement of the respective side of the sheet 104, it may then be reduced back to the size of sheet 104 and applied thereto, the N-gates 25, 26 then being diffused through the portions 112 into the P-lines 17. Mask 111 having line portions 113 thereon for depositing ohmic contact lines 128 may be formed in similar fashion.

It will now be seen that the secondary emission field effect charge storage system of the invention, when incorporated in an image tube, provides a nondestructive readout of the charge image stored therein, and rapid discharge of the charge image when desired. Further, the system of the invention, by utilizing solid state digital element sampling, completely eliminates deflection yokes and sweep generators, and provides a device having long life since no hot cathode or filament is employed. It will be understood that high power gain with low noise is provided due to the use of a field effect transistor principle, and that the overall camera tube can be small in size, with the element size likewise being small.

It will be observed that the signal provided by the P-channel current in the load resistor 55 is a maximum for minimum electron emission and a minimum for maximum electronic charge accumulation. This type of transfer function lends itself well to automatic latitude control where current flow is maintained constant and applied voltages are made to vary. It is thus seen that the dynamic range of the device is extended and a better signal-to-noise ratio is provided at low input levels. While raster-type readout scanning has been described in connection with FIG. 7, it will be readily understood that the system of the invention permits the use of other types' of scanning. It will further be understood that by employing digital selection of respective elements or groups of elements,

readout of any desired element or group of elements may' readily be provided.

While there have been described above the principles of this invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of the invention.

What is claimed is:

1. A secondary emission field effect charge storage system comprising: a body of P-type semiconductor material, a pair of bodies of N-type semiconductor material respectively forming PN junctions with opposite sides of said P-type body in a first dimension thereby forming an NPN transistor, said P and N- type bodies forming a P-channel field effect transistor in a second dimension generally perpendicular to said first dimension, one of said N-type bodies having an outer surface having secondary emissive properties; means for collecting secondary electrons emitted from said surface in response to electron bombardment thereof whereby said surface has a positive charge stored thereon; and switching means for respectively selectively making first, second and third electrical connections of the other of said pair of N-type bodies and opposite ends of the P-channel of said P-channel transistor to predetermined potentials.

2. The system of claim 1 further comprising a third body of N-type semiconductor material forming a PN junction with said P-type body in said second dimension for preventing flow of current in said P-channel in a direction opposite said firstnamed current flow, said switching means selectively connecting said other and third N-type bodies and a part of said P-type body on the side of said pair of N-type bodies remote from said third N-type body to said potentials.

3. The system of claim 1 further comprising a direct current source for providing said potentials, said source having positive and negative potential points, a first intermediate potential point, and a second intermediate potential point more negative than said first intermediate potential point, and a load resistor connected to said first intermediate potential point; said switching means in said first connection thereof coupling parts of said P-channel respectively on opposite sides of said pair of N-type bodies to said negative potential point, and said other N-type body to said positive potential point; said switching means in said second connection thereof coupling one of said P-channel parts to said load resistor, said other N-type body to said second intermediate potential point, and the other of said P-channel parts to said negative potential point; said switching means in said third connection thereof coupling both of said P-channel parts to said load resistor and said other N-type body to said second intermediate potential point.

4. The system of claim 3 further comprising a diode coupled in series with said other P-channel part for preventing current flow in said P-channel in a direction opposite that of said firstriamed current flow.

5. The system of claim 1 wherein said P-type body has first and second generally parallel opposite sides spaced-apart in said first dimension and first and second generally parallel opposite edges spaced-apart in said second dimension, said edges respectively forming the opposite ends of said P-channel, said first and second N-type bodies respectively forming PN junctions with said first and second sides, and further comprising first and second means for respectively making electrical contact with said first and second edges, and means for coupling said contact means to said switching means, said potentials being applied in said first connection to bias both said NPN transistor and said P-channel transistor to cutoff thereby to permit said charge storage, said potentials being applied in said second connection to bias said NPN transistor to cutoff and said P-channel transistor to below cutoff thereby to permit current flow in said P-channel as modulated by said charge to provide a readout signal, said potentials being applied in said third connection to bias said P-channel transistor to cutoff thereby to neutralize the charge on said surface,

6. The system of claim 1 wherein said P-type body is elongated in a third dimension mutually generally perpendicular to said first and second dimensions, and further comprising at least a second pair of bodies of N-type semiconductor material spaced from said first-named pair in said third dimension and respectively forming PN junctions with said opposite sides of said P-type body in said first dimensions thereby forming a second NPN transistor, said P-type body and said second pair of N-type bodies forming a second P-channel field effect transistor in said second dimension, the corresponding one of said second pair of N-type bodies having an outer surface having secondary emissive properties, said secondary electron collecting means also collecting secondary electrons emitted from said surface of said second pair of N-type bodies, said switching means also selectively making said first, second and third connections of the other of said second pair of N-type bodies and the P-channel of said second P-channel transistor to said predetermined potentials thereby respectively to provide charging of said surface of said one of said second pair of N-type bodies, a readout signal from said second P-channel, and neutralization of the charge on said last-named surface.

7. The system of claim 1 wherein said first-named body has spaced opposite edges generally parallel with said first dimensions and forming the opposite ends of said P-channel, and further comprising a second body of P-type semiconductor material, said second P-type body having a first dimension generally parallel with the first dimension of said first P-type body and a second dimension forming an extension of the second dimension of said first P-type body, a second pair of bodies of N-type semiconductor material respectively forming PN junctions with opposite sides of said second P-type body in its said first dimension thereby forming a second NPN transistor, said second P-type body and said second pair of N- type bodies forming a second P-channel field effect transistor in the second dimension of said second P-type body, said second P-type' body also having spaced opposite edges generally parallel with its first dimension and forming the opposite ends of said second P channel, first edges of said first and second P-type bodies being in juxtaposed relation, the corresponding one of said second pair of N-type bodies having an outer surface having secondary emissive properties, said secondary electron collecting means also collecting secondary electrons emitted from said surface of said second pair of N- type bodies, said switching means also selectively making said first,'second and third connections of the other of said second pair of N-type bodies and the P-channel of said second P- channel transistor to said predetermined potentials thereby respectively to provide charging of said surface of said one of said second pair of N-type bodies, a readout signal from said second P-channel, and neutralization of the charge on said last-named surface.

8. The system of claim 7 wherein the other one of both of said pairs of N-type bodies are connected together and to said switching means, said first edges of said first and second P- type bodies being connected together and to said switching means.

9. The system of claim 6 wherein said first P-type body has spaced opposite edges generally parallel with said third dimension and forming the opposite ends of said first and second P- channels, and further comprising a second body of P-type semiconductor material, said second P-type body having a first dimension generally parallel with the first dimension of said first P-type body and a second dimension forming an extension of the second dimension of said first P-type body, said second P-type body being elongated in a third dimension generally parallel with the third dimension of said first P-type body, at least third and fourth pairs of bodies of N-type semiconductor material respectively forming two pairs of PN junctions with opposite sides of said second P-type body in its first dimension and being spaced-apart in its third dimension thereby forming third and fourth NPN transistors, said second P-type body and said third and fourth pairs of N-type bodies respectively forming third and fourth P-channel field efiect transistors in the second dimension of said second P-type body, said second P-type body also having spaced opposite edges generally parallel with its third dimension and forming the opposite ends of said third and fourth P-channels, first edges of said first and second P-type bodies being in juxtaposed relation, said third and fourth pairs of N-type bodies being respectively spaced from said first and second pairs of N-type bodies in said second dimensions thereby forming a mosaic, the corresponding one of each of said third and fourth pairs of N-type bodies having an outer surface having secondary emissive properties, said secondary electron collecting means also collecting secondary electrons emitted from said surfaces of third and fourth pairs of N-type bodies, said switching means also selectively making said first, second and third connections of the other one of each of said third and fourth pairs of N-type bodies and the P-channels of said third and fourth P-channel transistors to said predetermined potentials thereby respectively to provide charging of said surface of said one of said third and fourth pairs of N-type bodies, readout signals from each of said third and fourth P-channels, and neutralization of said charges on said last-named surfaces.

10. The system of claim 9 wherein the other one of both of said first and third pairs of N-type bodies are connected together and to said switching means, the other one of both of said second and fourth pairs of N-type bodies being connected together and to said switching means, said first edges of said first and second P-type bodies being connected together and to said switching means.

11. The system of claim 9 wherein said switching means includes a diode matrix, and further comprising means for energizing said matrix to provide said second connections in a predetermined sequence.

12. The system of claim 9 wherein each of said NPN and P- channel transistors forms an element, the elements in each of switching means for sequentially actuating the same to provide said second connections for the elements of each line in succession thereby to provide said readout signals from said elements in line and frame raster fashion.

13. The system of claim 12 wherein said switching means includes first and second diode matrices, and further comprising first circuit means for connecting the other one of both of said first and third pairs of N-type bodies to said first matrix, second circuit means for connecting the other one of both of said second and fourth N-type bodies to said first matrix, said first matrix providing sequential switching of successive columns of the other ones of said pairs of N-type bodies to said second condition thereby providing line scanning, third circuit means for connecting the second edge of said first N-type body to said second matrix, fourth circuit means for connecting said first edges of said first and second P-type bodies to said second matrix, and fifth circuit means for connecting said second edge of said second P-type to said second matrix, said second matrix providing sequential switching of successive lines of said P-channels to said second condition thereby providing frame scanning.

14. The system of claim 13 wherein said actuating means comprises a first binary pulse counting register having at least first and second stages respectively coupled to said first and second circuit means, clock pulse generating means coupled to said first register for supplying pulses thereto, a second binary pulse counting register having at least three stages respectively coupled to said third, fourth and fifth circuit means, and means for coupling said first register to said second register for supplying a pulse thereto in response to each said line scan.

15. The system of claim 13 further comprising means for actuating both of said matrices to provide said third connection.

- 16. The system of claim 9 further comprising photocathode means for converting an optical image to an electron image, said photocathode means being spaced from said mosaic with said surfaces of said one of said pairs of N-type bodies facing said photocathode means, said collecting means being intermediate said surfaces and said photocathode means, and means for directing said electron image from said photocathode means toward said surfaces for impingement thereon.

17. A combined NPN and P-channel field effect transistor device comprising: a body of P-type semiconductor material having a wide dimension and a narrow dimension, a pair of bodies of N-type semiconductor material respectively forming PN junctions with opposite sides of said P-type body in said narrow dimension thereby forming an NPN transistor, a further N-type body spaced from said pair of bodies and extending transversely through said P-type body between said opposite sides, said P and N-type bodies forming a P-channel field effect transistor in said wide dimension generally perpendicular to said narrow dimension, and means for selectively applying predetermined potentials to opposite ends of said P- channel and to said N-type bodies whereby said device may be biased to function selectively as an NPN transistor and a P- channel field effect transistor.

18. The device of claim 17 wherein said means for applying a potential to one of said N-type bodies comprises an outer surface of said one N-type body having secondary electron emissive properties capable of storing a positive charge thereon in response to electron bombardment thereof.

19. The device of claim 17 wherein said further N-type body forms a PN junction with one end of said P-channel for preventing reverse current flow therein.

20. The device of claim 18 including means adjacent said outer surface for collecting secondary electrons emitted therefrom.

21. The device of claim 20 including switching means for selectively applying said potentials to obtain an output signal in accordance with said charge.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2754431 *Mar 9, 1953Jul 10, 1956Rca CorpSemiconductor devices
US3126505 *Nov 18, 1959Mar 24, 1964 Field effect transistor having grain boundary therein
US3482151 *Apr 10, 1968Dec 2, 1969Durand PaulBistable semiconductor integrated device
US3524113 *Jun 15, 1967Aug 11, 1970IbmComplementary pnp-npn transistors and fabrication method therefor
US3528064 *Sep 1, 1966Sep 8, 1970Univ CaliforniaSemiconductor memory element and method
US3543052 *Jun 5, 1967Nov 24, 1970Bell Telephone Labor IncDevice employing igfet in combination with schottky diode
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3737876 *Jun 16, 1971Jun 5, 1973Siemens AgMethod and device for scanning information content of an optical memory
US3751688 *Dec 23, 1971Aug 7, 1973Philips CorpErasing circuit for use in a display tube provided with a storage screen
US3860946 *Oct 13, 1972Jan 14, 1975California Inst Of TechnSpace-charge-limited solid-state triode
US4471378 *Dec 31, 1979Sep 11, 1984American Sterilizer CompanyLight and particle image intensifier
Classifications
U.S. Classification348/294, 365/174, 313/399, 313/391, 257/917, 327/208, 257/273, 257/E27.129, 365/118
International ClassificationH01J29/39, H01L27/00, H01L27/144, H01J31/26
Cooperative ClassificationH01L27/00, Y10S257/917, H01J29/39, H01J31/26, H01L27/1446
European ClassificationH01L27/00, H01J31/26, H01L27/144R, H01J29/39
Legal Events
DateCodeEventDescription
Apr 22, 1985ASAssignment
Owner name: ITT CORPORATION
Free format text: CHANGE OF NAME;ASSIGNOR:INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION;REEL/FRAME:004389/0606
Effective date: 19831122