|Publication number||US3659120 A|
|Publication date||Apr 25, 1972|
|Filing date||Jul 29, 1970|
|Priority date||Jul 29, 1969|
|Publication number||US 3659120 A, US 3659120A, US-A-3659120, US3659120 A, US3659120A|
|Original Assignee||Pioneer Electronic Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (3), Classifications (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Saeki 1 Apr. 25, 1972  SWITCHING CIRCUIT  References Cited  Inventor: Yoshlfumi Saeki, Tokyo, Japan UNITED STATES PATENTS  Assignee: Pioneer Electronic Corporation, Tokyo 2,572,179 10/ l 951 Moore .328/173 Japan 2,933,689 4/1960 Johnson. ....307/259 X Filed: y 1970 3,365,546 l/l968 Kemper ..l79/l5 W  Appl. No.: 59,168 Primary Examiner-Donald D. Forrer Assistant ExaminerB. P. Davis  Foreign Application Priority Data Attorney-Sughrue, Rothwell, Mion, Zinn & Macpeak July 29, 1969 Japan ..44/7i358  ABSTRACT [52} U.S. Cl ..307/253, 307/259 A switching circuit with two control terminals, one coupled to [51 int. Cl. ..H03k 17/00 the ba e of a transistor receiving input signals and the other to held Search --307/259; 328/99 173, 182; the emitter of the transistor. The switching circuit is operated such that when a positive potential is applied to one of the control terminals, a null potential is applied to the other.
3 Claims, 3 Drawing Figures SWITCHING CIRCUIT BACKGROUND OF THE INVENTION The invention is in the field of switching circuits and, in particular, to switching circuits which transmit or interrupt input signals in a signal transmission circuit. Such switching circuits find wide and varied use in the electronics art. A few examples are outlined below.
In receiver circuits, particularly in FM receiver circuits, muting circuits are utilized to block the operation of the audio frequency amplifier or the amplifiers in the IF stage during times when the receiver is untuned. Thus, the amplifiers are operated only during the time the receiver is tuned. Such operation results in the elimination of jarring noise at the output of the receiver generated during the intervals when the receiver is untuned. These muting circuits utilize switching circuits to accomplish the blocking operation.
In addition, transistor amplifiers utilize output transistor protection circuitry coupled to the output transistor to. protect this transistor from breakdown when its output terminals are shortened. Such output transistor protection circuitry includes means for automatically interrupting input signals when the output transistor is shorted. Switching circuits are here utilized to accomplish the blocking of the input signals.
A further type of circuitry where switching circuits are utilized is selection circuitry wherein a plurality of input signalsv are applied to a plurality of input terminals with the selection circuitry selecting the desired input signals. Such circuitry uses a switching circuit which permits a select number of input signals to pass while interrupting the other signals.
Prior switching circuits used in the above environment have included a coupling capacitor in the input circuit. These prior switching circuits suffer the disadvantage that when the coupling capacitor was made small, a loud click noise was generated each time the switching circuit was switched off to block input signals. One prior method of reducing the click noise involved making the capacitor large. However, such an approach caused the switching circuit, when it was turned on, to generate an output signal which progressively became smaller and distorted.
SUMMARY OF THE INVENTION The present invention alleviates the problems of the prior switching circuits by providing a switching circuit in which no click noise is generated at the interruption of an input signal while at the same time protects the input signal from becoming smaller and distorted when the switching circuit is turned on. To accomplish this, the switching circuit of this invention is provided with two control terminals, one coupled to the base of a transistor in the switching circuit and the other to its emitter. The circuit is operated such that when a positive potential is applied to one of the control terminals, a null potential is applied to the other.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a prior switching circuit,
FIG. 2 shows another prior switching circuit which is an improvement over the circuit shown in FIG. 1, and
FIG. 3 is a circuit diagram for a switching circuit in accordance with the teachings of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a representation of a prior switching circuit. An input signal is applied at terminal 1 to the base of the transistor TR, through a coupling capacitorC When the control terminal 2 is at a nullipotential, that is, a potential sufficient to forward bias diode D,,'the input terminal is shorted, thus preventing the input signal from appearing at the output terminal 3. When the'potential on terminal 2 is raisedso as to reverse bias diode D,, the input signal appears at the output terminal 3, providing the transistor TR, is properly biased by resistors R, and R, as is known in the art.
When the potential at terminal 2 is again dropped to the null potential, diode D, forward biases and thus capacitor C, discharges through the diode D,. When this occurs, transistor TR, is turned OFF and the signal on output terminal 3 disappears. However, if the capacity of capacitor C, is small, a large click noise is generated due to the fact that the potential at the output terminal 3 drops abruptly at the interruption of the input signal. If, on the other hand, the capacity of the capacitor C, is large, there is no click noise due to the fact that the potential at the base of transistor TR, drops gradually, thereby preventing an abrupt drop in the potential at the output terminal 3. However, if the capacitor C, is made large, as transistor TR, turns on, successively passing through class A, B, and C operation, the output signal becomes smaller and smaller and becomes more and more distorted.
A prior means which has been used to lessen the click noise is illustrated in FIG. 2. Like elements in FIGS. 1 and 2 are denoted by common numerals. In the circuit of FIG. 2, a resistor R, is added across the collector-emitter terminals of transistor TR,. In this manner, a constant bias voltage is applied to the output terminal 3. When an input signal is interrupted, the potential at the output terminal 3 does not become zero but instead drops to the bias potential determined by resistor R.,. Neither the circuits shown in FIGS. 1 nor 2 solve the problem associated with eliminating the click noise while at the same time assuring that the input signal does not slowly decay while becoming gradually distorted.
A switching circuit incorporating the teachings of this invention is illustrated in FIG. 3. Such a circuit provides for the elimination of the click noise while at the same time assures that the input signal does not become distorted or decay when the transistor TR, is turned on. Like elements in FIGS. 1, 2 and 3 are designated by common numerals. As in prior art switching circuits, input signals are applied to terminal 1 through a coupling capacitor C, to the base of the transistor TR,. A first control terminal 2 is coupled through diode D, to the base of the transistor TR,. Biasing resistors R, and R, provide proper operation of the transistor during those times when the control signal at terminal 2 reverse biases diode D,.
A second control terminal 4 is coupled through a time constant circuit, comprising resistor R and capacitor C and diode D to the output terminal 3 of the switching circuit. The time constant circuit is coupled to the output terminal 3 of the transistor TR, to assure that the output potential does not drop abruptly when the potential at terminal 4 drops to a null level.
Capacitor C, is made large so that the impedance does not become so large as to disrupt operation of the circuit for low frequency input signals. The potential at the base of transistor TR, drops at a rate determined by the time constant of the base circuit of which capacitor C, is the primary capacitance.
Operation of the invention will now be described with reference to FIG. 3. When diode D, is blocked due to a positive potential at control terminal 2, the input signal at terminal 1- is seen at the output terminal 3 of the transistor TR,. However, when the potential at terminal 2 drops to its null level, diode D, conducts thus blocking the input signal from the output terminal 3. When the control terminal 2 is at its null level, control terminal 4 is at a positive potential sufficient to forward bias diode D,. When this occurs, capacitor C, is charged, and the potential at the output terminal 3 becomes positive through the diode D,. When the potentials at control terminals 2 and 4 are reversed, that is, when the potential the control terminal 2 raises so as to block diode D, and the potential at control terminal 4 drops to back bias diode D,, the input signal is once again applied to the base of transistor TR, and thus to the outputterminal 3. I-lowever,.due to the charge stored in capacitor C the reversal of the potential at control terminal 4 does not cause an abrupt drop of the potential at terminal 3. Instead, the potential drops slowly determined by the time constant. of the RC circuit comprising capacitor C, and resistor R By properly selecting the time constants of the base and the emitter circuits of transistor TR the output at terminal 3 remains relatively constant even when the input signal to terminal l is blocked. That is, the time constants of the base and the emitter circuits are so selected that when the input signal is blocked, the capacitor C substantially charges to a DC value equal to the DC value of the input signal before the potential on capacitor C decays through diode D,. Similarly, when the input signal is unblocked, by reverse biasing diode D the potential across capacitor C discharges through R, at a rate such that capacitor C is charged before there is any substantial decay of the potential on capacitor C In this manner, the DC level of the potential at the output terminal 3 remains substantially constant regardless of whether or not the input signal is blocked from input terminal 1.
In summary, the present invention provides a switching circuit wherein there is provided control terminals for the base and the emitter circuits of a transistor in a switching circuit, the switching circuit being located along a signal transmission line. When a positive potential (or null potential) is applied to one of the control terminals, a null potential (or positive potential) is applied to the other. One of the control terminals provides a control signal for selectively interrupting an input signal applied to the input terminal signal. To the other control terminal, there is supplied a potential equal to the DC potential of the input signal. When the input signal is interrupted, this DC potential is supplied to the output terminal. The circuitry of the present invention further provides for the removal of the defect that, when the input signal is interrupted, the output signal gradually decays while being distorted, even though the time constant due to the coupling capacitor in the input circuit is made large enough to remove the clicking noise. This latter defect in prior circuits is corrected by'the addition to the circuit of means to keep the output signal at a substantially constant DC value at all times.
What is claimed is:
l. A switching circuit comprising:
a. a transistor in a signal transmission path, said transistor including a base, emitter and collector terminal,
b. a first control terminal connected to the base of said transistor,
c. a first diode connected between the first control terminal and the base of said transistor,
d. an output terminal connected to the emitter of said transistor, said output terminal being grounded through a resistor,
e. a second control terminal connected to said output terminal,
f. a second diode and a time constant circuit connected between said second control terminal and said output terminal, and
g. means connected to said first and second control terminals for selectively supplying a positive potential to one of said control terminals while simultaneously supplying a null potential to the other control terminal and for selectively supplying a positive potential to said other control terminal while simultaneously supplying a null potential to said one of said control terminals whereby, the D. C. potential at said output terminal is maintained at a substantially constant value irrespective of the presence or absence of an input signal.
2. A switching circuit comprising:
a. means, placed in the path of a signal transmission line, for
selectively passing an input signal,
b. an input terminal, connected to said means for selectively passing, for receiving said input signal,
c. an output terminal connected to said means for selectively passing,
d. a first control means connected to said input terminalfor selectively blocking said input signal from entering said means for selectively passing, and e. a second control means connected to said output terminal for supplyin a DC potential equal to the DC level of: said input signal 0 said output terminal when sald input signal is blocked and for removing said DC potential when said input signal is unblocked.
3. The switching circuit of claim 2, wherein said second control means includes a time constant circuit for maintaining said potential at said output terminal until said input signal, when unblocked, substantially reaches said DC level at said output terminal.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US2572179 *||May 24, 1949||Oct 23, 1951||Philco Corp||Peak leveling circuit|
|US2933689 *||Apr 4, 1958||Apr 19, 1960||Bendix Aviat Corp||Gated amplitude discriminator|
|US3365546 *||May 14, 1965||Jan 23, 1968||Collins Radio Co||Microphone bias supply for eliminating or reducing key clicks|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4198541 *||Feb 7, 1978||Apr 15, 1980||Hitachi, Ltd.||Signal holding circuit|
|US4403246 *||Nov 13, 1981||Sep 6, 1983||Rca Corporation||Vertical detail enhancement on/off switch|
|US6150852 *||Jan 14, 1999||Nov 21, 2000||Qualcomm Incorporated||Active differential to single-ended converter|
|International Classification||H03K17/16, H03F3/72, H03F1/30|
|Cooperative Classification||H03F3/72, H03F1/305, H03K17/16|
|European Classification||H03F1/30E, H03K17/16, H03F3/72|