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Publication numberUS3662191 A
Publication typeGrant
Publication dateMay 9, 1972
Filing dateJan 20, 1971
Priority dateJan 20, 1971
Publication numberUS 3662191 A, US 3662191A, US-A-3662191, US3662191 A, US3662191A
InventorsAley Albert H
Original AssigneeGte Sylvania Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory drive circuit
US 3662191 A
Abstract
Floating switch type of memory drive circuit having a transformer with the ends of the secondary winding connected to the base and emitter of a driving transistor. TTL NAND logic gates of the type having a pull-up transistor are connected to each end of the primary winding. When one of the gates is operated to produce a logic O at its output and the other gate is operated to produce a logic 1 at its output, the driving transistor turns on rapidly. When the operating states of the gates are subsequently reversed, the driving transistor turns off rapidly.
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I United States Patent [151 3,6 91 Aley 1 May 9, 1972 [5 MEMORY DRIVE CIRCUIT OTHER PUBLICATIONS [72] Inventor: Albert H. Aley, Holliston, Mass. Trinko, Modular Current Driver," IBM Technical Disclosure Bulletin, Vol. 9, No. 10, P. 1428, 3/1967. [73] Ass'gnee' GTE Sylvan Incorporated Cielo, Current Drive Circuit," IBM Technical Disclosure [22] Filed: Jan. 20, 1971 Bulletin, Vol. 9, No. 7, p. 932, l2/l966, [2]] pp. No: 108,090 Integrated Circuits," Sylvania Universal High Level Logic,

pgs. 4- I3 [52) U.S. Cl. ..307/270, 307/215, 307/242, P i E i r-Donald D. Forrer 328/60 Assistant E,\-aminer-L. N. Anagnos [51] II. Cl. ..H03k 3/02 A0rne. NOrman J. n Elmer J. Nealon and David [58] Field of Search ..307/240, 241, 242, 243, 215, M g,

307/236, 254, 270; 328/60, 6l, 116, ll7,118, I54;

340/173 FF 5? ABSTRACT [56] References Cited Floating switch type of memory drive circuit having a transformer with the ends of the secondary winding connected to UNITED STATES PATENTS the base and emitter of a driving transistor. TTL NAND logic 3,5 l9,85l 7/l970 Groner .307/270 X gates of the type having a pull-up transistor are connected to 3,466,462 9/l969 H nsom i --307/240 each end of the primary winding. When one of the gates is 19 H1966 h a] 307/25 X operated to produce a logic 0 at its output and the other gate 3,470,391 9/l969 Grallger "307/270 is operated to produce a logic I at its output, the driving 3522'444 8/1970 Loune "307/215 X transistor turns on rapidly. When the operating states of the 356076] 2/197! Kardash "307/25 gates are subsequently reversed, the driving transistor turns of? rapidly.

6 Claims, 3 Drawing Figures AB 0 DE FG HI JK on, 00 0B QD O O l I O l I l l l u of! 0" off 0 O O O l l I l I l l w off 0" Off 0 l l l l O l I l l oft 0" 0" O l O l l 0 l l l I OH QF F off 0" l 0 l l l l 1 0 l 0" 0H mi 0" l0 0 1| ll 0| ll 0" off Q F F 0" l l l l l l l l l l O oft o" o" O N llOllllllOloffotlofffi 0N FORWARD BIASING CURRENT FLOWS THROUGH TRANSFORMER OFF REVERSE BlASlNG CURRENT FLOWS THROUGH TRANSFORMER 0H= NO CURRENT FLOWS THROUGH TRANSFORMER PATENTEBMII 9m? 3.662.191

SIIIEI 1 III 2 CONTROL ERR! ABC DEFGHIJK QDL O0; 00;, Q04 00: IOII Q! on on off 00 0 0| l I I I l I OFF 0" O" o" OIIIIIOIIII at! gm of! 0| 0 II OI II I I OH QFF on on IOI IIIIIOII off oflgmon I 0 O I I I I OI I I 0" Off QFF off IIIIIIIIIIO offoffoflgg II 0 II II 0| on on on 2g 0N FORWARD BIASING CURRENT FLOWS THRouOH TRANSFORMER OFF REVERSE amsme CURRENT FLOWS THROUGH TRANSFORMER oH-NO CURRENT FLOWS THROUGH TRANSFORMER INVENTOR.

ALBERT H. ASHLEY AGENT PATENTEUMY 9 m2 3. 662. 191

SHEET 2 BF 2 Q N n a c: o g 0 o c! I 1 O -O m m IO m m N m n v m I D I m r0 ro r0 L ENABLE INVENTOR.

ALBERT H. ASHLEY AGENT MEMORY DRIVE CIRCUIT BACKGROUND OF THE INVENTION This invention relates to drive circuits. More particularly, it is concerned with circuits for rapidly turning on and turning of! the driving transistors of a memory drive line selection matrix.

Many memory systems employ the so-called "floating switch" type of memory drive circuit in which a transformer is employed to provide D.C. isolation between the driving transistor and the input address logic. The input address logic is connected to the primary winding of the transformer and the secondary winding of the transformer is connected across the input to the driving transistor. The input address logic, which is typically of the transistor-transistor-logic (TTL) type, provides sufiicient drive current through the primary winding of the transfonner to cause the driving transistor to be switched rapidly to saturation. However, when the input logic terminates current flow through the primary winding, only the stored energy in the secondary winding is available to turn the saturated driving transistor ofl'. Thus, the driving transistor turn-off time is relatively slow compared to the tum-on time.

Improvements in turn-off time can be obtained by employing pulse transformers specially designed for the particular input pulse conditions of the system. Another technique is the addition of inductors of suitable value across the secondary winding and transistor biasing resistance. However, these techniques are expensive and do not provide sufficient control of turn-off characteristics to obtain close agreement between the input and the output pulse widths.

SUMMARY OF THE INVENTION Rapid turn-off and turn-on of driving transistors is provided by drive circuits of the floating switch type in accordance with the present invention. A drive circuit according to the invention includes a transformer having a primary winding and a secondary winding. A first circuit means in the drive circuit includes a first pair of transistors with the collector of one transistor and the emitter of the other transistor connected to one end of the primary winding. A first input means is con nected to the transistors of the first pair and operates to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition during the occurrence of a first input condition at its input connection and operates to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at its input connection.

The drive circuit also includes a second circuit means which is similar to the first circuit means and includes a second pair of transistors with the collector of one transistor and the emitter of the other transistor connected to the other end of the primary winding of the transformer. A second input means is connected to the transistors of the second pair and operates to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition during the occurrence of a first input condition at its input connection and operates to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at its input connection.

Input data means is connected to the first and second circuit means and operates to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means in response to one set of input data being applied to it. The input data means operates to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means in response to another set of input data being applied to it.

The drive circuit also includes a driving transistor circuit means including a driving transistor having its emitter connected to one end of the secondary winding of the transformer and its base connected to the other end of the secondary winding of the transformer. The driving transistor circuit means operates to cause the driving transistor to conduct when a biasing voltage is present across the secondary winding of the transformer.

Thus, when the first input condition is applied at the input connection to the first input means and the second input condition is applied at the input connection to the second input means by the input data means, the one transistor of the first pair of transistors and the other transistor of the second pair of transistors conduct and current flows in one direction through the primary winding of the transformer inducing a forward biasing voltage across the secondary winding thereby causing the driving transistor to conduct. Subsequently when the first input condition is applied at the input connection to the second input means and the second input condition is applied at the input connection to the first input means by the input data means, the one transistor of the second pair of transistors and the other transistor of the first pair of transistors conduct and current flows in the opposite direction through the primary winding of the transformer inducing a reverse biasing voltage across the secondary winding thereby rapidly switching the driving transistor to non-conduction.

BRIEF DESCRIPTION OF THE DRAWINGS Additional objects, features, and advantages of drive circuits in accordance with the present invention will be apparent from the following detailed discussion together with the accompanying drawings wherein:

FIG. I is a schematic circuit diagram illustrating a drive circuit in accordance with the present invention;

FIG. 2 is a diagram illustrating several drive circuits of the type shown in FIG. I together with an exemplary input address logic arrangement; and

FIG. 3 is a truth table indicating the operating possibilities of the apparatus of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION The drive circuit in accordance with the present invention illustrated in the schematic circuit diagram of FIG. 1 includes an NPN driving transistor QD having its emitter and base connected to opposite ends of the secondary winding of a transformer 10. A biasing resistor R1 is connected between the base and emitter of the driving transistor OD. The collector and emitter are connected to terminals II and 12 which serve as the output terminals of the switch.

The two ends of the primary winding of the transformer 10 are connected to the output connections I5 and 16 of two similar circuits l3 and I4. These circuits may be typical TTL NAND logic gates of well-known type. The first circuit 13 includes a pair of NPN transistors 03 and Q4. The collector of one transistor 03 and the emitter of the other transistor 04 are connected directly to the output terminal 15. The emitter of the one transistor Q3 is connected directly to ground and the collector of the other transistor Q4 is connected through a resistance R5 to a positive source of voltage 3+.

The two transistors Q3 and Q4 of the pair are biased in conducting and non-conducting conditions by a biasing arrangement including an NPN coupling transistor Q2 having its emitter connected directly to the base of transistor 03 and through a resistance R4 to ground and having its collector connected through a diode D1 to the base of transistor 04 and through a resistance R3 to the BH- voltage source. When coupling transistor 02 is conducting, transistor O3 is biased to conduction and transistor O4 is biased in the non-conducting condition. When transistor Q2 is in the non-conducting condition, transistor O3 is also biased in the non-conducting condition and transistor 04 is biased in the conducting condition. The first circuit I3 also includes an NPN input transistor Q1 having its emitter connected to an input terminal 17, its collector connected directly to the base of the coupling transistor Q2, and its base connected through a resistance R2 to the B+ voltage source.

The first circuit 13 is a typical 'ITL NAND gate which in response to a relatively high input voltage at its input terminal 17 (designated a l logic level) biases the coupling transistor 02 to conduction thus causing transistor Q3 to be biased in the conducting condition and transistor O4 to be biased in the non-conducting condition. When a relatively low voltage is applied to the input terminal 17 (designated a O logic level) the base-emitter junction of transistor Q1 is forward biased and the voltage at its collector is such as to bias the coupling transistor Q2 to non-conduction. Under this condition transistor Q3 is biased in the non-conducting condition and the base of transistor Q4 is biased for conduction, depending upon conditions present at the output terminal 15.

The second circuit 14 is similar to the first circuit 13, having a second pair of NPN transistors Q7 and Q8 with the collector of one transistor Q7 and the emitter of the other transistor Q8 connected to the output terminal 16. A biasing arrangement of an NPN coupling transistor Q6, resistance R7, and resistance R8 establishes the biasing conditions at the bases of transistors Q7 and Q8. An NPN input transistor Q5 has its emitter connected to the input terminal 18. The coupling transistor O6 is biased into conduction or non-conduction depending upon the input signal voltage applied at the input terminal 18.

For illustrative purposes, the input terminals 17 and 18 of the first and second circuits l3 and 14, respectively, are shown connected to the output connections of a control circuit 19. The drive circuit of FIG. I operates in response to output signals from the control circuit 19 in the following manner.

When the control circuit 19 produces a relatively low voltage level (logic 0) on both terminals 17 and 18, the first and second circuits l3 and 14 operate to bias both transistors Q3 and O7 in the non-conducting condition, and both transistors Q4 and O8 in the conducting condition. Thus, no potential difference occurs across the output terminals and 16, or across the primary winding of the transformer 10. No current flows through the primary or secondary windings of the transformer l0 and the drive transistor QD does not conduct.

When the control circuit 19 produces a relatively high voltage level (logic 1) on both input terminals 17 and 18 of the first and second circuits l3 and 14, both transistors 03 and Q7 are biased in the conducting condition and both transistors Q4 and Q8 are biased in the non-conducting condition. Thus, no potential difference occurs across the primary winding of the transformer 10 and drive transistor QD does not conduct.

When the control circuit 19 switches from a previous operating state to produce a relatively high voltage level (logic l) at the input terminal 17 of the first circuit 13 and simultaneously a relatively low voltage level (logic 0) at the input terminal 18 of the second circuit 14, one or both of the two circuits l3 and 14 switches very rapidly to bias the one transistor Q3 of the first pair of transistors and the other transistor Q8 of the second pair of transistors to conduction. Current flows from the B+ voltage source of the second circuit l4 through transistor Q8, the primary winding of the trans former 10, and transistor 03 to ground. The flow of current through the primary winding induces a potential across the secondary winding which is in phase with the current flow in the primary winding. This potential across the biasing resistance Rl forward biases the base-emitter junction of the driving transistor QD causing that transistor to conduct and to provide a low impedance between its output terminals 11 and 12.

When the control circuit 19 subsequently reverses the conditions at the input terminals 17 and 18 producing the high voltage level (logic I) at the input terminal 18 of the second circuit 14 and the low voltage level (logic 0) at the input terminal 17 of the first circuit 13, the one transistor Q7 of the second pair of transistors and the other transistor Q4 of the first pair of transistors conduct. Current thus flows in the reverse direction from the B+ voltage source of the first circuit 13 through transistor 04, the primary winding of the transformer 10, and transistor O7 to ground. A voltage in phase with the current through the primary winding is induced across the secondary winding.

The induced voltage reverse biases the base-emitter junction of the driving transistor OD, and the charge stored in the transistor QD while it was operating in saturation is rapidly removed. The driving transistor QD is thus very quickly switched to non-conduction and a high impedance condition is established across the output terminals 11 and 12.

FIG. 2 is a diagram illustrating apparatus employing four drive circuits in accordance with the invention as'shown in FIG. 1 for producing bipolar output pulses at two output terminals 21 and 22 as determined by the address input data received at two address input data terminals A and B. The input data at a third input data terminal C controls the turnoff of the output pulses.

The data input terminals A, B, and C and an enable terminal 20 are connected to a binary to l-of-8 decoder 23. Relatively high voltage level signals (logic 1) or relatively low voltage level signals (logic 0) are applied to the input terminals A, B, and C. Depending upon the particular input signals at the three input terminals A. B, and C, during the presence of a relatively high voltage level (logic I) at the enable terminal 20, a relatively low voltage level condition (logic 0) is produced at one of the decoder output terminals D through K while a relatively high voltage level condition (logic I) is produced at the remaining seven of the decoder output terminals. Each of the gates 24 through 31 of the decoder is a TTL NAND gate similar to circuits l3 and 14 of FIG. 1. Each pair of gates 25 and 24, 27 and 26, 29 and 28, and 31 and 30 corresponds to the first and second circuits l3 and 14 of the drive circuit illustrated in FIG. I. The primary winding of a transformer 32, 33, 34, and 35, respectively, is connected between the output terminals of each pair of gates.

The secondary windings of each of the transformers 32, 33, 34, and 35 is connected between the base and emitter of N PN driving transistors 0D,, 0D,, OD and QB respectively. Biasing resistances 36, 37, 38, and 39, respectively, are connected across the secondary windings. The collector of driving transistor QD, is connected to a positive source of voltage, and its emitter is connected to the first output terminal 21 and to the collector of driving transistor DQD,. The emitter of driving transistor GB, is connected to a negative source of voltage. The collector of driving transistor QD, is also connected to a positive source of voltage, and its emitter is connected to the second output terminal 22 and to the collector of driving transistor OD The emitter of driving transistor QD, is connected to a negative source of voltage.

Operation of the apparatus of FIG. 2 may best be understood with reference to the truth table of FIG. 3. Data in the form of relatively low voltage level signals (logic 0) or relatively high voltage level signals (logic 1) are applied at the input terminals A, B, and C and also at the enable terminal 20 to control operation of the four driving transistors 01),, 0D,, QD and 0D,. Data at input terminals A and B determine which one of the four transformers 32, 33, 34 or 35 and associated driving transistor 0D,, 0D,, 0D,, QD is being addressed. Data at the third input terminal C controls the direction of current flow through the primary winding of the transformer addressed by the input data at terminals A and B.

For example, a high level input signal (logic I) at the A input terminal and a low level input signal (logic 0) at the B input terminal addresses the third transformer 34 and its associated driving transistor OD, through decoder terminals H and I. With the high level signal (logic 1) at the C input terminal and also at the enable terminal 20, the decoder terminals H and l have a high level (logic I) and low level (logic 0) voltage condition, respectively. Thus, current is caused to flow through the primary winding of the third transformer 34 in a direction to induce a biasing potential across the secondary winding. The third driving transistor QD conducts producing a positive-going pulse at the second output terminal 22.

When the input signal at the input data terminal C changes to a low level (logic 0), the operating conditions of the two NAND gates 28 and 29 are reversed and the output voltages at decoder terminals H and 1 become low (logic 0) and high (logie I), respectively. Current is caused to flow in the reverse direction through the primary winding of the transformer 34. This action causes a reverse current flow through the secondary winding of the transformer 34 rapidly discharging the stored charge in the previously saturated driving transistor OD and terminating the positive-going pulse at the second output terminal 22.

[n a similar manner if the input signals at the input data terminals A and B are both at the high level (logic l) and a high level signal (logic I) is present at the third input data terminal C and also at the enable terminal 20, a high level voltage condition (logic I) is produced at decoder terminal J and a low level voltage condition (logic 0) is produced at the decoder terminal K. Thus, current is caused to fiow through the primary winding of the fourth transformer 35 inducing a biasing voltage across the secondary winding and causing the fourth driving transistor QD to conduct. A negative-going pulse is produced at the second output terminal 22.

When the input signal at the third input terminal C is changed to the low level (logic 0). the operating conditions of the NAND gates 30 and 31 are reversed and the output voltages at the decoder terminals 1 and K change to the low level (logic 0) and high level (logic 1). respectively. This action causes current flow through the primary winding of the transformer 35 to be reversed. A reverse biasing voltage is induced across the secondary winding of the transfomier rapidly discharging the stored charge in driving transistor OD, and causing that transistor to become non-conducting. The negative-going pulse at the second output terminal 22 is thereby terminated.

Thus, the drive circuit as shown in FIG. 1 may be employed in apparatus such as that shown in FIG. 2 for providing driving pulses of either polarity. The two pairs of transistors connected to the opposite ends of the primary winding of the transformer and operating in alternation provide for rapid turn-0n and rapid turn-off of the driving transistor. Propagation delays through the circuit are approximately the same for turn-on and turn-off and thus the output pulse widths are in close agreement with the input pulse widths.

The apparatus may employ the individual circuits of Sylvania SUHL l SG-l series quad 2-input NAND/NOR gates as the TTL NAND gates. Each transformer may be a PE7709 pulse transformer produced by Pulse Engineering. Inc. The driving transistors may be 2N5262 NPN transistors. In the apparatus of FIG. 2 the decoder 23 may be a Sylvania SM-233 or Motorola MC 4006 binary to l-of-8 decoder.

While there has been shown and described what is considered a preferred embodiment of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined in the appended claims.

What is claimed is:

l. A drive circuit including in combination a transformer having a primary winding and a secondary winding;

a first circuit means including a first pair of transistors having the collector of one transistor and the emitter of the other transistor connected to one end of the primary winding,

a first input means connected to the transistors of the first pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition during the occurrence of a first input condition at the input connection thereto. and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto;

a second circuit means including a second pair of transistors having the collector of one transistor and the emitter of the other transistor connected to the other end of the primary winding,

a second input means connected to the transistors of the second pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition during the occurrence of a first input condition at the input connection thereto, and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto;

input data means connected to said first and second circuit means and operable to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means in response to one set of input data being applied thereto, and operable to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means in response to another set ofinput data being applied thereto;

driving transistor circuit means including a driving transistor having its emitter connected to one end of the secondary winding of the transformer and its base connected to the other end of the secondary winding of the transformer, said driving transistor circuit means being operable to cause the driving transistor to conduct when a biasing voltage is present across the secondary winding of the transformer; whereby when the first input condition is applied at the input connection to the first input means and the second input condition is applied at the input connection to the second input means by the input data means, the one transistor of the first pair of transistors and the other transistor of the second pair of transistors conduct and current flows in one direction through the primary winding of the transformer inducing a forward biasing voltage across the secondary winding thereby causing the driving transistor to conduct; and subsequently when the first input condition is applied at the input connection to the second input means and the second input condition is applied at the input connection to the first input means by the input data means. the one transistor of the second pair of transistors and the other transistor of the first pair of transistors conduct and current flows in the opposite direction through the primary winding of the transformer inducing a reverse biasing voltage across the secondary winding thereby rapidly switching the driving transistor to non-conduction.

2. A drive circuit in accordance with claim 1 wherein said first input means includes a first coupling transistor having its emitter connected to the base of the one transistor of the first pair of transistors and its collector coiinected to the base of the other transistor of the first pair and operable when in a conducting condition to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition and operable when in a non-conducting condition to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition, said first coupling transistor being biased to conduction during the occurrence of the first input condition at the input connection to the first input means and being biased to nonconduction during the occurrence of the second input condition at the input connection to the first input means; and said second input means includes a second coupling transistor having its emitter connected to the base of the one transistor of the second pair of transistors and its collector connected to the base of the other transistor of the second pair and operable when in a conducting condition to bias the one transistor in the conducting condition and the other transistor in the nonconducting condition and operable when in a non-conducting condition to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition, said second coupling transistor being biased to conduction during the occurrence of the first input condition at the input connection to the second input means and being biased to non-conduction during the occurrence of the second input condition at the input connection to the second input means. 3. A drive circuit in accordance with claim 2 wherein said first input means includes a first input transistor having its emitter connected to a first input terminal, its collector connected to the base of the first coupling transistor, and its base connected through a resistance to a first source of reference potential; the collector of the first coupling transistor and the collector of the other transistor of the first pair of transistors are connected to the first source of reference potential; the emitter of the one transistor of the first pair of transistors is connected to a second source of reference potential; said second input means includes a second input transistor having its emitter connected to a second input terminal, its collector connected to the base of the second coupling transistor, and its base connected through a resistance to the first source of reference potential; the collector of the second coupling transistor and the collector of the other transistor of the second pair of transistors are connected to the first source of reference potential; and the emitter of the one transistor of the second pair of transistors is connected to the second source of reference potential. 4. A drive circuit in accordance with claim 3 wherein all of said transistors are of the same conductivity type; and

the one end and the other end of the secondary winding of the transformer are in phase with the one end and the other end. respectively, of the primary winding. 5 Apparatus including in combination a first drive circuit in accordance with claim 1; a second drive circuit in accordance with claim 1; the collector of the driving transistor ofthe first drive circuit being connected to a third source of reference potential; the emitter of the driving transistor of the first drive circuit and the collector of the driving transistor of the second drive circuit being connected to an output terminal; the emitter of the driving transistor of the second drive circuit being connected to a fourth source of reference potential; whereby operation of the input data means of the first drive circuit to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means of the first drive circuit and then to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means of the first drive circuit produces a pulse of one polarity at the output terminal, and operation of the input data means of the second drive circuit to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means of the second drive circuit and then to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means of the second drive circuit produces a pulse of the opposite polarity at the output terminal.

6. Apparatus including in combination a first drive circuit in accordance with claim 3; a second drive circuit in accordance with claim 3; the collector of the driving transistor of the first drive circuit being connected to a third source of reference potential; the emitter of the driving transistor of the first drive circuit and the collector of the driving transistor of the second drive circuit bein connected to an output terminal; I the emitter of the rlving transistor of the second drive circuit being connected to a fourth source of reference potential of opposite polarity from said third source; the input data means of the first drive circuit and the input data means of the second drive circuit having common input data connections, the first input condition being produced at the input connection to the first input means and the second input condition being produced at the input connection to the second input means of the first drive circuit when a first set of input data is present at the common input data connections, the first input condition being produced at the input connection to the second input means and the second input condition being produced at the input connection to the first input means of the first drive circuit when a second set of input data is present at the common input data connections, the first input condition being produced at the input connection to the first input means and the second input condition being produced at the input connection to the second input means of the second drive circuit when a third set of input data is present at the common input data connections and the first input condition being produced at the input connection to the second input means and the second input condition being produced at the input connection to the first input means of the second drive circuit when a fourth set of input data is present at the common input data connections; whereby the presence of the first set of input data at the com mon input data connections and then the presence of the second set of input data at the common input data connections produces a pulse of one polarity at the output terminal, and the presence of the third set of input data at the common input data connections and then the presence of the fourth set of input data at the common input data connections produces a pulse of the opposite polarity at the output terminal.

* n 4 i n:

I 22%; UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,662,191 Dated May 9, 1972 Inventor-(s) Albert H. Ashley It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the heading (Item [72] Inventor) the inventor should be I Albert H. Ashley.

At column 4, line 44, "DQD should be -QD Signed and sealed this 5th day of December 1972.

(SEAL) Attest:

EDWARD M.FLETCI-IER,JR. ROBERT GOTISCHALK Attesting Officer Commissioner of Patents

Patent Citations
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Reference
1 * Integrated Circuits, Sylvania Universal High Level Logic, pgs. 4 13
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3914628 *May 13, 1974Oct 21, 1975Raytheon CoT-T-L driver circuitry
US3959671 *Jun 20, 1975May 25, 1976The United States Of America As Represented By The Secretary Of The NavyHigh current pulser circuit
US4011468 *Oct 1, 1975Mar 8, 1977Sperry Rand CorporationLow power clock driver
US4533989 *Mar 10, 1980Aug 6, 1985Sprague Electric CompanyTransformerless power inverter with only one type transistors
Classifications
U.S. Classification326/89, 326/128, 326/105
International ClassificationG11C11/02, G11C11/06, H03K19/018, H03K17/60
Cooperative ClassificationH03K17/601, G11C11/06007, H03K19/01825
European ClassificationG11C11/06B, H03K19/018C, H03K17/60C