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Publication numberUS3664294 A
Publication typeGrant
Publication dateMay 23, 1972
Filing dateJan 29, 1970
Priority dateJan 29, 1970
Publication numberUS 3664294 A, US 3664294A, US-A-3664294, US3664294 A, US3664294A
InventorsRaymond Solomon
Original AssigneeFairchild Camera Instr Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Push-pull structure for solution epitaxial growth of iii{14 v compounds
US 3664294 A
Epitaxial layers of III-V compounds are grown on the facing surfaces of a pair of parallel, spaced-apart wafers by forcing a small quantity of a solution saturated with a III-V compound between the wafers for a selected time. Lowering the temperature of the solution precipitates the III-V compound epitaxially onto the adjacent surfaces of the wafers.
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United States Patent Solomon [4 May 23, 1972 [5 PUSH-PULL STRUCTURE FOR [56] References Cmd SOLUTION EPITAXIAL GROWTH OF UNITED STATES PATENTS III-v Como 2,748,026 5/1956 Ogle ..1 18/503 X [72] Inventor: Raymond Solomon, Sunnyvale, Calif. 3,533,856 10/1970 Panish a 3,539,759 11/1970 Spiro et al..... [73] Asmgnec: .Falrchild Camera and Imtrument Cor- 3,551 219 12/1970 Banish t 1 p Mounwm View. Callf- 3,560,276 2/1971' Panish et al.-.. [22] Filed, Jan 29 1970 3,565,702 2/1971 Nelson 148/172 [21] Appl. No.: 6,819 Primary Examiner-John P. McIntosh Altqmey-Roger S. Borovoy and Alan H. MacPherson 52 us. 01 ..118/7, 118/9, 118/58, [57] I m 5 118/412, 118/415 [51] 1m. (:1. ..B05c 5/02, B05c 11/10 m III-V 'wmlmmd8 fficmg [58] Field 01 Search ..1 18 401, 412, 415, 315, 503, Pan f by a I 4 6 7 9 SP small of-a solution saturated Wllh 8 compound 273 between the wafers fora selected time. Lowering the temperature of the solution precipitates the Ill-V compound epitaxially onto the adjacent surfa'ces of the wafers.

6 Claims, 16 Drawlng Figures PATENTEDMAY 23 I972 SHEET 1 [1F 4 FIG.IA l0 I N VENTOR.


sum 3 0F 4 FIG.6

' g 500 I I g 400 f I FEGBA FIG.8B FIG.8C F|G.8D



F/ v W 4 4 J3 l \1 V 12 v 5 s 2% m,\%\ 4 INVENTOR. RAYMOND SOLOMON a Mflm ATTORNEY PUSH-PULL STRUCTURE FOR SOLUTION EPITAXIAL GROWTH OF III-V COMPOUNDS BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the epitaxial growth of III-V compounds and in particular to the epitaxial, controlled growth of gallium arsenide or gallium phosphide in such a manner as to precisely control the thickness of the epitaxially grown layer.

2. Prior Art Usually the Nelson Tilt Technique, described in volume 24 of the RCA Review, page 603 1963), is used to grow epitaxial gallium arsenide or other gallium compounds from gallium solutions. To grow gallium arsenide by this technique, a gallium arsenide wafer is clamped at one end of a boat by means of a clamp, such as a spring clamp or a carbon screw; in the other end of the boat is placed a small quantity of gallium, typically on the order of l grams, together with a small piece of gallium arsenide, added to saturate the gallium which is molten at growth temperature of around 700-800 C. The boat is placed in a furnace. Once the melt is saturated at the growth temperature, the furnace is tilted so that the gallium flows over the wafer. At the same time, the furnace temperature is decreased at a programmed rate, usually about C. per hour. As the temperature decreases, the gallium arsenide in solution becomes supersaturated and precipitates epitaxially onto the wafer.

The Nelson Tilt Technique has several disadvantages. First, it requires a movable, tiltable furnace.

Second, because of surface tension, the molten gallium containing the saturated gallium arsenide varies from very thin at the edge of the gallium arsenide wafer to very thick at the middle of the wafer. Since the temperature of gallium on the wafer is influenced by gas streaming over its surface, the thermal gradients in the gallium are non-uniform, resulting in rough epitaxial surfaces on the wafer and poor electrical characteristics in the resulting epitaxially grown layer.

Third, the spring clamp or screw severely distorts the adjacent growth of the epitaxial layer. This distortion extends over a large fraction of the wafers surface area. This distortion, together with the distortion due to the variable thickness of the gallium on the wafer, results in at least 50 percent of the surface area of the epitaxially grown layer being unusable.

A final disadvantage of the Nelson Tilt Technique is that once the furnace is tilted and the temperature begins to decrease, the gallium will not easily flow off the gallium arsenide wafer. Thus the epitaxial growth process, once started, cannot be stopped until all the gallium arsenide in solution precipitates out onto the gallium arsenide wafer. Consequently, once growth starts, growth continues from the starting temperature, typically 700 C., down to a temperature where the growth ceases, typically 500 C. With the commonly used 10 C. per hour drop in temperature, epitaxial growth runs are about hours long. Furthermore, if the gallium arsenide epitaxial layer is being simultaneously doped, the segregation coefficients of the impurities in the liquid gallium are strong functions of temperature. Consequently, the resulting epitaxial layer contains impurity gradients resulting from this temperature dependence of the segregation coefficient.

Thus, the Nelson Tilt furnace, while suitable for certain types of epitaxial growth processes, is not suitable for growth of precisely controlled, thin, epitaxial layers.

A second technique of epitaxially growing gallium compounds is called the vertical dip" technique. To grow gallium arsenide epitaxially using this technique, the gallium melt, containing gallium arsenide in solution, is held in a crucible. A gallium arsenide wafer, held vertically, is dipped into the gallium melt, held there for a selected time proportional to the thickness of the desired epitaxial layers to be grown on the two faces of the wafer, and then removed. Although conceptually simple, this technique also has problems.

One is that the electrical characteristics of the epitaxially grown layers are of poorer quality than the similar characteristics of the epitaxial layers grown by the Nelson Tilt Technique. Furthermore, gallium globs stick to the surface of the wafer as the wafer is removed from the molten gallium and thus cause uneven growth spots on the wafer surface. Also, control over the epitaxial layers thicknesses is very poor because of convection currents in the large volume of gallium in the crucible. These convection currents vary the concentration of impurities in the gallium and consequently result in uneven and graded impurity concentrations in the resulting epitaxially grown layers on the wafer. Indeed, the gallium arsenide concentration is usually greater at the top of the gallium melt than at the bottom of the melt so the wafer tends to be thicker in those regions held at the top of the gallium melt.

SUMMARY OF THE INVENTION This invention substantially overcomes these disadvantages of the prior art. Epitaxial layers of gallium arsenide and other III-V compounds grown in accordance with this invention possess precisely controlled thicknesses and substantially homogeneous and uniform impurity distributions. Using the technique and structure of this invention, the epitaxial growth process can be terminated at any desired time without continued uncontrolled growth due to globs of impurity-saturated, liquid gallium forming on the surface of the wafer. Moreover, the technique and structure of this invention are particularly amenable to the growth of epitaxial layers on a large number of wafers simultaneously. Automatic processing techniques are particularly useful with this invention.

According to this invention, epitaxial layers are grown on a wafer, typically a gallium arsenide wafer, by first placing the wafer in a recessed slot in the bottom of a horizontal floor of a jig. Molten gallium, containing source gallium arsenide when the wafer is gallium arsenide, is then placed in a cavity in a runner resting on the bottom of the jig. This cavity extends through the runner from its top to its bottom. Next, the jig containing the wafer and the runner is heated to a desired temperature, typically 700800 C. When the desired temperature is reached, it is held constant for a period, typically two hours, while the source gallium arsenide goes into solution and saturates the gallium. The runner is then slid along the jig, forcing the gallium into the space on top of the wafer. The furnace temperature is then dropped at a selected rate, thereby to precipitate the semiconductor, such as gallium arsenide, out of the gallium onto the topvof the underlying wafer. The semiconductor grows epitaxially on the wafer. After a selected time has elapsed, the runner is slid back off the wafer, thereby cleanly removing the gallium melt from the wafer surface. Because the runner can he slid on and off the wafer at any time, epitaxial layers can be grown to any selected thickness, from a few thousand angstroms on up to several microns or greater.

One embodiment of this invention places a second wafer in a slot on the upper inside face of the jig. As the runner is slid into the jig to place the molten gallium over the wafer in the bottom of the jig, the second wafer in the top of the jig stays in place and the gallium is forced into the space between the wafers. When the cavity directly overlies the wafer in the bottom portion of the jig, this second wafer directly overlies the melt at the top of the runner cavity, and indeed, is pressed by the heavier gallium into the slot recessed into the top of the jig. Upon removal of the runner from the jig, this wafer is held in the recess in the top of the jig. Thus in this embodiment, epitaxial layers can be grown simultaneously on two wafers.

The jig design of this invention is such that a plurality of jigs can be stacked in a furnace allowing the simultaneous growth of a large number of epitaxial layers on selected wafers. The runners can, if desired, be automatically inserted into, and withdrawn from, the corresponding jigs allowing precise control of the epitaxial growth.

DESCRIPTION OF THE FIGURES FIGS. la through 10 show side, top and end views of the boat of this invention;

FIG. 1d shows an isometric, cutaway view of the boat of this invention;

FIGS. 2a and 2b show cross-sectional, schematic, exploded views of the runner and jig of this invention;

FIGS. 3 through 5 show cross-sectional schematic views of the relationship of the jig and runner during various stages of the process of this invention;

DETAILED DESCRIPTION As shown in top, side, and end views in FIGS. 1a through It, in schematic, cross-sectional view in FIGS. 20 and 2b, and in isometric cutaway view in FIG. 1d, the structure of this invention consists of three pieces. Bottom piece 26 contains a recessed slot 23 for receipt of a wafer. Slot 23 faces into chamber 24 and is located directly beneath a similarly recessed slot 22 in top piece 25 of the jig. The edges of both slots 23 and 22 are undercut, as shown, to hold securely a wafer. Bottom piece 26 and top piece 25 together comprise the jig.

The third piece, runner 11, contains cavity 12 which extends through the runner from its top to its bottom surface. As shown in FIGS. 1d and 2c, runner 11 rests initially on the outermost portion of bottom 26. The jig and runner together are called a boat." A typical boat is about 3.5 inches long, 0.875 inches wide, and 0.5 inches high. Bottom piece 26 and top piece 25, when joined, have a U-shaped cross section, as shown, with bottom 26 being substantially longer than top 25.

Typically, all pieces of boat 10 are made of an inert, heat resistant material to withstand the high temperatures employed in the growth of epitaxial semiconductor layers and to minimize impurities transferred from boat 10 to the molten solution contained in cavity 12. Graphite and fused quartz are two materials suitable for use in boat 111.

The use of the structure shown in FIGS. 1a through 1d will be described in conjunction with the simultaneous growth of epitaxial layers on two wafers. The structure of this invention can alternatively be used to grow only one epitaxial layer at a time. While the process described will involve the epitaxial growth of gallium arsenide, the structure of this invention can be used to grow epitaxially other III-V compounds.

As shown schematically in FIG. 3, gallium arsenide wafer 32 is placed in recess 23 in the bottom 26 of jig 21. Gallium arsenide wafer 31 is placed in recess 22 in top 25 ofjig 21. The cutaway sides of the recesses help hold these wafers in place. (For simplicity, some parts of boat 10 numbered in FIGS. 2a and 2b are not numbered in FIGS. 3 to 5.)

Next, melted gallium 41 is placed in cavity 12 of runner 11. A piece of gallium arsenide is also placed in cavity 12. When the gallium 41 is heated to a temperature at which the gallium arsenide contained therein is all dissolved and saturates the gallium, runner 11 is pushed into chamber 24 of jig 21, as shown in FIG. 4. Gallium arsenide is lighter than gallium. Thus gallium arsenide wafer 31 is pressed by gallium 41 up into recess 22.

When runner 1 1 is as far as it can go into chamber 24, gallium 41 is directly above wafer 32 (FIG. 4). Because gallium 41 is saturated with gallium arsenide, a slight decrease in temperature results in gallium arsenide precipitating out of gallium 41. This precipitated gallium arsenide grows epitaxially in layers on the exposed surfaces of wafers 31 and 32. By dropping the temperature in the furnace at a selected rate, typically 10 per hour, epitaxial layers are grown on the two exposed surfaces of wafers 31 and 32. The thicknesses of the resulting layers are a function of the time wafers 31 and 32 are left in contact with gallium 41.

When the desired thickness epitaxial layers have been grown on wafers 31 and 32, runner 11 is removed from chamber 24 as shown in FIG. 5. Wafers 31 and 32 remain in their recessed slots during the removal of runner 11. Portion 13 of runner 11 cleans all molten gallium from the surfaces of wafers 31 and 32 during the removal of runner 11.

FIG. 6 shows a typical temperature versus time curve for the above-described process. Gallium 41 is placed in cavity 12 of runner 11 together with a source of gallium arsenide. Jig 21 and runner 11, together with gallium 41, are heated to a selected temperature, typically around 700 C. Then at time T runner 11 is slid into chamber 24 so that gallium 41 rests over wafer 32 and under wafer 31. The temperature is then decreased at a uniform rate until time T At this time, the desired thickness epitaxial layer has been grown. Runner 11 is then immediately drawn out of chamber 24 thereby sweeping all gallium 41 from contact with the surfaces of wafers 31 and 32. Consequently, epitaxial growth stops immediately on all portions of these surfaces.

The advantages of growing a wafer pair in the manner of this invention are numerous. First, the two wafers are located symmetrically on opposite sides of the gallium. Hence temperature gradients parallel to the epitaxially grown films on the two wafers are substantially reduced relative to the gradients present in the prior-art techniques. Second, the geometry of the gallium is defined by the wafer spacing rather than by surface tension, thereby resulting in better reproducibility of the epitaxially grown layers than heretofore obtaina ble.

The temperature profile across the molten gallium between the two wafers is close to an ideal temperature gradient as shown in FIG. 8a. The gallium temperature is a maximum in the middle of the gallium equidistant from the two wafers and drops as one approaches either wafer due to the slightly lower furnace temperature. The temperature gradient in the gallium using prior-art techniques is shown in FIG. 8b. This gradient is taken along center line of the gallium wafer shown in FIG. 8a. Because the thickness of the gallium 81 varies with respect to the position on wafer 82 at which one measures this thickness, the temperature gradient through the gallium 81 varies with this position in order to satisfy the substantially constant temperature boundary condition at the surface of gallium 81. On the other hand, because of the uniform spacing between the two wafers placed in boat 10, as shown in FIG. 8c, the thickness of gallium between the two wafers is substantially uniform resulting in a substantially uniform temperature gradient throughout the gallium. This results in quite uniform growth of an epitaxial layer on the two exposed surfaces of the wafers in boat 10.

Before proceeding with the epitaxial growth process of this invention, the jigs and furnace tube must be thoroughly cleaned and outgassed. This cleaning and outgassing can be accomplished by techniques well known in the semiconductor arts. The furnace system itself must be leak tight and oxygen free to ensure growth of pure epitaxial layers. Preparation of The wafer surfaces is very important. The surfaces should be etched or chemically polished prior to epitaxial growth. The wafer surfaces must be oxide and dust free.

The molten gallium should be saturated with the source semiconductor at high temperature. If gallium arsenide is the source semiconductor, the saturation can occur at about a 900 C. temperature for 3 to 5 hours. This ensures that the source gallium arsenide goes into solution and bakes out both the gallium and the gallium arsenide to volatilize trace impurities. If excess gallium arsenide is used, the baking out process need be done only once every 10 to 20 runs.

Smooth epitaxially grown layers are more easily obtained on the wafers if the gallium solution is slightly supersaturated before pushing the gallium between the wafers. supersaturation can be achieved by rapidly dropping the furnace temperature immediately before or after insertion of runner l 1 into jig 21.

FIG. 7 shows a structure for automatically implementing the technique of this invention. A furnace 91 contains therein a plurality 94-1 through 94-n of boats identical to the boat shown in FIGS. 1-6. These boats, schematically shown as stacked, each can contain one or two wafers, for example gallium arsenide wafers, upon the exposed surfaces of which are to be grown epitaxial layers of selected thicknesses. Each boat contains an associated one of runners 98-1 through 98-n, all runners being attached to a drive rod 97 which in turn is connected to the interior face of a steel bellows 94. Bellows 94 prevents oxygen and other contaminants from entering the furnace, while allowing rod 97 to be moved so as to drive runners 913-1 through 98-n into their corresponding jigs.

A programmable controller 93 receives signals representing the temperature in furnace 91. When this temperature reaches the proper level for initiation of epitaxial growth, a signal is transmitted to motor 92. Motor 92 drives runners 98-1 through 98-n into their corresponding jigs by means of cam 96, rods 95 and 97, and bellows 94. Upon the elapse of a given time, programmable controller 93 sends a second signal to motor 92 indicating the completion of epitaxial growth. Motor 92 is driven so as to withdraw runners 98-1 through 98-n from their corresponding jigs.

In one version of the boat 10 shown in FIGS. 1a through 1d, the bottom portions of the sides of runner 11 are angled in toward each other to occupy grooves cut in the adjoining surfaces of bottom piece 26. Thus, the sides of runner 1 1 grip the adjoining faces of bottom piece 26 as runner l1 slides between bottom and top pieces 26 and respectively. This prevents runner 11 from lifting slightly off bottom piece 26 while being moved into and out of chamber 24.

FIG. 9 shows an embodiment of this invention in which runner 71 contains two cavities, cavities 74 and 75. The structure shown in FIG. 9 is particularly useful in growing an epitaxial layer of a first conductivity type on a wafer, and then, immediately thereafter, an additional epitaxial layer of an opposite conductivity type on the first epitaxial layer. The boat of FIG. 9 contains as before, a top piece 72, which rests on top of. and fits into, a bottom piece 73, and a runner 71. To load cavities 74 and 75 in runner 71 with molten gallium plus source impurities and dopants, top piece 72 is removed from bottom piece 73. To grow on a gallium phosphide wafer first an N-type epitaxial layer followed immediately by a P-type epitaxial layer, gallium together with a source of gallium phosphide plus an N-type impurity such as tin or tellurium is placed in cavity 75. In cavity 74 is placed gallium together with gallium phosphide source material and a P-type impurity, such as silicon or germanium. Other P-type impurities used with III-V compounds include zinc or cadmium. However, these two impurities are not particularly suitable for this application because their high vapor pressures make it possible for their vapors to travel through the gas stream and contaminate the N -doped gallium in cavity 75.

Initially, runner 71 is pulled by means of pull rod 79 so that the molten gallium plus source material and N-type impurities in cavity 75 rest between wafers 31 and 32. After a desired thickness of an N-type gallium phosphide epitaxial layer has been grown on the exposed faces of wafers 31 and 32, runner 71 is slid back such that the P-doped gallium together with gallium phosphide source material in cavity 74 rests adjacent the exposed faces of wafers 31 and 32. Epitaxial growth continues for a selected time period until the desired thickness P-type epitaxial layers have been grown on these two wafers. Then runner 71 is again slid back so that center portion of runner 71 rests adjacent wafers 31 and 32, thereby cleanly terminating the epitaxial growth process. Thus two adjacent oppositely doped epitaxial layers are grown on each of two gallium phosphide wafers using the structure shown in FIG. 9. This structure can, of course, be used to grow such layers on a single wafer, if desired. For growing single wafers, the top piece can be left ofi, and the wafer placed in the bottom groove. This can be done for either the double cavity design of FIG. 9, or the single cavity design of FIG. 1.

To grow gallium phosphide using the techniques of this invention, a gallium melt is saturated with phosphine, typically at 1,060" C. The temperature is then dropped about 10 C. to insure that the melt is saturated or slightly super-saturated with gallium phosphide. Next, the melt is placed adjacent the surface or surfaces of one or two wafers, as shown in FIG. 2a through FIG. 5. The gallium temperature is then dropped at a rate between 10 C./hr and l00 C./hr. The rate is controlled by the crystal quality desired and the type of impurity desired to be incorporated in the resulting epitaxially grown gallium phosphide. When the solubility of an impurity is limited in gallium phosphide, often more impurity can be placed in the gallium phosphide by growing the gallium phosphide layer at higher rates. The thickness of the epitaxially grown gallium phosphide layer is proportional to the total temperature drop of the gallium adjacent the wafer.

Prior to placing the gallium phosphide wafers in the boat, the exposed surfaces of the wafers are chemically etched and polished. Likewise, the boat itself, together with the furnace tube, must be thoroughly cleaned and outgassed as in the preceding discussion relating to the epitaxial growth of gallium arsenide.

The epitaxial growth of gallium phosphide and particularly of doped layers of gallium phosphide, is particularly important to achieve visible light emitting devices. To obtain the emission of green light, gallium phosphide layers are epitaxially grown with N-type impurities such as sulphur and nitrogen in a concentration of about l0 /cc for sulphur and IO /cc for nitrogen. To obtain the P-type side of the junction, a zinc dopant to a concentration of 10" to l0 /cc is used.

To obtain red light-emitting gallium phosphide devices, an epitaxial layer of gallium phosphide containing N-type impurities such as tellurium to a concentration of IO /cc is first formed. An adjacent epitaxial layer containing P-type impurity formed from zinc and oxygen to a concentration of 5 lO"/ cc and l0"/cc respectively, is commonly used.

It should be noted that in the green light-emitting device, both sulphur andnitrogen must be present in the N-type epitaxial gallium-phosphide layer while in the red lightemitting device, the P-type layer must have both zinc and oxygen present simultaneously.

What is claimed is:

1. Structure which comprises:

means for holding two wafers in parallel, spaced-apart relation, said means for holding comprising a jig containing a spaced-apart bottom and top with a chamber therebetween, said bottom and said top each containing a recess facing said chamber for receiving a wafer, said recesses being selectively alligned; and

means for placing a first selected material adjacent to the facing surfaces of said two wafers comprising a runner capable of being slid into and out of said chamber, said runner possessing a cavity for containing said first selected material, said cavity being located in and extending through said runner so as to be adjacent to said recesses in said bottom and said top during the times said runner is fully inserted into said chamber.

2. Structure as in claim 1 wherein said runner possesses a second cavity, located in and extending through said runner, for containing a second selected material, said second cavity being located in said runner in such a manner that said second cavity is capable of being placed adjacent said recesses in said bottom and said top.

3. Structure as in claim 1 wherein said jig and said runner are made of graphite.

4. Structure as in claim 1 wherein said jig and said runner are made of fused quartz.

5. A system for the automatic growth of epitaxial layers on wafers, which comprises means for heating;

a plurality of boats stacked one on top of another in said means for heating, each boat comprising a jig containing a spaced-apart bottom and top with a chamber therebetween, said bottom and said top each containing a recess facing said chamber for receiving a wafer, said recesses being selectively aligned; and

a runner selected to slide into and out of said chamber, said runner possessing a cavity for containing a selected fluid, said cavity being located adjacent said recesses in said bottom and said top when said runner is fully inserted into said chamber; and

means for inserting automatically said runners into said jigs in response to a signal indicating that the temperature in said means for heating has reached a certain value, and for withdrawing automatically said runners from said jigs when said temperature has dropped to a selected lower value.


means for measuring the temperature in said means for heating and for producing a signal indicative thereof;

bellows means, attached to one end of said means for heating, including a first drive means linking the interior of said bellows to each runner, for moving each runner into and out of its corresponding jig, and a second drive means linking the exterior of said bellows means to a drive motor, for actuating, through said bellows means, said first drive means, and

means, responsive to signals from said means for measuring, for actuating said drive motor at a first time so as to move each runner into its corresponding jig, and for actuating said drive motor at a second time so as to move each runner out of its corresponding jig.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2748026 *Mar 26, 1953May 29, 1956Libbey Owens Ford Glass CoMethod and apparatus for thermal evaporation
US3533856 *Jul 17, 1967Oct 13, 1970Bell Telephone Labor IncMethod for solution growth of gallium arsenide and gallium phosphide
US3539759 *Nov 8, 1968Nov 10, 1970IbmSusceptor structure in silicon epitaxy
US3551219 *May 9, 1968Dec 29, 1970Bell Telephone Labor IncEpitaxial growth technique
US3560276 *Dec 23, 1968Feb 2, 1971Bell Telephone Labor IncTechnique for fabrication of multilayered semiconductor structure
US3565702 *Feb 14, 1969Feb 23, 1971Rca CorpDepositing successive epitaxial semiconductive layers from the liquid phase
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3753801 *Dec 8, 1971Aug 21, 1973Rca CorpMethod of depositing expitaxial semiconductor layers from the liquid phase
US3791887 *Jun 28, 1971Feb 12, 1974Gte Laboratories IncLiquid-phase epitaxial growth under transient thermal conditions
US3804060 *Jun 28, 1972Apr 16, 1974Sperry Rand CorpLiquid epitaxy apparatus
US3853643 *Jun 18, 1973Dec 10, 1974Bell Telephone Labor IncEpitaxial growth of group iii-v semiconductors from solution
US3889635 *Jul 3, 1974Jun 17, 1975Siemens AgApparatus for producing epitaxial layers
US3933123 *Dec 19, 1974Jan 20, 1976U.S. Philips CorporationLiquid phase epitaxy
US3936328 *Oct 15, 1974Feb 3, 1976Mitsubishi Denki Kabushiki KaishaProcess of manufacturing semiconductor devices
US4110133 *Apr 21, 1977Aug 29, 1978The Post OfficeGrowth of semiconductor compounds by liquid phase epitaxy
US4159694 *Jul 19, 1978Jul 3, 1979Rca CorporationApparatus for depositing epitaxial semiconductor from the liquid phase
US4263064 *Feb 19, 1980Apr 21, 1981The United States Of America As Represented By The Secretary Of The NavyMethod of liquid phase epitaxial growth
US4401487 *Nov 14, 1980Aug 30, 1983Hughes Aircraft CompanyLiquid phase epitaxy of mercury cadmium telluride layer
US4468258 *Jul 22, 1982Aug 28, 1984Licentia Patent-Verwaltungs-GmbhMethod of controlling the partial pressure of at least one substance mixture or mixture of substances
US4578126 *Jun 22, 1983Mar 25, 1986Trw Inc.Liquid phase epitaxial growth process
US4702781 *Oct 15, 1985Oct 27, 1987Matsushita Electric Industrial Co., Ltd.Liquid phase epitaxial growth method
US20020137877 *Dec 7, 2001Sep 26, 2002Debruin Bruce RogerLow cost polyester process using a pipe reactor
WO1982001671A1 *Oct 21, 1981May 27, 1982Barbara Res Center SantaProcess and apparatus for growing mercury cadmium telluride layer by liquid phase epitaxy from mercury-rich melt
U.S. Classification118/666, 257/E21.117, 117/61, 118/58, 148/DIG.490, 148/DIG.107, 118/415, 118/412
International ClassificationH01L21/208, C30B19/06
Cooperative ClassificationY10S148/107, C30B19/063, Y10S148/049, H01L21/2085
European ClassificationC30B19/06H, H01L21/208C