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Publication numberUS3665496 A
Publication typeGrant
Publication dateMay 23, 1972
Filing dateMay 20, 1970
Priority dateMay 23, 1969
Publication numberUS 3665496 A, US 3665496A, US-A-3665496, US3665496 A, US3665496A
InventorsDonjon Jacques
Original AssigneeSfim
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electrical signal sampling device
US 3665496 A
In a sampling device for receiving simultaneously several electrical signals at different inputs and successively sampling them in predetermined order, there is provided a priming gate for each input, the priming gates being controlled in succession by a ring counter such that the samples taken from each input appear in succession at a single output.
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Description  (OCR text may contain errors)

United States Patent Donjon 1451 May 23, 1972 ELECTRICAL SIGNAL SAMPLING References Cited DEVICE UNITED STATES PATENTS [721 Jacqu Pans Fran 2,662,175 12/1953 Staal ..328/104 [73] Assignee: Societe de Fabrication d'llistruments de 3,015,806 1/ 1952 Wang et 37 Maggy, France 3,184,663 5/ 1965 Mergler ..307/225 3,229,115 1/1966 Amarel ..328/104 led: May 20, 1970 3,280,309 10/1966 Villwock... .....307/223 3,461,313 8/1969 Hansen ..307/273 [21] Appl. No.. 39,690 3,517,175 6/1970 Williams... ..328/37 [30] Foreign Application Priority Data Primary Exami' 'er Dnald Forte! Asszstant Examiner-R. E. Harr May 23, 1969 France ..6916900 Attorney-Ireitenfeld & Levine 52 us. c1. ..307/251, 307/223, 307/304, ABSTRACT 328/43 In a sampling device for receiving simultaneously several elec- [51 Int. Cl. trica] signals at different inputs and successively Field of Search them in predetermined order, there is provided a priming gate for each input, the priming gates being controlled in succession by a ring counter such that the samples taken from each input appear in succession at a single output.

5 Claims, 2 Drawing Figures PATENTED MAY 2 3 I972 SHEET 1 [IF 2 Amanda 1:

PATENTEDMAY 23 m2 sum 2 OF 2 Fia- 2 ELECTRICAL SIGNAL SAMPLING DEVICE The present invention relates to an improved sampler.

A sampler is a device receiving simultaneously several electric signals at different inputs, taking successively, in a predetermined order, samples" of the value of these electric signals, in order to provide on its single output an output signal carrying these samples in the predetermined order.

The present invention provides a sampler of this type comprising for each input, a priming gate making it possible to connect the corresponding input to the output, and a ring counter controlling the successive opening of the priming gate according to a predetermined cycle in such a way that the samples taken on the different inputs appear on the output following this cycle.

In a preferred embodiment of the device according to the invention, each priming gate comprises one control input; at least two of the inputs of adjacent priming gates controlling the taking of samples, being able to be connected to each other in a detachable manner in order to introduce synchronization information into the output signal of the device.

In a preferred embodiment of the device according to the invention, the priming gates are field effect transistors comprising a control, the control being connected to a source of electrical supply through the intermediary of a diode connected in a direction such that the transistor does not allow any signal to pass in the absence of this supply.

For a better understanding of how the present invention may be realized, there will be described hereafter, as a nonlimiting example, a preferred embodiment of the sampler according to the invention, with reference to the accompanying drawings in which:

FIG. 1 shows diagrammatically the sampler according to the invention; and,

FIG. 2 shows the electric signals appearing at various points of the diagram of FIG. 1.

The sampler of FIG. 1 comprises eight inputs 1 to 8 to which there are applied the electric input signals intended to be sampled and an output 9 at which the output signal carrying the samples appears.

ln order to carry out the sampling of input signals priming gates 10 to 17 are associated with respective inputs and control the connections between the corresponding inputs and a common line 18 connected to the output 9.

In the example illustrated the priming gates are field-effect transistors comprising a source S, a drain D and a control electrode P, the source S being connected to an input of the sampler and the drain D to the common line 18. The state of conduction or non-conduction of the transistor is controlled by the application of electric signals on its control electrode P in known manner.

In accordance with the invention, these control signals are provided by a ring counter 19 in such a way that the priming gates are each brought into a state of conduction in their turn according to a predetermined order. It can be seen that in the state of conduction, each transistor applies to the common line 18 an electric signal substantially identical to that which is on the corresponding input and for the duration of this condition. There thus appears at the output 9 samples of each of the input signals, each sample being identified within a cycle by its position.

The ring counter 19 is constructed for example of J-K flipflops 20 to 27.

Each of these trigger circuits comprises two synchronous inclock inputs of the different trigger circuits or bistable circuit. In addition, the input K and the output Q of the same bistable circuit are connected to each other such that the bistable circuit returns to its previous condition after being triggered. ln addition, the output Q of a bistable circuit is connected to the input 1 of the following bistable circuit such that this latter is in turn triggered.

In FIG. 2 the output signals at respective Q's are shown illustrating successive triggerings. The output 29 of the last bistable 27 is connected by a lead to the input 30 of the first bistable circuit 20.

The signal coming from the outputs 6 of the bistable circuits is used to control the conditions of conduction or non conduction of the transistors 10 to 17. In order that there is a separation between the gates released by the transistors, the control signals from the bistable circuits are divided by a clock signal H (Identical to the clock signal H in logic gates NOT-OR" 31 to 38, the clock signal H being applied at 39.

The result of this is that the signals delivered by the different transistors on the common lead 18 are those shown on FIG. 2. It can be seen that in fact samples at only the inputs 1 to 6 are taken, the input 7 being connected to a predetermined D.C. voltage (for example of +2V) and the control electrodes of the transistors 16 and 17 being connected to each other by a detachable bridging connection or jumper 40. The input 8 may provide the D.C. voltage (for example +2V) in order to serve as a synchronization signal; in addition, the control signal coming from the bistable circuit 26 is not chopped by the clock signal H since one of the inputs of the gate NOT- OR 37 has no connection. At the output of the gate 37, there is thus a gate pulse of length identical to that coming from the bistable circuit 26, such that the two transistors 16 and 17 are simultaneously conducting without there being any direct interconnection. Further there appears a normal gate pulse at the output of the following gate 38, which still keeps the two transistors in a state of conduction. There is thus obtained on the output 9 a gate pulse of triple the length of a normal gate pulse, this said synchronization gate pulse serving to indicate the end of a sampling cycle.

At the end of this cycle, the gate pulse appearing at 29, is fed to an external circuit (not shown) including an inverter in order to provide a signal at the input 41 in order to re-set'to zero (RAZ) all the bistable circuits except the last one 27. This re-setting to zero takes place by firstly means of the clock signal H, opening a gate 42 to pass the gate pulse from the inverter and then by applying simultaneously to the RAZ inputs of the bistables 20 to 26 the signal thus passed. This re-setting to zero is carried out in order to eliminate cases which could arise where one of the bistable circuits is in the one" condition.

In order to start the sampler a signal for resetting to one is applied to the input 43 which is connected to the RAU input (re-set to one) of the bistable circuit 27 and on the input 41 for resetting the other bistable circuits to zero.

The terminals 44 and 45 are respectively connected to the and poles of a source of direct current. There have not been shown, for the sake of clarity of the drawing, the leads from these terminals to the transistors.

The terminal 46 is connected to the substrates of the transistors. According to an important feature of the invention, a diode 47 is connected between the substrates and the positive supply terminal 44 in order to prevent a transistor from allowing a signal, which is applied to it, to pass, when no positive voltage is present on the terminal 44.

The device is made so that it may be connected by simple connection to another identical device in order to be able to sample a greater number of input signals.

For this reason, the output 29 of the ring counter 19 is not permanently connected to the input 30; in this manner one can connect the output 29 to the input of another ring counter and make a connection between the output of this other counter and the input 30. Also for this reason, the bridge 40 connecting the grids of the transistors 16 and 17 is removable.

The removal of the bridge 40 and the applications at the terminal 48 of the gate 37 of the clock signal H suppresses the synchronization gates. In this case, an identical bridge is placed on the control electrodes of the two latter transistors of the other identical device.

A logic AND" gate 50 for controlling the interconnection and operated by the clock signal H puts a similar auxiliary gate in a conducting condition (not shown in FIG. 1), the supply source for which is grounded and the collector connected to the lead 18, the effect of this is to provide a zero signal at terminal 9 during the period of interconnection except during the synchronization period, the gate being made inactive by the signal Q of the bistable circuit 26 arriving at its second output.

What is claimed is:

1. A sampler comprising:

a. a plurality of inputs each of which is adapted to receive one of a plurality of electrical input signals,

b. a single output at which samples of the input signals appear in a predetermined order,

c. a priming gate between each input and said output for controlling the connection of its respective input to said output, and

d. a ring counter having a plurality of stages serially connected in an endless chain, the output of the last stage being connected to the input of the first stage, said stage being equal in number to the number of said inputs, each stage applying control signals to a different one of said priming gates to cause that gate to connect its respective input to said output for a predetermined duration, said stages operating in a predetermined order to apply their control signals and only one of said priming gates receiving a control signal at any one time, whereby samples of the electrical input signals appear one at a time at said output.

2. A sampler according to claim 1 wherein said priming gates are field effect transistors each having a collector electrode, and including a positive D.C. source for said transistors and a diode connected between said collector electrodes and said source, thereby preventing the taking of samples in the absence ofa supply voltage.

3. A sampler according to claim 1 including means for providing first and second identical clock signals, and a logic gate between each ring counter stage and its respective priming gate, and wherein each stage of said ring counter includes a trigger circuit responsive to each of said first clock signals for supplying a gate pulse, said gate pulses and said second clock signals being applied to the logic gate associated with that stage for opening its respective priming gate for a duration shorter than the duration of said gate pulse, whereby samples appear at said output at spaced apart intervals.

4. A sampler according to claim 3 wherein each of said priming gates includes a control electrode, and including a removable connection between the control electrodes of two adjacent priming gates, the logic gate associated with one of said adjacent priming gates being unconnected to said means providing second clock signals, whereby said two adjacent priming gates deliver a synchronization pulse.

5. A sampler according to claim 4 including means for deriving from the gate pulse of the last stage of said ring counter a signal for resetting the other stages to zero.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2662175 *Feb 18, 1948Dec 8, 1953Hartford Nat Bank & Trust CoMultiplex transmission device
US3015806 *Mar 12, 1958Jan 2, 1962Wang LaboratoriesMachine tool control system
US3184663 *Jul 25, 1960May 18, 1965Warner Swasey CoPlural pulse responsive motor synchronizing control system with uniform pulse spacing
US3229115 *Feb 21, 1962Jan 11, 1966Rca CorpNetworks of logic elements for realizing symmetric switching functions
US3280309 *Jun 28, 1963Oct 18, 1966Electro Optical Systems IncLogarithmic pulse counter
US3461313 *Dec 9, 1965Aug 12, 1969Teletype CorpCircuit for maintaining selected circuits operated
US3517175 *Aug 15, 1967Jun 23, 1970Plessey Co LtdDigital signal comparators
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4903242 *May 6, 1988Feb 20, 1990Nec CorporationSerial access memory circuit with improved serial addressing circuit composed of a shift register
US5016263 *Jul 6, 1989May 14, 1991Kabushiki Kaisha ToshibaSample-hold circuit with outputs taken between gates of dynamic shift register to avoid skew from unequal interstage connection lengths
US5371525 *Nov 25, 1991Dec 6, 1994Kyocera CorporationImage head
U.S. Classification327/91, 327/231, 377/76
International ClassificationH03K17/693, H04J3/04
Cooperative ClassificationH04J3/047, H03K17/693
European ClassificationH04J3/04D, H03K17/693