|Publication number||US3668430 A|
|Publication date||Jun 6, 1972|
|Filing date||Jul 12, 1971|
|Priority date||Jul 12, 1971|
|Publication number||US 3668430 A, US 3668430A, US-A-3668430, US3668430 A, US3668430A|
|Inventors||Kan David T|
|Original Assignee||Signetics Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (9), Classifications (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Kan June 6, 1972  HIGH SPEED LOGIC CIRCUIT WITH  References Cited LOW EFFECTIVE MILLER UNITED STATES PATENTS CAPACITANCE 3,364,434 1/1968 Widlar ..330/30 D [721 111mm" David Santa Clara cahf' 3,573,489 4/1971 Sramek ..307/215 73 Assi nee: Si etics Co ration Sunn vale, Cai'f. I 1 g gn rpo y 1 Primary Examiner-Stanley D. Miller, Jr.  Filed: July 12, 1971 Assistant Examiner-L. N. Anagnos I pp No': 161,476 Attorney-Flehr, Hohbach, Test, Albrmon 8L Herbert  ABSTRACT  U.S.Cl ..307/235, 307/215, 307/218, A high speed logic circuit includes a differential amplifier 328/ 330/30) driving a shunt feedback output amplifier having an input  Int. Cl ..H03k 19/30, H03k 19/34 which acts as an ac ground The effective Miner capacitance  FieldofSem-ch 307/213,214,215,218,235,
of the differential amplifier is therefore minimized.
3 Claims, 3 Drawing figures I-HGH SPEED LOGIC CIRCUIT WITH LOW EFFECTIVE MILLER CAPACITANCE BACKGROUND OF THE INVENTION The present invention is directed to a high speed logic circuit with low effective Miller capacitance.
Prior logic circuits have had excessive propagation delays. A partial cause of such delays was the effect of the Miller capacitance of the active components; in other words, a change from one state to another of the logic circuit necessitated a charging of these capacitances.
OBJECT AND SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a high speed logic circuit with low effective Miller capacitance.
In accordance with the above object there is provided a logic circuit having an output terminal switchable between two levels in response to a bi-level input signal on an input terminal. A differential amplifier is switchable between two states having a reference voltage input and also being coupled to the input terminal of the logic circuit. The amplifier is responsive to a level change in the input signal for switching from one state to another on at least one input terminal. A shunt feedback output amplifier includes shunt feedback means for maintaining an active element of the amplifier continuously on the input terminal of the active element being coupled to the output terminal of the difierential amplifier and forming a virtual ac ground. The shunt feedback means is also coupled to the output terminal of the differential amplifier. A change of state of the terminal causes a change of current through the feedback means for providing the two levels of the logic circuit output terminal.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram embodying the present invention; FIG. 2 is a detailed circuit schematic of FIG. I; and FIG. 3 is an alternate embodiment of FIG. 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic circuit of the present invention as illustrated in FIG. 1 includes a differential amplifier or current switch 10 having an input terminal 11 responsive to a bi-level input signal to switch the output terminal designated V between two logic levels. Amplifier 10 also includes a V input on line 12 to provide the differential amplifying action. A bias network 13 is coupled to amplifier 10.'A shunt feedback output amplifier 16 includes an amplifying unit 17 with a shunt feedback resistor 18 coupled between the output temiinal which is V, and its input on line 19. Because of the shunt feedback action of resistor 18 which always maintains amplifier 17 in an on or active condition, line 19 is a virtual ac ground. Thus, as will be described below a switching action of differential amplifier 10 does not affect the voltage potential of line 19 and any associated Miller capacitances with the differential amplifier 10 are, therefore, not charged or discharged to cause delay.
The detailed circuit schematic of FIG. 1 is shown in FIG. 2 where differential amplifier 10 includes transistors 01 and Q2 which have their emitters coupled together and to a bias current source Q4. The base input of O1 is the voltage input terminal 11 and the base input of O2 is the reference line 12. Line 12 is coupled to a diode connected transistor Q through series connected resistor R1. The collector of Q5 is also the base input of biasing transistor Q4. This input is always at the V level because of the diode connection of transistor Q5.
Thus, transistors Q4 and Q5 constitute a diode biased current source for biasing differential amplifier 10. In practice, the entire circuit would be produced in integrated format with transistors Q4 and Q5 being constructed with similar geometry. Since they have the same base to emitter voltage across them the collector current of 04 will follow the collector current of Q5. Similarly, since the emitter of transistor 04 is the only path to ground for the differential amplifier transistors Q1 and 02, any current flow through transistor Q1 or Q2 will be equal to that through transistor Q4.
The base of O2 is held at the reference voltage V which is chosen to be approximately 0.3 volts above V,,, which is the zero output level at the output terminal V,,. The 0.3 volts is provided by the constant current flow through the resistor R1 due to V Feedback output amplifier 16 includes a transistor Q3 and the feedback resistor 18 (also designated R coupled between the collector and base terminals. This resistor is chosen so as to always maintain. O3 in an on or conductive condition. The collector of O3 is also coupled to V through resistor R].
In operation, depending on the bi-level input signal at input terminal 1 1, either transistor Q1 or O2 is in a conductive condition. For example, if the input is high, meaning that the base voltage of O1 is greater than the base voltage to Q1 by substantially 200 mV or V ()1 is on and O2 is off. With Q2 off the output voltage is low because of the inverter action of the logic circuit of the present invention and it is substantially at the level of the base to emitter voltage drop, V of transistor Q3. The slight base current through R can beneglected.
When the input goes low, the differential amplifier switches and O2 is now on. This causes the collector current of O2 to flow to ground through Q4 and also through the feedback resistor R The collector current I of 02 which is also the current through R, is as discussed above equal to I the collector current of 04, which in turn because of the diode biased current source configuration equal to the current through Q5 which is L,,. In other words, I detennines the current to Q2. The current through O5 is merely simply determined by the ratio of V V /Rl R2.
The output voltage V is now determined, with O2 in its on condition, by the V of Q3 and the voltage drop across R, which is I R, Thus, the change of current through R, provides a two level output at vV between V,,, and V I R However, in accordance with the invention this change of output level does not afl'ect the base input line 19 to Q3 since because of the continuous on condition of Q3 the input is always maintained at V The switching action of the differential amplifier does not change the voltage level at the collector of Q2 and thus no Miller capacitance associated therewith need be charged or discharged. The same is clearly true at the collector of 01 which is tied directly to V Thus, line 19 forms a virtual acground since it is at a constant voltage, V above ground to provide for an effective low Miller capacitance and therefore high switching speeds.
The circuit of FIG. 2 can be modified to provide a complementary output V by adding in the collector circuit of Q1 a similar shunt feedback amplifier 16. In addition, if it is desired to drive the logic circuit of the present invention with a similar type logic circuit a modification can be made to prevent saturation of Q1. Two additional diodes are added, for example of the Schottky barrier type, in the emitter and collector circuits of the shunt feedback transistor Q3. This then prevents saturation of Q1 and the shunt feedback transistor Q3. This is normally accomplished with the alternate complementary configuration.
The circuit of FIG. 2 is also ideally suited, as illustrated in FIG. 3, for use where a transmission line, designated 2 is necessary between a driving circuit and a driver circuit. A single terminating resistor R is connected at the base input to Q3. It is assumed that resistor R, in conjunction with the input impedance of transistor Q3 is equal to the characteristic impedance of the transmission line. This mode of driving the transmission line may be termed a terminated series mode." The collector of O2 is used as a driver for the transmission line. With the present configuration, the transmission line is reasonably terminated at its far end or at the Q3 end and there is therefore no power loss.
Thus, the present invention has provided an improved high speed logic circuit which minimizes the effect of Miller capacitance.
1. A logic circuit having an output terminal switchable between two levels in response to a bi-level input signal on an input terminal comprising: a differential amplifier switchable between two states having a reference voltage input and also being coupled to said input temiinal of said logic circuit said amplifier being responsive to a level change in said input signal for switching from one state to another on at least one output terminal; a shunt feedback output amplifier including shunt feedback means for maintaining an active element of said amplifier continuously on an input terminal of said active element being coupled to said output terminal of said differential amplifier and forming a virtual ac ground, said shunt feedback means also being coupled to said output terminal of said differential amplifier, a change of state of such terminal causing a change of current through said feedback means for providing said two levels on said logic circuit output terminal.
2. A circuit as in claim 1 where said differential amplifier includes two emitter coupled transistors the collector of one being said differential amplifier output terminal said feedback output amplifier including a transistor and a feedback resistor coupled between its collector and base said base being coupled to said collector of said differential amplifier transistor, conduction of such transistor causing an increase of current through such resistor to switch said output level, said resistor maintaining said transistor of said amplifier continuously conductive whereby the voltage level of the base input of such transistor is maintained constant to form said virtual ac ground.
3. A circuit as in claim 1 together with diode biased current source means for biasing said differential amplifier.
t i l
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3364434 *||Apr 19, 1965||Jan 16, 1968||Fairchild Camera Instr Co||Biasing scheme especially suited for integrated circuits|
|US3573489 *||May 29, 1969||Apr 6, 1971||Gen Electric||High speed current-mode logic gate|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US4145621 *||Jan 19, 1976||Mar 20, 1979||Ferranti Limited||Transistor logic circuits|
|US4962341 *||Feb 2, 1988||Oct 9, 1990||Schoeff John A||Low voltage non-saturating logic circuit technology|
|US5150073 *||Dec 17, 1990||Sep 22, 1992||St Microelectronics Srl||Low-noise preamplifier stage, in particular for magnetic heads|
|US5925914 *||Oct 6, 1997||Jul 20, 1999||Advanced Micro Devices||Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance|
|EP0018172A2 *||Apr 10, 1980||Oct 29, 1980||Fujitsu Limited||High speed electronic switching circuit|
|EP0018172A3 *||Apr 10, 1980||Nov 12, 1980||Fujitsu Limited||High speed electronic switching circuit|
|EP0089091A2 *||Mar 14, 1983||Sep 21, 1983||Philips Electronics N.V.||Voltage translator|
|EP0089091A3 *||Mar 14, 1983||Jan 16, 1985||N.V. Philips' Gloeilampenfabrieken||Voltage translator|
|WO1992006537A1 *||Oct 2, 1990||Apr 16, 1992||Schoeff John A||Low voltage non-saturating logic circuit technology|
|U.S. Classification||327/87, 326/136, 330/260, 327/50, 330/286|
|International Classification||H03K19/013, H03K19/01, H03K19/018|
|Cooperative Classification||H03K19/013, H03K19/01812|
|European Classification||H03K19/018B2, H03K19/013|