|Publication number||US3668687 A|
|Publication date||Jun 6, 1972|
|Filing date||Nov 17, 1969|
|Priority date||Nov 17, 1969|
|Publication number||US 3668687 A, US 3668687A, US-A-3668687, US3668687 A, US3668687A|
|Inventors||Hale David B|
|Original Assignee||Sanders Associates Inc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (11), Classifications (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Hale June 6, 1972 RASTER SCAN SYIVBOL GENERATOR Primary Caldwell 6 Assistant Examiner-Michael Slobasky  Inventor. David B. Hale, Claremont, NH. Atmmey Louis Eflinger  Assignee: Sanders Associates, Inc., Nashua, N.H.
57 ABSTRACT  Filed: Nov. 17, 1969 1 A raster scan character generator which forms different sized  Appl' 877323 characters with dot pattern forming nets which are shared by characters employing common dot patterns. The generator in-  US. Cl. ..340/324 A, 315/18 cludes a timing control which responds to a size code to selec-  tively change the dot signal frequency as well as to perform a  Field of Search ..340/3 24. l; 315/ 8.5, 18 size conversion operation on the odd and even scan line signals. A character stroke or dot pattern encoder responds to Reference-5 Cited a selected character to provide dot pattern or stroke identifier signals to a stroke/dot pattern generator. The dot pattern UNITED STATES PATENTS generator includes vertical, horizontal and slant dot pattern 3,533,096 /1970 Bouchard ..340/324 A forming networks which respond to the dot pattern identifier 3,426,344 2/ 1969 Clark ..340/324.1 stroke signals as well as to the scan line and dot signals to pro- 3,428,85l 2/1969 Greenblum ..340/324.l vide a signal pattern indicative of a selected character of a selected size.
.599%? 7 7. D awinsli sy s SIGNAL SOURCE 32 CHR. CODE CHARACTER REGISTER F STROKE DOT PATTERN GENERATOR I CHARACTER p vERT. STROKES DECODER RNHVERT STROKES VERTICAL 70 H 2 CHARACTER SET HOR. STROKES STROKE RESET HOR STRO HOR'ZONTAL gggg E i kg ENCODER SIZE CODE SLANT STROKES SLANT SPECIAL DOT GROUPS SPECIAL 40 l SCAN LINES TIMING CONTROL DOTS PATENIEIIJIJH 6 I972 SHEET 5 OF 9 TO STROKE DOT f'GENERATOR IVI5 LI6-I9 CAI SH5S4 SH I954 CVI5 IV l5 Ll6-I9 IV|5 L5-8 REMAINING STROKE CONTROL LINES lNVENTOf? DAVID B. HALE .4 T TORNE Y PMENTEUJUH 61912 5 7 SHEET 6 OF 9 89B\ OCDAD 1.0 s N CONTROL Lw 89A4\ 89A v SYNC. SYNC CONTROL 89A2 31 12 8 8 H SYNC. Q 1.1NE
COUNTER 1'" R BLANK 89A- J c K 89A3 I ODD SCAN LA,LC,-LW I i EVEN SCAN LB,LD,--LX NOR s20 81 7 WE CON 2 l CODE S E CON 1 NOR 1 1 l i l i c1 oc1 1 I i m SOURCE i j a L 1 1145 f 1 I 1 1.7 Ls- 1 5 l j 1 83 I I 1- l l l 11 1 85-8 1 1 NAND 1 1 I I 1 L 1 1 s7 1 1.9-1.23 1 DOT 84 I I COUNTER i i L24 I l 1 J J I v s1- $24 1 a SCAN LINE SIGNALS TO STROKE/ DOT SIGNALS DOT GEN. TO STROKE (FIG.3) 001' GEN. (FIG. 3)
5 lNl/ENTOR DAVID B. HALE ATTORNEY PATENTEDJUH 6 I972 3, 668.667 SHEET 70F 9 I F1 I i l I I I 52 53 r NET I I I A3 1 1 I K5 I 'A 6 I w A Q A' I A I -Tl' I KTE I W ITO. OR NET 70 A I5 AI4 I FIG. 3 I NET BI NET m B2 NET B3 NET g3 "IVE/V701? B4 NET B 4 J DAVID B. HALE FIG. 6A
ATTORNEY PATENTEDJUH 6 I97? 3. 668,687
sum 8 OF 9 CVl SI VI v| INH VI NET LINE GROUP TO OTHER VERTICAL STROKE NETS CV4 v4 v4 L533! NET L5-I9 56 54 CV8 L. I 1
S8 V8 W INH V8 NET NAND NAND LINE GROUP TO OR ,NET 70 CVH VII W su NET l 57 55 NAND NAND CV5 J v5 V3 55 NET INVENTO/i v DAVlD B. HALE PMKMM ATTORNEY PATENTEDJUH 6:972 3,668,687
SHEET 9 OF 9 TO OR NET 70 lNVE/VTOR DAVID B. HALE FMKW ATTORNEY RASTER SCAN SYMBOL GENERATOR BACKGROUND OF THE INVENTION This invention relates to new and improved display systems which convert digital signals (e. g. binary) corresponding to informational data into video signals for displaying such data as symbols on conventional television picture tubes. Display systems of this type are useful since one video signal source can provide informational data to many standard television receivers or monitors via conventional transmission media, such as closed circuit transmission lines, microwave links, radio links and the like. Because the data can be displayed on standard television monitors, the display system is less costly than other display systems which display informational data (e. g. alphanumerics, vectors, curves and other symbols).
In general, the standard scanning raster of the television picture tube is utilized in such systems to produce the displayed symbols. For example, the active viewing area of a 525 line television raster consists of 483 horizontal scan lines, equally spaced in a vertical direction to display a two dimension picture. This two-dimensional picture is generally divided into equal symbol spaces arranged in rows and columns. In the exemplary system described hereinafter embodying the improvements of the present invention, the television raster is capable of generating up to 27 rows of 56 symbols. Each row and, hence, each symbol space consists of a group of television scan lines. Each column and, hence, each symbol space consists of successive time segments (along the horizontal dimension) during which the scanning beam may be unblanked.
Since the television scanning beam moves horizontally by line and progresses vertically downwardly, the symbols are written on a line by line basis, row by row. Portions of each scan line associated with a symbol row are selectively blanked and unblanked in accordance with selected symbols so as to produce a slice of each symbol in a row for each scan line. The symbol slices in successive scan lines then integrally form the selected symbols.
Each symbol is represented by coded binary signals. To generate the correct video signals, selected ones of the binary input signals are shifted in sequence to a prescribed position during each scan line. In the prescribed position, each selected binary input signal is decoded to provide a symbol identifier signal. Each symbol identifier signal is coupled to partially enable unique combinations of logic gates. The partially enabled logic gates are further enabled by TV scan line signals so as to pass selected vertical time segment or dot signals thereby producing unblank signals at the proper times to provide slices of the corresponding symbol. The sequencing of the coded binary input signals causes the correct video signal to be applied to the display device at the proper times in the scan lines.
In some known raster scan type display systems, separate gating chains are required for each character in the set. In others, an attempt has been made to share logical gating nets among those characters having common characteristics. For example, in one of the latter systems alphanumeric characters having common vertical dot patterns share common logic nets to generate the video unblank signals for such common dots. Although, the latter system does gain a reduction in logic gating nets and a uniform type of logical net, it does not provide an efficient logical net reduction, especially for higher resolution displays. In addition, it is believed that such systems are incapable of displaying more than one character size without adding additional gating chains for each additional size.
BRIEF SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel and improved display system.
Another object is to provide novel and improved raster scan symbol generating apparatus.
Still another object is to provide novel and improved raster scan symbol generating apparatus capable of generating different sized characters.
In brief, the invention is embodied in display apparatus for generating patterns for display on a display device which exhibits a television raster scan line pattern wherein rows and columns of symbol spacers are defined by sequences of scan line signals and sequences of dot signals, respectively. The apparatus includes first means for providing symbol codes representative of a symbol set, the symbols of which are formed from a common set of dot patterns including horizontal, vertical and slant lines, the horizontal and vertical directions corresponding to the row and column directions, respectively. Second means is responsive to the symbol codes to provide horizontal, vertical and slant line identifier signals. Third means including horizontal, vertical and slant line forming circuits responds to corresponding line identifier signals and to the scan line and dot signals to provide horizontal, vertical and slant dot pattern signals in accordance with coded combinations of the symbol identifier signals. The horizontal, vertical and slant dot pattern signals are then combined into a single dot pattern signal representative of the symbol codes.
According to one feature of the invention means is provided to change the size of the symbol spaces. This means includes means responsive to symbol size control signals to 1) change the frequency of the dot signals and to (2) change the count sequence of the scan line signals.
BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings like reference characters denote like structural elements; and
FIGS. 1A and 1B illustrate the resolution, character spacing and typical characters of different sizes for one exemplary embodiment of the invention;
FIGS. 2A-2F illustrate typical vertical, horizontal and slant dot patterns which can be shared by a number of characters in a particular character font;
FIG. 3 is a block diagram of a raster scan generator embodying the present invention;
FIG. 4 is a block diagram in part and a logic diagram in part of the character stroke encoder shown in the FIG. 3 diagram;
FIG. 5 is a block diagram in part and logic diagram in part of the timing control portion of the raster scan generator shown in FIG. 3; and
FIGS. 6A, 6B and 6C are block diagrams in part and logic diagrams in part of the slant, vertical and horizontal stroke forming networks, respectively, of the stroke/dot pattern generator of the raster scan character of FIG. 3.
DESCRIPTION OF THE PREFERRED EMBODIMENT It is within the contemplation of the present invention that symbols of any desired shape such as alphanumeric characters, graphical type symbols, and others can be formed from a common set of dot patterns including horizontal, vertical and slant line patterns. However, by way of example and completeness of description, the invention is herein illustrated for an alphanumeric character generator embodiment.
The manner in which character patterns are formed on a display device having a television raster scan is illustrated in FIGS. 1A and 1B and FIGS. 2A, 2B, 2C and 2D. As shown in part in FIG. 1A, the display surface is apportioned into a row and column grid of character spaces with a row margin between adjacent rows and a character or column margin between adjacent character columns (characters .in a row). For the illustrated high resolution embodiment, each character space is shown to comprise a sub grid of 24 scan lines, L1, L2 L24, by 24 time segment spaces, S1, S2 S24. The row and column margins, thus, consist of six scan lines (L22-L24 and L1-3) and of seven time segment spaces ($17-$24), respectively. The maximum active character area then is a grid of 21 scan lines (Ll-L21) by 16 time segment spaces (51- $16). It is understood, of course, that the illustrated 24 by 24 grid is merely indicative of the resolution obtainable with embodiments of the present invention and other grids of different resolutions may be employed.
In a standard television raster, the scan lines Ll-L24 are interlaced; i.e., the scanning beam first scans the odd lines L1, L3 L23 of each character row and then scans the even linesL2, L4 L24 of each row to form the complete raster.
Scan line signals which correspond ,in time to the duration of 5 the active trace scan ofa scan line are also referred to as L1-L24 throughout the description for convenience. Also, throughout the description, the time segment sequence S1- S24 designates time segment'signals which occur in sequence for each characterspace (including the column margin) along each character row. Thus, in each scan line, the time segment signals occur in repetitive sequences. Throughout the description, these .time segment signals will be referred to as dot signals. In order to provide bridging between the dot spaces and to provide uniform horizontal, slant and vertical line widths, each dot signal is two time segments in time duration so as to eliminate voids in character patterns caused by failure of the dots to overlap. For example, the S3 dot signal begins on S3 time and ends on S4 time (scan line L6 of FIG. 1A).
As shown in FIG. 1A, each character is composed of unique combinations of dot patterns, some of which patterns are common to several characters of symbols in a particular font of characters comprising the character set or library. As described later in detail, all characters which use a common dot pattern share a single logical gating net which produces a dot pattern signal, for selectively unblanking the scanning beam in the display device. In such a device, the dots are, of course, a solid color on a contrasting color background, whereas the dots are shown in outline form in FIG. 1A to illustrate the formation of characters with common dot patterns.
Although different character fonts may require different dot patterns, FIGS. 2A, 2B, 2C, 2D, 2E and 2F illustrate typical vertical, horizontal and slant patterns which are formed of adjacent dots so as to give a stroke or vector appearance. For clarity and convenience the strokes are illustrated in FIGS. 2A, 2B, 2C and 2D by small circles in the dot spaces, which correspond to stroke end points and lines extending between the end point circles and through adjacent dot spaces therebetween which are utilized to form the strokes. For example in FIG. 2A, vertical stroke V1 includes the adjacent S1 dot spaces from scan line L5 through L19. In FIG. 2B, horizontal stroke H5 includes the dot spaces Sl through 515 along scan line LS..In FIG. 2C, slant stroke A8 includes the dot spaces S13, S14 and S15 on scan lines L18, L17, and L16, respectively. Since each of the dot signals is two dot spaces in time duration, each of the slant and vertical strokes are essentially two dot spaces wide. Thus, as shown in FIG. 1A the slant stroke A8 actually occupies dots S15 and S16 on scan line L16, dots S14 and $15 on L17 and dots S13 and S14 on L18. For convenience, only the left hand one of such dots will be referred to throughout the description.
While FIGS. 2C and 2D are illustrative of slant strokes, the slopes of which increase or decrease one scan line at a time in stair-step fashion; other slopes are obtainable. For example, FIGS. 2E and 2F show slant strokes having slopes which are determined by two scan line steps. The B1 stroke in FIG. 2E and the B4 stroke in FIG. 2F can be employed, for example, in the formation of the alphabetic character A." On the other hand, the B3 slant stroke in FIG. 2F and the B2 slant stroke in FIG. 2E can be employed in the formation of the alphabetic character V."
Before describing the formation of characters with the strokes (or dot patterns), it is well to point out the symbolic language used herein to describe each stroke. The symbolic language essentially specifies a stroke or portion thereof in terms of control signals which are applied to a logic net which produces the stroke. For the case of slant and vertical strokes the control signals are designated by the letter "C" followed by the stroke name, for example CA8, CB1, CV15. For the slant strokes no further control identifier signals are necessary.
However, for vertical strokes, different characters may require different lengths of the same stroke. Thus, inhibit signals are also required to describe the vertical stroke length when less than the total length is employed. These inhibit signals are designated by the letter I (inhibit) followed by the stroke name which in turn is followed by the scan lines to be inhibited. For example, CV15 and IVI5L16-l9 describe a V15 stroke which extends from L5 to L15 at S15 time. Similarly, for the case of horizontalv strokes, two control identifier signals are required to designate stroke length. The first of these signals identifies the start of the horizontal stroke and is designated by the letter "S" (set) followed by the stroke name which in turn is followed by the dot time at which the stroke starts. Similarly, the end point of a horizontal stroke is designated by the letter R" (reset) followed by the stroke name and dot time at which the stroke ends. For example, SH19S4 and RH19S14 indicates a horizontal stroke on scan line 19 which begins at S4 time and ends at S14 time.
It will be appreciated that though the vertical, horizontal and slant strokes illustrated in FIGS. 2A-2F can be employed to form all of the usual alphanumeric characters, other special dot patterns may be included so as to form such special symbols as and the like. Since such special dot patterns may be generated bymeans of appropriate identifier signals and logical gating similar to those described hereinafter and since such special dot patterns are not germane to an understanding of the present invention, no further description thereofis necessary.
Returning again to FIG. 1A the numeric character 9" and the alphabetic character .U" are shown as illustrative of the formation of characters with the horizontal, vertical, and slant dot patterns. In particular, it will be noted that both the 9" and the U" characters employ the CA1 and CA8 control identifier signals and thus share the same logical nets. The 9 and U characters also share the logical net which produces the H19 horizontal stroke from S4 to S14 time. The 9 and U characters further share another logical gating net which produces the V15 vertical stroke. For both characters the V15 logical gating net is inhibited on scan lines L16-Ll9 by the inhibit signal IV15L16-19. For the case of the 9 character the V15 gating network will be further inhibited on scan lines L5-L8 by an inhibit signal IVl5L5-8 (not shown in FIG. 1A). The formation of the U character is completed by a portion of the V1 stroke. The formation of the 9 character is completed by the CA3, CA4, CA5 and CA6 slant strokes and portions of the H5 and H12 horizontal strokes.
The characters 9 and U" are normal sized characters. According to one feature of the invention the same stroke gating chains which produce normal sized characters can be employed to produce smaller sized characters. FIG. 1B illustrates the smaller size for the character U." The technique employed is to shrink the horizontal dimension of the dot size, to eliminate certain scan lines from the normal sized character and to shift the remaining scan lines to fill up the voids created by the eliminated scan lines. The shifting may be either up or down in the character space, the down shift being shown in FIG. 1B.
Referring now to FIG. 3, display apparatus embodying the invention displays character patterns on a display device 72 which may, for example, comprise a standard television'monitor having a conventional picture tube. Information to be displayed on the display device 72 is provided to a character register 30 by signal source 32 in binary form. The signal source 32 includes a suitable storage means for storing the binary input data and suitable control circuits which are synchronized with the scanning raster of the display device 72 so as to provide binary input characters to the character register 30 at the proper times. For example, the signal source 32 may update the character code contained in character register 30 during the character or column margins (dot times $17-$24, FIG. 1A) which follow each scan of the active character scan area in each character space. It is also understood that the binary input characters could be provided to the character register 30 in other ways. For example, the character register 30 could comprise enough stages to hold an entire row of characters in which case signal source 32 would update character register 30 when the scanning beam has completed the scan of an entire row (during the row margin, FIG. 1A). Also in such case, the character codes in the character register 30 would be sequentially shifted during each of the character or column margins so as to provide at the proper time the proper character to a character decoder 31.
The character decoder 31 decodes the input character code to provide a character identifier signal on one of a plurality of character identifier lines to a character stroke encoder 40. The input data format for each character to be displayed may, for example, comprise a 6 bit binary code. Such a code is sufficient to display all the alphanumeric symbols as well as punctuation and other marks. There is one character identifier line for each character or symbol in the set. For example, a 64 character or symbol set requires 64 character identifier lines.
The character stroke encoder 40 responds to a selected character identifier signal to produce the aforementioned stroke identifier signals on a plurality of stroke identifier lines. In FIG. 3, the stroke identifier lines are illustrated in groupings which correspond to the previously described stroke or dot patterns. Thus, the stroke identifier lines includes a vertical stroke group, an inhibit vertical stroke group, a set horizontal stroke group, a reset horizontal stroke group, a slant stroke group and a special dot group.
A stroke and/or dot pattern generator 50 responds to the stroke identifier signals to produce a different pattern of digital unblank signals for each vertical, horizontal, slant or special dot pattern required by the selected character. To this end the stroke and/or dot pattern generator 50 includes vertical, horizontal, slant and special logical gating nets; each of which receives scan line information and dot information from a timing control 80.
The vertical, horizontal, slant, and special dot unblank signal patterns are ORed together in an OR NET 70 to produce a single digital unblank signal pattern. A video processor 71 amplifies and processes the digital unblank signal pattern for intensity modulation of the convention picture tube (not shown) on the display device 72.
Referring now to FIG. 4 the character stroke encoder 40 will now be described in more detail. In this description of the stroke encoder a number of logical networks will be referred to and illustrated as NAND gates which are operated as an OR function. For example, when all inputs to a NAND gate are high the output is low. When anyone of the inputs to the NAND gate goes low, its output goes high thereby providing an OR function on its inputs.
The character stroke encoder 40 essentially performs logical OR functions on those groups of character identifier signals which require common strokes or dot patterns. To this end, the stroke encoder 40 includes a logical OR NET for each stroke identifier signal. Each such logical OR NET has inputs from those character identifier lines which require the associated stroke identifier signal. Thus, the logical OR NET 41 which produces the CA1 stroke identifier si nal has inputs from the following character identifier lines: .l, and U, (the encircled letter designates a character group identifier line which identifies selection of any one of a number of characters including 9"). The logical OR NET 41 is one ofa group of similar logical OR NETS, collectively designated as 42. A portion of the stroke identifier lines and signals which are employed to form the 9 and U characters is shown in FIG. 4 to be derived from the logical OR NETS 42. The remainder of the stroke identifier lines and signals; namely, those for producing the V vertical stroke and for inhibiting portions thereof, is shown to be derived from a logical OR NET 43.
The logical OR NET 43 will produce a high signal on a stroke identifier line CV15 when any one of its input character identifier lines or W oes low. Thus,
5, or lines goes low,
a a when any one o the f W, 6, u, a NAND gate 46 responds thereto to provi e a high going CV15 signal. When either the G, U@ 9, orcharacter identifier lines goes low, another NAND gate 5 responds thereto to provide a high going IVl5L16-l9 signal (inhibit vertical 15 on scan line 16-19). The high going IV15L16-19 signal is inverted by an inverter 47 to cause NAND gate 46 to prod ce a hi h going CV15 signal. Finally, when any one of the oharacter identifier lines goes low, an AND gate 44A and an inverter 44B respond thereto to provide a high going IV15L58 signal (inhibit vertical 15 on scan lines 5-8). The NAND gate 45 also responds to the low signal condition of the output of AND gate 44A to further provide the IV15L16-19 signal which in turn is responded to by inverter 47 and NAND gate 46 to provide a high going CV15 signal. It is to be noted that the AND gate 44A and the inverter 44B are, of course, the logical equivalent of a NAND gate.
The stroke/dot pattern generator 50 (FIG. 3) receives not only the stroke identifier signals from the character stroke encoder but also receives scan line and dot information from the timing control 80. Before describing the vertical, horizontal and slant logic nets contained in the generator 50, it is best to describe the nature of the scan line and dot signals provided by the timing control 80. The scan line and dot signals produced by timing control also include character size information. That is, the scan line and dot signals have one set of characteristics for normal sized characters such as those shown in FIG. 1A and another set of characteristics for smaller sized characters such as the one shown in FIG. 1B. To this end, the signal source 32 (FIG. 3) also provides a size code to the timing control 80.
The timing control 80 is shown in FIG. 5 to include a size decoder 81 which responds to the size code to produce three control signals; namely, a normal signal NOR indicative of a normal sized character, a conversion one signal CONl indicative of a smaller sized character having the vertical character space position illustrated in FIG. 1B, and another conversion signal CON2 also indicative of a smaller sized character which has a higher vertical position than that shown in FIG. 1B. A
size conversion network 85 responds to the NOR, CON1 and CON2 control signals to relate its scan line output leads L1 through L24 to selected ones of odd scan signals LA, LC, LW and of even scan signals LB, LD, LX. For the illustrated embodiment there are 12 odd scan signals and l2 even scan signals which are produced by a sync control and line counter 86 in accordance with the standard vertical and horizontal and synchronizing signals Vsync and Hsync, respectively, which are associated with conventional television picture tubes. The odd and even scan signals may be produced on an interlaced basis as is well known in the art.
The size conversion network 85 includes a number of gating nets 85-1, 85-2 85-24 associated with the output scan line leads L1 through L24, respectively. The odd and even scan signals are wired in various combinations to inputs of the gating nets 85-1 through 85-34. The NOR, CON1 and CON2 signals are wired to others of the inputs of the gating nets 85-1 through 85-24 so as to select certain ones of the odd and even scan signal for coupling to the scan line leads L1 through L24.
A typical wiring program for the scan, NOR, CON! and CON2 signals is shown in TABLE I.
L L13 L F L16 L15 L21 0 L17 L16 L23 R L18 L17 L24 S L19 L19 T L20 L20 U L21 L21 V L22 L23 W L23 L24 As can be seen in TABLE I, for a normal sized character the conversion network 85 responds to the NOR signal to couple the scan signals LA through LX to the scan line leads LI through L24, respectively. To convert the normal sized character to a smaller sized character certain ones of the scan line leads Ll through L24 are inhibited or made inactive by the network 85. For the illustrated embodiment six such leads are inhibited; namely, L2, L6, L10, L14, L18 and L22. The wiring program is selected so that network 85 couples the remaining scan line lead to a group of 18 consecutive scan signals. For the CONl case the uninhibited scan line leads are coupled to the scan signals LF through LW. The CONI case is illustrated in FIG. 1B for the small sized character U" having the relatively low character space position. For the CON2 case, network 85 connects the uninhibited scan line leads to the 18 consecutive scan signals LA through LR. The CON2 case essentially produces a small sized character having a relatively higher character space position than the one illustrated in FIG. 1B).
By way of example, the specific wiring and gating is shown for the gating nets 85-2 and 858. The gating net 85-2 responds to the NOR control signal to connect the LB scan signal to its associated scan line lead L2 for the normal size character condition. For all the smaller sized character conditions the NOR control signal inhibits the coupling of the L2 scan line lead .to any of the scan signals. Thus, the gating net 852 may suitably comprise an AND gate as illustrated.
According to TABLE I the gating net 858 must connect its output lead L8 to the scan signals LH, LK and LF for the NOR, CONI and CON2 conditions, respectively. Thus, the gating net 858 consists of a first level of AND gates, one for each of the LH, LK and LF signals, having their outputs ORED together in a second level OR gate, the output of which is the L8 lead. As illustrated, the NOR, CON 1 and CON2 control signals are applied to the same AND gate as the LH, LK
and LF signals, respectively.
The scan line output leads LI through L24 of size conversion network 85 are connected to apply scan line signals to the stroke/dot generator of FIG. 3 and are further connected to a scan line grouping network 87. The scan line grouping 87 consists of a number of OR nets which combine various ones of the scan line signals so that they appear on a single lead. Such combined scan line signals are useful in the generation of vertical strokes or dot patterns. One of the combined scan line leads L5-8 is illustrated in FIG. 5 as the output of an OR net which receives as inputs the L5, L6, L7 and L8 scan line signals. The combined or grouped scan line leads are also applied to the stroke/dot generator in FIG. 3.
In addition to the scan line conversion and grouping functions, the timing control 80 also includes means to shrink the horizontal dimension of the dots for smaller sized characters. To this end, a clock source 82 responds to the NOR control signal to produce a first clock signal CPI of relatively low frequency for normal size characters and to produce another clock signal CP2 of a relatively higher frequency for smaller sized characters. In an exemplary system the frequency of the clock signal CPI is such that 40 large sized characters comprise a character row. The frequency of the clock signal CP2 0f the same system is such that 56 of the smaller sized characters can be displayed in a single character row. For such a choice the frequency of the CP2 signal is about 3/2 the frequency of the CPI clock signal. A NAND gate 83 is enabled by the conventional television signal BLANK signal to pass the selected one of the clock signals CPI or CP2 to a dot counter 84 which provides the dot signals S1 through $24 to the stroke/dot generator in FIG. 3. The dot counter 84 may include any suitable digital counting circuits, as for example, a
The clock source 82, for example, may include a JK flipflop (not shown) which receives the NOR control signaland its complement at its J and K inputs, respectively. The clock terminal of the flip-flop may be connected then to receive a suitable one of the dot signals near the end of a character space (character column margin), for instance the dot signal $20, in order to assure that a change in character size doesnt occur in the character space portion of a scan line. The outputs of the JK flip-flop are employed to condition CPI and CP2 oscillators (not shown),
It is apparent that the shrinking of the dot size makes the character space smaller thereby permitting more characters to be displayed in a row for the case where either all small sized characters are to be displayed or where both normal and small sized characters are to be displayed. In the aforementioned exemplary system 40 normal sized characters can be displayed in a row and up to 56 normal and/or small sized characters can be displayed in a row.
For the case where any one of the character rows is to contain only small sized characters, the vertical height of the character space can be made smaller so as to permit the display of more rows of characters. According to one feature of the invention means is provided to sense the presence of a normal sized character in a character row and to provide in response thereto a scan line count or sequence of 24 and in the absence thereof to provide a scan line count or sequence of 18.
To this end, in FIG. 5 a JK flip-flop 88 is arranged to sense during each scan line the presence high) or absence (low) of the NOR signal and to store a sensed presence of the NOR signal until the end of the scan line at whichtime the reset terminal of flip-flop 88 is driven by the trailing edge of television blank signal. The flip-flop 88 is clocked by a dot signal occurring in the character space margin, such as the illustrated S20 dot signal. Thus, whenever flip-flop 88 senses a high condition of the NOR signal during a scan line, its Q output will be driven high at the S20 dot time of the associated character space. If succeeding characters in the row are small sized such that the NOR signal goes low, flip-flop 88 will not respond thereto since both its J and K inputs will be low, the K input being tied to a logical low level illustrated in FIG. 5 as circuit ground.
The Q output of flip-flop 88 and its complement O are employed to control the count sequence of the even and odd counters in the sync and scan counter control 86. For the exemplary 24 and 18 scan line system, both of the scan counters have 12 stages, all of which are employed for a 24 scan sequence when one or more normal sized characters are sensed and nine of which are employed (in each counter( when only small sized characters are to be displayed in a row. The count sequence of the scan counters is controlled by means of even and odd scan controls 89A and 89B, respectively. For the sake of simplicity the even and odd scan controls for the exemplary system are shown for displaying either character rows having one or more normal sized characters or character rows having all CON2 type small characters. The mixed mode of CONI and CON2 type small characters is not allowed in the programming of the character codes, though it could be with suitable changes in the scan controls and additional sensing means for sensing the presence of both CONI and CON2 type characters in a row.
To afiect a count sequence of 9 or 12 the even and odd scan counter controls 89A and 89B, respectively, receive the ninth and twelfth stage outputs from their associated scan counters and the Q and O outputs of flip-flop 88. Thus, according to TABLE I even scan control 89A receives the LR and LX scan outputs of the even scan counter and the odd scan control 89B receives the L0 and LW scan signals of the odd scan counter.
Each of the scan controls 89 and 89B contain substantially similar logic such that only the logic for even scan control 89A is shown. The even scan control 89A contains AND gates 89A1 and 89A2 each receiving the ninth stage of LR of the associated even scan counter. AND gate 89A2 also responds to the output of flip-flop 88 to configure the even scan counter into a 12 count sequence whenever one or more NOR type characters are sensed during a particular scan. That is, the output of AND gate 89A2 is fed to the input of the tenth stage of the even scan counter. On the other hand, AND gate 89A1 responds to the 6 output of flip-flop 88 to configure the even scan counter in a 9 count sequence when no NOR type characters are sensed during a scan. That is, the output of AND gate 89A1 is fed by way of an OR gate 89A4 to the input of the first stage of the even scan counter. A third AND gate 89A3 responds to both the Q output of flip-flop 88 and the twelfth stage output of LX of the even scan counter to complete the configuration of the even scan counter into a 12 count sequence. That is, the output of AND gate 89A3 is fed by way of OR gate 89A4 to the input of the first stage of the even scan counter.
The odd scan control 898 contains substantially similar logic to affect a similar operation of the odd scan counter with respect to the odd counter ninth stage output L0 and twelfth stage output LW in response to the O and O outputs of flipflop 88. In summary, the timing control 80 includes means for controlling the count sequence of the raster scan counters and the frequency of the clot counter in response to a size code and means also responsive to the size code to couple the scan counter outputs in a programmable fashion to the scan line lead L1-L24.
The stroke/dot generator 50 responds to the stroke identifier signals provided by the stroke encoder 40 to provide vertical, horizontal, and slant patterns of dots in accordance with the scan line and dot signals provided by the timing control 80. The slant, vertical and horizontal stroke forming networks are shown in FIGS. 6A, 6B and 6C, respectively.
Referring first to the slant forming networks in FIG. 6A, there is shown an individual logic gating net for each of the slant strokes A1 through A15 (FIGS. 2C and 2D) and B1 through B4 (FIGS. 2E and 2F). For the sake of convenience, only the A1 stroke forming net is illustrated in any detail. It will be appreciated that the remaining slant stroke gating nets contain similar gating structures. The A1 stroke forming net includes three levels of NAND gating in which the third level is a single NAND gate which is enabled by the CA1 stroke identifier signal. The first level of NAND gating serves to match the dot signals with the associated scan line for the Al slant stroke pattern. Thus, with reference to both FIG. 2D and FIG. 6A the A1 stroke is formed on three successive scan lines L16, L17 and L18 on dot times S1, S2 and S3. In the first NAND gate level NAND gates 51-1, 51-2 and 51-3 are enabled by high going scan line signals L16, L17 and L18, respectively, to provide low going output signals in response to high going dot signals S1, S2 and S3, respectively. The single NAND gate 52 in the second level of gating essentially performs an ORING function on the low going output signals of the first level NAND gates to provide a high going signal to the third level NAND gate 53. Thus, NAND gate 53 produces at its output a dot pattern of three low going signals during S1, S2 and S3 dot time on scan lines L16, L17 and L18, respectively. The low going dot sigE patte n A1, as w e ll as the dot signal patterns A2 through A15 and B1 through B4 are all applied to the OR NET 70 (FIG. 3).
With reference now to both FIGS. 2A and 6B the vertical stroke forming network is shown in FIG. 68 to include three levels of NAND gating. The third level of NAND gating includes two NAND gates 54 and 55. The NAND gate 54 is enabled by the scan line grouping signal L-19 to form the vertical strokes V1, V4, V8, V12 and V15. On the other hand, the third level NAND gate 55 is enabled by another scan line grouping signal L4-20 to form the V5 and V1 1 stroke dot pattern. The second level includes NAND gates 56 and 57, each of which essentially performs an ORING function on the low going output signals of the associated first level stroke gating nets. Thus, the outputs of the first level V1, V4, V8, V12 and V15 gating nets are applied as inputs to second level NAND gate 56; and the outputs of the first level V5 and V11 nets are applied as inputs to the second level NAND gate 57.
The first level of vertical gating combines the vertical stroke identifier signal with their associated dot signals and associated vertical inhibit signals and line grouping signals, if any. For instance, the V12 vertical dot pattern is always employed in its entirety in one exemplary character font. Since the first level vertical gating nets employ similar gating structures, only the V15 net is illustrated in detail as an example.
The V15 net includes two levels of NAND gating, the second level of which is a single NAND gate 58 enabled by the stroke identifier signal CV15 at $15 dot time. The first level NAND gates 59-1, 59-2 and 59-3 serve to inhibit the second level NAND gate 58 during the scan lines L5-8, L5-11 and L16-19, respectively. Thus, for example, in the formation of the normal sized numeric character 9" (FIG. 1A) NAND gate 59-1 is active during scan lines 5 through 8 to inhibit formation of the V15 stroke. From scan line L9 through L15 none of the NAND gates 59-1, 59-2 and 59-3 is active such that NAND gate 58 provides at its output a sequence of negative going signals at S15 dot time, one such signal during each of the scan lines L9-L15. During scan lines L16 through L19, first level NAND gate 59-3 is active to inhibit NAND gate 58 from forming the remainder of the V15 stroke pattern. The NAND gate 59-2 is active only in the formation of the character 6" to provide the inhibiting function during scan lines 5 through 11. The ou tput V l 5 2f NAND gate 58 is then ORED together with the V1, V4, V8 and V12 first level outputs by second level NAND gate 56. The output of NAND gate 56 is then passed by third level NAND gate 54 to OR NET (FIG. 3).
Although the longer vertical strokes V5 and V11 are formed by a separate gating chain, all of the strokes could be formed by a single third level gate so long as such third level NAND gate is enabled for scan lines L4-20 and appropriate inhibiting signals are added or modified in the first level gating structures.
With reference now to both FIGS. 23 and 6C, the horizontal stroke forming network is shown in FIG. 6C to include a number of gating nets, one for each of the horizontal strokes H5, H9, H12, H15 and H19. Since all of the horizontal forming nets employs similar gating structures, only the H5 net is illustrated in detail as an example.
The horizontal stroke H5 net includes a flip-flop 60 which is set by either of the NAND gates 61-1 or 61-2 and is reset by the NAND gate 61-3. Although the flip-flop 60 may be any suitable flip-flop which performs the set and reset function, it is illustrated as a pair of NAND gates 60-1 and 60-2 which are cross-coupled to one another. The NAND gate 60-1 receives set signals from the outputs of NAND gates 61-1 and 61-2. The NAND gate 60-2 receives an enable input from the scan line L5 signal and reset inputs from the output of NAND gate 61-3 and from the complement of the S17 dot signal.
The H5 net is capable of forming a horizontal stroke on scan line 5 of different lengths, including those between either dot times S1 and S15 or between dot times S4 and S15. Thus, NAND gates 61-1 and 61-2 respond to a selected one of the stroke identifier signals SH5S1 and SH5S4 at S1 and S4 dot times, respectively, to selectively provide a low going set signal to the flip-flop NAND gate 60-1. Prior to S1 or S4 dot time, as the case may be, it is assumed that the outputs of NAND gates 60-1 and 60-2 are low and high, respectively. Thus, a set signal at 81 or S4 time causes the output of NAND gate 60-1 to go high and the output of NAND gate 60-2 to go low, all other inputs to NAND gate 60-2 being high at this time. At S14 time, NAND gate 61-3 responds to the stroke identifier signal RH5S14 to provide a low going reset signal to NAND gate 60-2. NAND gate 60-2 responds to the reset signal at S14 time to force its output high and to force NAND gate 60-1 to change its state. The S17 dot signal is normally high and dips low at S17 time in order to assure that the flipflop 60 is reset at the end of each character space. The scan line signal L is high only during scan line L5 and is low for all other scan lines such that iE-flop 60 is enabled only during s n B LS. The output H5 together with the outputs 1%, H12, H and l-T9of the other horizontal stroke forming nets are applied to the OR NET 70 (FIG. 3).
in summary, there has been described a raster scan generator embodying the invention which is capable of displaying different sized characters with relatively high resolution on a conventional television picture tube. As pointed out previously, the illustrated raster scan generator and character font are by way of example only; and other character fonts and different gating structures capable offorming vertical, slant and horizontal dot patterns may be employed.
What is claimed is:
1. In display apparatus for generating symbol patterns for display on a display device which exhibits a television raster scan line pattern wherein rows and columns of symbol spaces are defined by sequences of scan line signals and sequences of dot signals, respectively, the improvement comprising:
means for generating said scan line signal sequences and said dot signal sequences;
means for providing symbol codes representative of a symbol set, the symbols of which are formed from a common set of dot patterns including horizontal, vertical and slant lines, the horizontal and vertical directions corresponding to the row and column directions, respectively;
means responsive to said symbol codes to provide horizontal, vertical and slant line identifier signals in combinations determined by each code;
means including horizontal, vertical and slant line forming circuits responsive to said horizontal, vertical and slant identifier signals, respectively, and to said raster scan line and dot signals to provide horizontal, vertical and slant dot pattern signals in accordance with said coded combinations of identifier signals; and
means for combining said horizontal, vertical and slant dot pattern signals into a single dot pattern signal representative of said symbol codes.
2. The invention according to claim 1 wherein said identifier signal means responds to different character codes to provide line length identifier signals indicative 'of different lengths of at least one line in said common set; and wherein at least one of said horizontal,'vertical and slant line forming circuits includes a variable length line forming network responsive to said line length identifier signals to provide corresponding-dot pattern signals indicative of said one line with different lengths in accordance with said difierent symbol codes. 3. The invention according to claim 2 wherein said one variable line length network is a horizontal line forming network; and v wherein first and second ones of said length identifier signals initiate the horizontal dot patterns signal of said network at different dot signal times along a like scan for any symbol space.
4. The invention according to claim 3 wherein a third one of said length identifier signals terminates the horizontal dot pattern signal of said network at another later occurring dot signal time.
5. The invention according to claim 2 wherein said one variable line length network is a vertical line forming network which is normally enabled at a selected dot time for each of n consecutive scan lines in a symbol space; and
wherein a first one of said length identifier signals inhibits said network during predetermined ones of said 11 scan lines at said selected dot time.
6. The invention according to claim 1 wherein each of said horizontal, vertical and slant line forming circuits includes a number of line forming networks corresponding to the number of horizontal, vertical and slant lines, respectively, in said common dot pattern set; and 1 wherein any one of said networks is enabled by a corresponding one of said identifier signals in response to different symbol codes.
7. The invention according to claim 6 wherein said identifier signal means responds to different symbol codes to provide line length identifier signals indicative of different lengths of at least one line in said common set; and
wherein at least one of said horizontal, vertical and slant line forming networks is a variable length line forming network responsive to said line length identifier signals to provide corresponding dot pattern signals indicative of said at least one line with different lengths in accordance with said different symbol codes.
8. The invention according to claim 7 wherein said at least one variable line length network is a horizontal line forming network; and
wherein first and second ones of said length identifier signals initiate the horizontal dot patterns signal of said network at different dot signal times along a like scan line for any symbol space.
9. The invention according to claim 8 wherein a third one of said length identifier signals terminates the horizontal dot pattern signal of said network at another later occurring dot signal time.
10. The invention according to claim 7 wherein said one variable line length network is a vertical line forming network which is normally enabled at a selected dot time for each of n consecutive scan lines-in a symbol space; and
wherein a first one of said length identifier signals inhibits said network during predetermined ones of said n scan lines at said selected dot time.
1 l. The invention according to claim 6 wherein a selected one of said slant networks is enabled on consecutive scan lines at consecutive dot times. I
12. Display apparatus for displaying symbols on a display device which exhibits a television raster scan line pattern, said apparatus comprising:
means for generating a plurality of dot signals in repetitive sequences during said scan lines to correspond to elemental dots on said display device to divide said device in a first direction into a plurality of symbols spaces;
means for generating a plurality of line signals in repetitive sequences in synchronism with said scan lines to divide said device in a second direction into a plurality of rows;
the combination of a plurality of sequences of said dot signals and a plurality of sequences of said line signals forming a plurality of symbol space areas on said display device;
means for providing symbol size control signals;
means responsive to said control signals to change the count sequence of said scan line counting means; and
means responsive to said control signals to change the frequency of said dot signals.
13. The invention according to claim 12 wherein said scan line generating means includes a scan line counter having n stages to produce a count sequence of n,- and wherein said count changing means responds to said control signals to cause said counter to produce a count sequence of nm, where n and m are integers.
14. The invention according to claim 13 wherein said dot signal generating means includes a dot counter; and
wherein said frequency changing means includes means responsive to said control signals for changing the frequency of said dot counter.
15. The invention according to claim 12 wherein said do! signal generating means includes a do: responsive to said contra signal for changing the frequencounter which produces said plurality of dot signals; and y f 581d dOl rwherein said frequency changing means includes means na: 1- n-
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