|Publication number||US3668688 A|
|Publication date||Jun 6, 1972|
|Filing date||Dec 29, 1969|
|Priority date||Dec 29, 1969|
|Also published as||CA932428A1, DE2064298A1, DE2064298B2, DE2064298C3|
|Publication number||US 3668688 A, US 3668688A, US-A-3668688, US3668688 A, US3668688A|
|Inventors||Schmersal Larry J|
|Original Assignee||Owens Illinois Inc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (22), Classifications (7), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Schmersal 51 June 6,1972
 GAS DISCHARGE DISPLAY AND MEMORY PANEL HAVING ADDRESSING AND INTERFACE CIRCUITS INTEGRAL THEREWITH  Inventor: Larry J. Schmersal, Toledo, Ohio  Assignee: Owens-Illinois, Inc.
 Filed: Dec. 29, 1969  Appl. No.: 888,741
 U.S.Cl.  Int. Cl.  Field of Search ....340/324 R, 315/169 TV, 340/343 ..HOlj 17/48, H05b 41/44 ..315/169 R, 169 TV; 340/166 R, 340/324 R, 343
3/1970 Merryman et a1. ..340/324 4/1970 Holz ..315/169 [5 7] ABSTRACT There is disclosed a method and apparatus for reducing the number of wires to gaseous discharge display/memory panels. Logic circuit circuits are combined with interface pulsing circuits which are electrically floated on the sustainer voltage for the panel and the interfacing and logic circuits are mounted integrally on panel support plate extensions. In addition to conductor arrays forming matrix cross points for locating a discrete discharge site, edge extension of support plates carry directly on the plates or on substrates bonded thereto additional conductor arrays to the interfacing and logic circuits which, in turn, are electrically connected to the matrix conductor arrays for supplying sustaining and discharge condition manipulating potentials thereto.
8 Claims, 5 Drawing Figures PATENTEDJUH 6 m2 SHEET 2 OF 3 FIG. 2A
COLUMN CONDUETGR PANEL ROW CONDUCTOR Rl28 GAS DISCHARGE DISPLAY AND MEMORY PANEL HAVING ADDRESSING AND INTERFACE CIRCUITS INTEGRAL THEREWITH CROSS REFERENCE TO RELATED APPLICATIONS The invention is related to the subject matter of Baker et al. application Ser. No. 686,384, filed Nov. 24, 1967 now US. Pat. No. 3,499,167; Nolan application Ser. No. 764,577, filed Oct. 2, 1968, Johnson et a]. application Ser. No. 699,170, filed Jan. 19, 1969 now US. Pat. No. 3,618,071, Schmersal application Ser. No. 851,131, filed July 18, 1969 now US. Pat. No. 3,592,127; I-Ioehn application Ser. No. 856,373, filed Sept. 9, 1969 as well as others owned by the common assignee hereof.
BACKGROUND AND SUMMARY OF THE INVENTION The present invention relates to interface and logic circuit arrangements for use with gaseous discharge display/memory panels having a pair of transverse conductor arrays supplying relatively high operating potentials to discrete discharge sites.
Gaseous discharge display/memory panels to which the invention pertains include a thin gaseous discharge medium under pressure bounded by dielectric charge storage members and a pair of transverse conductor arrays forming a cross point matrix for supplying operating potentials to discrete discharge sites in the gaseous medium. Such operating potentials include a periodic sustaining potential applied to all conductors in an array and discrete discharges at selected discharge sites (the cross points of the matrix conductor array e.g. crossing points of column and row conductors) are manipulated on and off by selectively applied relatively high voltage pulses added to the periodic sustaining potential. The sustaining voltage is of such amplitude that it is insufficient by itself to initiate a discharge at any of the cross points. Such panels have an inherent electrical memory constituted by the storage of charges produced by an initial discharge on the dielectric charge storage members which stored charges constitute electrical potentials opposite the applied potentials which created them and hence terminate the discharge. The potential due to store charges, being in the same polarity direction of the succeeding half cycle of applied sustaining potential, aid in initiating the next discharge so that for each cycle of applied sustaining potential there will be at least two discharges. Since the charges collect rapidly, each discharge lasts for a fraction of a half cycle of applied potential so that light production is a sequence of short flashes. The repetition rate is high enough (for a 50 KH sustainer there will be 100,000 flashes per second) that the light appears continuous to the human eye. However, once a sequence of discharges at a selected matrix cross point has been initiated, the sequence will be maintained by the sustaining potential. A sequence of discharges, once initiated and maintained by the sustaining voltage, may be terminated, e.g. a selected site turned off, in a similar manner by applying an erase signal voltage to selected columns and row conductors locating an on site (one at which a sequence of discharges has been initiated) which is to be turned off (termination of the sequence of discharges). The timing of such erase or 01? signal voltage pulses may be in the manner disclosed in Johnson et al. application Ser. No. 699,170 filed Jan. 18, 1968 now US. Pat. No. 3,618,071. In turning off a discharge site the objective is to modify the amount of charge stored so that the potential or field due to the stored charge is insufficient when added to the field due to applied potential to produce a discharge on the following half cycle.
Gas discharge panels of the type described above require relatively high operating voltages, the magnitude of which depends upon, among other things, the discharge gap or distance between dielectric storage surfaces, gas mixture and pressure, and thickness of the dielectric. For example, with a gas mixture consisting of 99.9 percent neon atoms and 0.1 percent argon atoms at a pressure of from about 2 atmospheres to about 1 atmosphere, a discharge gap of 4-6 mils; and a dielectric l-2 mils thick, the sustaining voltage is in the range of about 335 to 350 volts peak to peak at a frequency or period rate of 30 to 50 KH and a high voltage discharge manipulating pulse preferably of about the same amplitude.
In a panel having a 4 X 4 inch display area and with column conductors being spaced on 30 mil centers with a like spacing for the row conductors there will be approximately 132 column conductors and a like number of row conductors and approximately 17,000 discrete cross points or discrete discharge sites. For discharge site selection purposes e.g. addressing, each column conductor and each row conductor normally use a separate high voltage address pulse, the initiation of a discharge at a selected site or matrix cross point being determined by the coincidence of high voltage pulses on the column and row conductors, half of the high voltage on the selected column conductor and half of the high voltage, but of opposite relative polarity, on the row conductor, in the respective arrays in algebraic adding relation to the sustaining voltage. The periodic sustaining voltage is applied in a similar fashion: one half is applied to all column conductors and one half, out of phase, is applied to all row conductors.
As the size of the display area increases, assuming the same degree of resolution (conductors spaced on 30 mil centers) the number of wires to the panel increases proportionately. Likewise, when the degree of resolution is increased by reducing the spacing between conductors (assuming the same size display area) the number of wires to the panel increase in an inversely proportional manner. For example, as the spacing between individual row and/or column conductor is reduced, say conductors spaced on 20 mil centers, the number of wires carrying operating potentials to the panel increases. The present invention solves wiring this problem by integrally combining logic and high voltage interface pulsing circuits on the panel. Except for the sustainer voltages, and high voltage supply to the interface pulsing circuits, a reduced number of wires and external coupling circuitry to the panel per se as well as a reduction in the number of high voltage carrying wires is achieved by providing low voltage logic circuitry integrally mounted on the panel, preferably on edge extensions of glass support plates, said logic circuitry preferably including selector circuitry in one or more integrated circuit packages for selecting group or sectors of panel conductors and further logic circuitry for selecting one or more conductor lines (row and column) to which high voltage discharge condition manipulating pulses are applied.
The selector circuit means and said logic and interface circuits are included in integrated circuit packages having external terminals which are arranged to electrically engage one or more conductor patterns on the support plate extension or on separate substrates having output terminals electrically engaged with the respective row and column conductors.
The selector logic circuits as well as the high voltage pulser circuits are floated on the panel sustainer voltage which permits combining of the logical control and decoding function thereof. While this requires isolation coupling to the selector logic circuitry as well as the logic circuitry associated with the high voltage interface pulser circuits, since the number of input data signals are reduced, the number of couplers are reduced by the same amount, there is no significant additional expense or complexity introduced.
BRIEF DESCRIPTION OF THE DRAWINGS The above and other features, aspects and details of the invention will become more apparent from the following specification when considered with the accompanying drawings illustrating a preferred embodiment of the invention wherein:
FIG. 1 is a block diagram illustrating the logic and pulsing circuits floating with respect to the power supply configuratron.
FIG. 2A illustrates the invention as applied to a gas discharge display/memory panel wherein edge extensions of the panels are provided with selector logic circuits and gatepulser circuits for supplying sustaining potentials to the row and column conductor arrays along with selectively applied discharge condition manipulating pulses,
FIG. 2B is a partial side elevational view of a panel incorporating a modification wherein the selector logic and gatepulser integrated circuit packages and conductor arrays thereto are on a separate substrate,
FIG. 3 is a block diagram showing the arrangement of two gated high voltage pulser sections in a package, two chips in a single integrated circuit package with terminal leads for engagement with specific conductor arrays and conductor configurations on the panel edge extension.
FIG. 4 is a block diagram of the selector logiccircuitry in an integrated circuit package.
DESCRIPTION OF A PREFERRED EMBODIMENT With reference to the drawings, particularly FIG. 2A, a gas discharge panel is constituted by a pair of support plate members 11 and 12, respectively, each of which has on opposing surfaces thereof row and column condcutor arrays 13 and 14 which cooperate to define a matrix locating the discharge sites, and a pair of thin dielectric members 15 and 16, respectively, overlying or coated on the conductor arrays and the support plates. Plates 1 1 and 12 are joined by a spacer sealant means 17 to thus define a thin gas discharge chamber containing a gaseous medium under pressure which produces a copious supply of charges during discharge at any selected cross point, such charges being collected on and stored within the discrete areas on the surfaces of the dielectric members 15 and 16, respectively.
The gas chamber is under about 10 mils thick (dielectric surface to dielectric surface) and, preferably, the ratio of discharge gap to conductor spacing to avoid certain forms of cross talk being about 1 to 5. Transversely oriented row and column conductor arrays 13 and 14 are supplied with operating potentials for selectively effecting discharges within the thin gas chamber between selected cross points. The gas is one which is under relatively high gas pressure so as to localize the discharges within the chamber and to confine charges produced on discharge to within the volume of gas in which they are created. As set forth in the aforementioned Nolan application, the gas may be a mixture of 99.9 percent atoms of neon and about 0.1 percent atoms of argon and at a pressure preferably from about 0.2 atmosphere to about 1 atmosphere. Other gas compositions and pressure may be used.
Referring now to FIG. 1 the gaseous discharge display/memory panel 10 is shown in a simplified form having eight row conductors R1, R2, R3, R8 and eight column conductors C 1, C2, C3 C8, the crossing points of the row and column conductors in the panel matrix defining addressable discrete discharge sites, each of which is selectively addressable by application of proper potentials to any selected row conductor and any selected column conductor. Input information from a computer, teletype unit or telephone line, from a remote input unit or any other similar forms of digital data input device supplies information in binary coded form on row information input conductors X X and X and column information input conductors Y Y and Y Such information is coupled into row and column decoding logic circuits and 31, respectively by transformers TX TX TX, for the row conductors and transformers TY TY and TY, for the column conductors, it being appreciated that the transformer coupling is for isolation purposes and that other forms of isolation coupled may be coupling as for example, photon coupling as disclosed in my application, Ser. No. 851,131 filed July 18, 1969 now US. Pat. No. 3,592,127. Binary information as coupled by transformers TX TX and TY TY is applied to logic circuitry 30 and 31, respectively, which units perform logical operations required to convert (e.g. decode) the input information into a form suitable for address location (e.g. discharge site selection) in the panel. In the arrangement shown in FIG. la, since there are three binary inputs there will be eight outputs (2" 2 8), one for each logic output conductor LR-l, LR-2 LR-8 and LG], LC-2 LC-8. Each output is used to actuate a high voltage pulsing circuit included within pulser blocks labeled 32 and 33 which circuits supply high voltage pulses algabraically added to sustaining voltages from sources VSR and VSC and applied to the row and column conductors, respectively, to selectively manipulate the discharge condition at any site defined by the crossing of a row and column conductor. It may be noted that the high voltage interface pulsing circuits 32 comprise transistors of the NPN type whereas transistors in the high voltage interface pulsing circuits contained within unit 33 are of the PNP type and that the high voltage direct current sources EPR and EPC are poled in a direction to correspond thereto. Likewise, it will be noted that sustaining voltage source VSR for the row conductors is relatively positive at the instant shown whereas the sustaining voltage source VSC for the column conductors is relatively negative at the instant shown. In other words, the sustaining potentials applied to the row conductors are 180 out of phase with respect to the sustaining potentials applied to the column conductors and vice versa. In this way, one-half of the required sustaining potential may be applied to the row conductors and one-half of the sustaining potential may be applied to the column conductors. At the same time, by providing synchronized but separate sustaining voltage sources for the row and column conductors, the discharge panel 10 essentially floats with respect to ground. Moreover, the high voltage direct current potential EPR and EPC which are used to form or generate the high voltage discharge condition manipulating pulses in the interface circuits 32 and 33, respectively, are floated on or have as a common reference potential the instantaneous magnitude of the sustaining potential. Likewise, the low voltage sources ELR and ELC are used to supply operating potentials to the logic circuits 30 and 31 have their respective operating potentials connected so as to float on the sustaining potentials through the high voltage pulsing sources EPR and EPC respectively. Thus, by .floating the logic circuitry with the pulsing circuits, it is possible to combine certain logical control and decoding functions in the logic thereby reducing the number of control wires going to the gas discharge display panel. However, floating the logic and pulses on the sustaining voltage does have a drawback in that the information from the data source which is ground referenced, cannot be communicated by wire directly to the floating logic which is referenced to the sustaining generator and therefore, it requires signal couplers to couple the signal into the logic circuits. As mentioned above, such coupling can be provided, including the isolation necessary, by transformers, as shown, or by photon couplers as disclosed in my earlier referenced application. As will be explained more fully hereinafter, not shown in FIG. 1 is the necessary inverters for inverting one or the other of the outputs from logic circuits 30 and 31 to a proper polarity for operating the transistor circuitry in high voltage interface pulsing circuits 32 and/or 33.
In a typical example, the sustaining voltages VSR and VSC may be a sinusoidal waveform having 175 volt peak amplitude (however, any other periodic waveform may be used, as for example, a square wave, triangular wave, etc.); high voltage direct current sources EPR and EPC may be about volts; and the low voltage logic circuit supplies ELR and ELC about 4 volts. It will be understood that these voltage parameters are given by way of example and are not intended to be limiting. For example, the high voltage pulsing circuits may require higher amplitude input trigger voltages in which case the logic circuit input voltages may be higher or require amplification.
As described above the panel 10 has 128 row and 128 column conductors in arrays 13 and 14, respectively, each spaced on 20 mil centers (e.g., a 2.56 inch square display area with 16,384 addressable discharge sites or cross points). Using the base 8, the row conductors are arbitrarily divided into groups of eight so there will be 16 groups of row conductors (RI-8, R9-l6, R12l-l28) and 16 groups of column conductors (Cl-8, C9-16 C121-128). The respective groups of row conductors and column conductors may then be divided into sub groups or panel sectors. As for example, upper sector I and lower sector II for the row conductors in array 13 on support plate 11 and a similar grouping and sectoring arrangement of groups is provided for the conductors of conductor array 14 on plate 12.
Each group of conductors in row conductor array 13 is served from an integrated circuit package 40-1-1, 40-1-2 40-11-8, therebeing one suchpackage serving each group of eight row conductors. In FIG. 3, the arrangement of two gated high voltage pulser sections in package 40-1-2 two integrated circuit chips 50, 51 per integrated circuit package with external terminals for engagement with a specific group of eight conductors in either array and conductor configurations on the panel edge extensions or a separate substrate carried on the extensions (as indicated in FIG. 28). It will be appreciated that as many chips per package may be included as desired, two per package being shown for purposes of illustration.
Referring now to FIG. 3, the internal components of a gated high voltage pulser package 40-I is illustrated and as explained above, two integrated circuit chips 50 and 51 are indicated, with four high voltage pulsers 52 per chip (which may be of the type shown in Johnson application, Ser. No. 821,306, filed May 2, 1969 now U.S. Pat. No. 3,614,739; it being appreciated that other forms of high voltage pulsing circuits are contemplated). In addition, each integrated circuit chip is provided with four AND gate logic elements 54, one for each high voltage pulser 52 (such logic AND gate elements and high voltage pulser circuits being further disclosed in Johnson application, Ser. No. 888,743 now U.S. Pat. No. 3,61 1,296, filed concurrently herewith and entitled Driving Circuitry for Gas Discharge Panel", it being appreciated that other forms of logical gates are contemplated). Finally, each integrated circuit chip may be provided with an inverter circuit 56 to permit logic gates 54 to function in the normal manner. It will be appreciated that if the data inputs on edge conductors 11-18 inclusive are of proper polarity, then the inverter circuit 56 may be eliminated. Each circuit chip 50 is provided with a series of input power and signal terminals 1-8 inclusive on chip 50 and 1-4 and 9-12 on chip 51 and a series of output terminals 13-16 for chip 50 and 17-20 for chip 51. The input terminals 1-8 are on chip 50 and 1-4 and 9-12 on chip 51 wired internally in the circuit package to external package terminals having corresponding numbers. As illustrated diagrammatically in FIG. 3, external terminal 1, is connected internally by a wire 57 to input terminal or pad 1 on circuit chip 50. Similarly, external package terminal 2 is internally connected to input terminal or pad 2 of circuit chip 50 as well as input terminal or pad 2 of circuit chip 51. In a similar fashion, the remaining of the input and signal and power terminals 2 and 3 are connected to terminals 1-8 of circuit chips 50 and 51. Output terminals numbered 13, 14, 15 and 16 of chip element 50 are connected by wires to output external terminals 13, 14, 15 and 16 and, in a similar fashion (although not shown), output terminals 17, 18, 19 and 20 on circuit chip element 51 are connected to package external terminals 17, 18, 19 and 20. In the manner illustrated, external package terminals 13-20 are electrically connected directly to the panel row conductors, which in the instance shown, are row conductors R-9, R- R-16. Only the connections from terminals 13 and 20 are shown on the drawing.
Except for the enabling pulses which are delivered from selector logic circuitry by row selector enable pulse conductor 81-2 on external input terminal 1, the input power and signal to all of gated high voltage pulser packages by a common conductor array constituted by conductors 8, 9, 10 18, which carry signals in accordance with the schedule set forth below, this conductor array is constituted by a plurality of linear conductors on the plate extensions (or a separate substrate or circuit board C.B., FIG. 2B) which extend in a direction normal to the row conductor array 13 and has the same spacing as the spaced input power and input signal terminals or pads and are electrically engaged therewith. However, it should be noted that the input power and signal terminals (numbered 2-12) on the packages are staggered or alternated on opposite sides thereof and are spaced for alternate electrical engagement 6 with the conductors in the array constituted by conductors 8, 9, 18. This permits sufi'lcient room for alignment and engagement of the external package conductor terminals with the input power and signal conductor array. The individual external terminals on the packages may be in simple pressure contact with the conductor arrays on the panel edge extensions (or the substrate carrying same). Alternatively, a fusion bond may be achieved by application of mild heat and sonic vibration.
The following schedule identifies the supply and signal voltages which are applied to the individual conductors.
Conductor Function 1 Strobe-Sector selector Logic I 2 Strobe-sector selector Logic II 3 Sector Selects LogicPower 4 Sector Select Logic Power 5 Sector Select Logic Data 6 Sector Select Logic Data 7 Sector Select Logic Data 8 Input line for sustainer power supply (terminal 8, FIG. 1) 9 Input line for High Voltage Power Supply to Pulser (terminal 9, FIG. 1) 10 Input line for low voltage power supply to logic (terminal 10, FIG. I) l 1 Data Conductor 1 12 Data Conductor 2 13 Data Conductor 3 14 Data Conductor 4 15 Data Conductor 5 16 Data Conductor 6 17 Data Conductor 7 18 Data Conductor 8 The circuitry illustrated in FIG. 3 operates in the manner described in Johnson application Ser. No. 888,743, filed Dec. 29, 1969 now U.S. Pat. No. 3,611,296 entitled Driving Circuitry for Gas Discharge Panel." Briefly, gated high voltage pulser 52 and logic circuit 54 serve to translate low level logic signals to high level pulse voltages which are algebraically,
added to the sinusoidal sustainer potential. Thus, the coincidence of an enabling pulse on external package terminal 1 (row selector bus conductor S-I-2) and a logic pulse on any one of data input terminals 11-18 produces an output from the selected logic elements 54 to which the coincidence pulses have been applied which serve to trigger the high voltage pulser 52 associated therewith to produce a high voltage discharge condition manipulating pulse on the associated output terminal. For example, a pulse on row conductor SI-2 enables the four AND gates 54 on circuit chip 50 for operation as well as the four AND gates 54 on circuit chip 51. Hence, if there is a logic pulse on any one of data input terminals 1 1-18 (which are in engagement with the conductor array carrying signal input and power to the gated pulser packages 40-1) there will be an input signal applied to the corresponding AND gates 54 connected thereto with a corresponding output applied to trigger a corresponding high voltage pulser 52. As a consequence, thereof, a high voltage pulse is generated in gated high voltage pulser 52 which is algebraically added to the sustainer voltage which is likewise passed therethrough and this combined voltage appears at the output terminals (right edge of integrated circuit package) and on the selected row conductor 40-1-2.
In connection with the above description of the manner in which high voltage pulses are generated and applied to the panel row conductors, it will be appreciated that a corresponding and simultaneous action is occurring for the respective column conductors and the gated high voltage pulser packages associated therewith. In other words, at a selected cross point of a row and column conductor, two high voltages pulses of opposite relative polarity are generated, algebraically added to sustaining voltages which are continually applied to all conductors in the array to manipulate the discharge condition of any selected discharge site.
In the panel illustrated in FIG. 2A, there are 128 row conductors and 128 column conductors in arrays 13 and 14, respectively. And as described earlier, the conductors are arbitrarily divided into two sections of 64 conductors each, with each eight conductors in a section being controlled by an individual gated high voltage pulser package. An enabling pulse is required to the logic circuitry 54 for each gated high voltage pulser. While such enabling pulses may be supplied by individual circuitry not directly associated with or mounted on the panel, preferably, in order to reduce the circuitry further as well as reduce the number of conductors directly to the panel, in a preferred embodiment of the invention, sector selector logic circuits I and II are provided, each of which is capable of enabling eight gated high voltage pulser packages, either individually or in combination.
Such a circuit is shown in FIG. 4 in a greatly enlarged view of an integrated circuit package 60 which contains the sector selector logic for section I encompassing the first 64 row conductors in array 13.
As illustrated in FIG. 4, the selector logic circuitry comprises a conventional AND gate tree which functions as a binary decoder (or some other unique code) to expand unique (permutated) address signals. The circuit per se is conventional and is composed of a series of AND gates 61 and associated inverters 62 on an integrated circuit chip element 63 having input power terminals or pads 2 and 3 connected to external package connectors 2 and 3, respectively, as shown, and signal input terminals or pads 1, 4, 5 and 6 connected to signal input terminals 1, 4, 5 and 6 on the external edges of the package as illustrated. Terminal 1 constitutes a strobe input terminal for receiving a strobe signal from conductor 1 which is effective to select for operation any one of the first 64 conductors in array 13. For there to be an output on any one of output terminals or pads 7, 8, 14 of integrated circuit chips 63, there must be an input logic signal on input terminal 1. An output logic signal on any one of terminals 7, 8 14 is produced through the decoding by the AND gate tree of the permutated binary inputs on terminals 4, 5 and 6. It will be appreciated that the decoding function performed by this logic circuitry is conventional in nature in that the permutative code carried by the presence or absence of input signals on terminals 4, 5 and 6 (assuming the presence of a strobe signal) is capable of producing an output on any one of terminals 7, 8 14, e.g. therebeing eight outputs which are respectively connected output terminal 7, 8 14 at the right hand edge of integrated circuit package 60-I. As shown, the external package output terminals 7, 8 14 are in electrical engagement with row select conductor array SI-l, SI-2 SI-8.
It is to be understood that other forms of logic and gate circuitry may be easily adaptedv to perform the functions described above.
The external input power and signal terminals 2, 3 6 on packages 60-I and 60-II are in electrical contact or engagement with the conductor array constituted by conductors 3, 4 7, with a strobe signal on conductor 1 serving to activate sector logic I in package 60-I and a strobe signal on conductor 2 serving to activate selector logic circuit II in package 611-.
As described above, in connection with FIG. 1, the supply voltages for the high voltage pulser circuits as well as the logic circuits are floated on the sustainer voltage. In FIG. 1 the logic circuitry is illustrated as single blocks 30 (row) and 31 (column) whereas in the equivalent logic circuitry in the expanded description and disclosure of FIG. 2A, two logic sections are shown. It will be appreciated that the floating low voltage logic supplies applied between conductors 9 and 10 may be arranged and connected externally of the panel to supply both logic circuits (the ones in the selector logic packages 60 and the ones in the gated pulser packages 40 for the row conductors, and a similar arrangement for the column addressing circuits) or the connectionmay be made by conductors on the plate edge extensions on circuit board CB (FIG. 2B). In other words the operating potentials for all logic circuits carried on the plate edge extensions are preferably floated on the sustainer potential in the manner indicated in FIG. 1 and the connections to achieve this may be made directly on the panel or externally thereof.
In the 128 x 128 panel array shown in FIG. 2A, there are 18 supply and signal input conductors l to 18 which terminate at the edge of the plate edge extension for the row conductors and a corresponding number terminating at the edge of the plate edge extension for the column conductor array so that there are only 36 wires (to control 256 row and column conductors) to the panel 10 required from external circuitry, only two of which carry the high voltage sustaining potential (one for the row conductors and one for the column conductors, to carry the high voltage direct current potential to the pulsers circuits 52, one for the row pulsers and one for the column pulsers). The remaining conductors (l, 2, 5, 6, 7, 11-18) are low voltage logic signal conductors so that the discharge panel 10 essentially appears as a low voltage device.
The number of signal wires to panel 10 may be further reduced by providing the panel with a signal storage device such as a conventional integrated circuit shift register (not shown) for receiving data to be stored and applied to conductors 1 1-18 (for example), such storage device being mounted on the panel plate extension with its output terminals in electrical engagement with conductors ll-18.
As indicated above, it is not necessary that all conductors in an array be served from circuitry mounted on a single plate edge extension. Thus, alternate conductors in arrays 13 and 14 may be served from right and left side plate edge extensions for the row conductors in array 13 and top and bottom plate edge extensions for the column conductors in array 14. Instead of alternate conductors being served in this manner, al-
ternate groups of eight (for example) conductors in an array may be served from logic and pulsing circuitry on one plate edge extension with the interposed groups served from circuitry on the opposite plate edge extension. Or, one-half, onethird, one quarter, etc. of the conductors in an array may be served from logic and pulser circuitry on one plate edge extension with the remainder being served from logic and pulser circuitry on the opposite plate edge extension. Although preferable, it is not necessary that the number of conductors in an array served from circuitry on one plate edge extension be equal to the number of conductors in the same array served from circuitry on an opposite plate edge extension.
While the conductors in arrays 13 and 14 are shown as having equal spacing, it is apparent that this is not necessary; where alphanumeric characters are to be written into the display area, some conductors in the arrays may be eliminated or no operating potentials are supplied to such conductors.
Conductors l-18 on the plate edge extensions extend to the edge of the panel to permit slip-on or edge connectors in the manner of printed circuit boards. In FIG. 2B, the sector select logic 60 and gated pulser packages as well as the conductor arrays serving same are on a conventional printed circuit board CB which is integrally mounted on the plate edge extensions, with the row output conductors which are electrically connected to the external output terminals of the gated pulser packages 40 (for the row conductors, for the column conductors) being extended over or through edge E of the circuit boards CB to make electrical contact or connection with each row or column conductor, respectively. An edge (not shown) of circuit boards CB carrying conductors l-l8 may be extended to facilitate application of a conventional printed circuit board edge connector strip. While it is preferred that circuit boards CB overly and be secured to the plate edge extensions for support purposes, it will be appreciated that this is not necessary. Thus, it is within the contemplation of this invention that the row and column conductors extend towards the extreme edges of the plate extensions and that the edges of circuit boards CB carrying row and column arrays operating potentials be provided with an edge connector (not shown) for making individual connection to the conductors in there respective row and column arrays with signal and operating potentials to the circuitry carried on the printed circuit board being supplied by way of a separate connector strip to conductors l-18.
thereon, the other of said plates having a row conductor array thereon, each array comprising a plurality of spaced parallel conductors, spacer-sealant means joining said plates in spaced relation to define a thin gas discharge chamber between the plates, thin insulating means on the conductor surfaces within said gas chamber, said plates being oriented such that said row and column conductor arrays are at transverse angles to each other with at least one end of each plate extending beyond the side edges of the other plate, respectively,
the improvements comprising,
first circuit means on said plate edge extensions, respectively, for receiving and uniformly supplying sustaining potentials to said row and column conductors, respectively, and for supplying discharge manipulating pulse potentials to selected row and selected column conductors, respectively, said sustaining potentials and said discharge manipulating potentials being algebraically added by said first circuit means for application to said row and column conductors, respectively, and
selector circuit means on said plate edge extensions for receiving and decoding coded address signals and controlling the application of said discharge manipulating pulse potentials to selected row and column conductors, respectively, according to the address carried by said address signals.
2. The invention defined in claim 1 wherein said row conductors and column conductors in each of the arrays, respectively extend a substantially equal distance beyond said spacer sealant means, respectively,
said first circuit means being included in at least one integrated circuit package, said package having spaced input power and input signal terminals on an external surface of said package, and output signal terminals on an external surface of said package having the same spacing as said row and column conductors and engaged therewith, and
a further conductor array constituted by a plurality of linear conductors on each said plate extension, respectively, extending in a direction normal to said row and column conductor arrays, respectively, and having the same spacing as said spaced input power and input signal terminals, and electrically engaged therewith.
3. The invention defined in claim 2 including,
a selector conductor array on each said plate extensions, respectively, the number of conductors in said selector conductor array equalling the number of said integrated circuit packages and each in contact with and electrically engaged with a signal input terminal on a package, respectively,
said selector circuit means being included in at least one integrated circuit package having on one surface thereof spaced input power and input signal terminals and spaced output signal terminals, each said spaced signal output terminal being electrically engaged with one of the conductors in said selector conductor array, respectively,
and a selector input power and input signal conductor array on each said plate edge extensions, respectively each conductor of which is electrically engaged with one of said spaced input power and input signal terminals on said selector integrated circuit package, respectively,
said further conductor array and said selector input power and input signal conductor arrays being extended to a terminal edge of the plate edge extensions on which they are formed and adapted for connection to sources of operating potentials and input date signals.
4. The invention defined in claim 2 wherein the input power and signal terminals on said packages are at opposite sides thereof and being spaced for alternate electrical engagement with the conductors in said further conductor array.
5. The invention defined in claim 3 wherein the input power and si al terminals on said integrated circuit packages are at opposite sides thereof and being spaced for alternate electrical engagement with the conductors in said further conductor array.
6. In a gas discharge display and memory panel having a pair of support plates, each plate having dielectrically coated conductor arrays thereon, spacer sealant means joining said plates in spaced relation to constitute a thin gas discharge chamber with a gas under pressure in said chamber, said conductor arrays being oriented relative to each other to define a plurality of separately addressable discrete discharge sites, the improvements comprising,
circuit means mounted directly on said panel for supplying a I periodic sustaining potential to all said conductor arrays,
logic circuit and high voltage pulse producing means mounted directly on said panel for selectively generating high voltage pulses and algebraically adding same to the periodic potential on selected ones of said conductors in said arrays,
and means on said panel for supplying a permutated low voltage address control signal to said logic circuit and high voltage pulse producing circuit means.
7. In a gaseous discharge panel in which a gas discharge medium under pressure in a thin gas discharge chamber bounded by a pair of parallel dielectric charge storage members respectively backed by row conductor and column conductor arrays wherein the discharge conditions of selected discharge sites defined by selected cross points of selected row and column conductors are manipulated by selectively applied high voltage pulses and discharges once initiated are sustained by a relatively high periodic sustaining voltage applied to all said row and column doncutors and wherein said sustaining voltage is supplied to said conductor arrays such that said panel floats with respect to a point of common potential and said selectively applied high voltage pulses when applied have as a reference point the instantaneous magnitude of said high voltage periodic pulse, the improvements comprising,
a low voltage source of direct current potential, said low voltage source of potential being connected in circuit so as to have as a reference point the magnitude of said high voltage,
selector circuit means having logic circuit elements for selecting row and column conductors, respectively, and initiating the application of said discharge condition manipulating high voltage pulses,
said selector circuit having as its sole source of operating potential said low voltage source of direct current potential, and,
coupler circuit means for isolatingly coupling a coded discharge site selection signal from a data source to said selector circuit,
each of said dielectric charge storage member and associated conductor array is on a non conductive support plate, said plates being joined in spaced apart relation by a spacer-sealant means and the respective ends of said plates extend beyond said spacer-sealant means and wherein said conductor arrays extend on said plates beyond said spacer-sealant and dielectric charge storage members so as to be exposed for electrical connection, and
the respective said selector circuit means for the row conductor and column conductor arrays is directly on said respective plate ends and have electrical output terminals electrically engaging conductors in said arrays.
8. The invention defined in claim 6 wherein said means on said panel for supplying a permutated low voltage address control signal includes a signal conductor array running at a transverse direction to said conductor arrays, respectively.
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|International Classification||G09G3/28, G09G3/288|
|Cooperative Classification||G09G3/297, G09G3/296|
|European Classification||G09G3/296, G09G3/297|
|Jun 9, 1987||AS||Assignment|
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC., SEAGATE,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648
Effective date: 19870323
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC.,OHIO