US 3673579 A
A two-dimensional matrix of semi-conductors is arranged in ordered array as a flat, light emitting and light sensing device activated both electrically and by radiant energy from a penlight to achieve a graphical input and output display by the active or inactive condition of the light emitter with circuitry for control of flow of graphical data into and out of the device for use in conjunction with a digital computer.
Claims available in
Description (OCR text may contain errors)
United States Patent Graven [451 June 27, 1972  Inventor: Robert Michael Graven, 203 Holly Lane,
Orinda, Calif. 94563  Filed: Aug. 26, 1970  Appl. No.: 70,626
52 U.S. CI. ..340/173 LS, 250/213 A, 340/324 A, 340 1725 51 Int. Cl ..G11c 13/04  Field ofSearch .250/213 A,214 P,217 ss; 340/324 R, 172.5
 References Cited UNITED STATES PATENTS 3,309,712 3 19'67 Cole ..340 324 R 3,364,473 1/1968 Reitz ..340/l 72.5 3,559,182 2/1971 Floret ..340/324 A 3,559,307 2/1971 Barrekette .....340/324 A 3,579,225 5/1971 Clark ..340/324 A Primary Examiner-Terrell W. Fears Attomey-Robert '1'. Tipton ABSTRACT A two-dimensional matrix of semi-conductors is arranged in ordered array as a flat, light emitting and light sensing device activated both electrically and by radiant energy from a penlight to achieve a graphical input and output display by the active or inactive condition of the light emitter with circuitry for control of flow of graphical data into and out of the device for use in conjunction with a digital computer.
33 Clains, 24 Drawing Figures 3,673,579 sum us I 15 PATENTEDJum I972 P'ATENTEnJum I972 sum 07 or 15 IN VENTOR.
JROBERT M. GRAVEN BY W - fi i DRAWINGBOARD u, A GRAPHICAL INPUT-OUTPUT DEVICE FOR A COMPUTER BACKGROUND OF THE INVENTION This invention relates generally to registers and in particular to electrical calculators of the hybred type.
Various devices have been used in the past for placing graphical data into a computer and for display of graphical data generated by a computer.
Cathode ray tube displays have been used with a light pen having a photo sensitive cell directed at the display on the surface of the tube to pick out or place a point in the display.
Other devices use a flat matrix of electrical terminals which are connected to a computer and a metal stylus also connected to the computer which acts as a writing instrument when applied to and traced across the surface of the matrix.
Still other devices use photosensitive materials for receiving information but do not display information back from the same plane of the device after it is entered or processed by the computenFew of the graphical input-output devices of the prior art provide circuitry which can control the flow of graphical information into and out of the device which is separate and apart from the computer.
SUMMARY OF THE INVENTION The device of the present invention is a flat graphical inputoutput device for a computer using light sensors to receive information, with light emitters juxtaposed adjacent corresponding sensors to display information. A penlight, i.e., a pen or light emitting writing instrument, is held inthe hand of the operator and is used to activate the light sensors. A processor unit is used to control the flow of information into and out of the device for operation with a computer. The processor unit circuitry provides for activating, deactivating and determining the status of each emitter in accordance with either a coded or uncoded signal. The processor unit also is arranged to activate rows, columns and blocks of emitters as desired.
It is, therefore, an object of the present invention to provide a graphical input-output device for a computer.
It is another object of the present invention to provide a graphical input-output device for a computer having individual point control using a coded or uncoded address.
It is still another object of this invention to provide a graphical input-output device for a computer in which the flow of information into and out of the device is separately controlled.
It is another object of this invention to provide a graphical input-output device for a computer in which logical information is associated with the positional information in the graphical display.
It is another object of this invention to provide a graphical input-output device for a computer in which a penlight is used for graphical input.
It is another object of the present invention to provide a graphical input-output device for a computer in which photon output of the penlight is controllable for shading the graphical input and output.
It is another object of the present invention to provide a graphical input-output device for a computer in which the photon output of the graphical display is controllable for information output.
It is still another object of the present invention to provide a graphical input-output device for a computer having apparatus for performing programmed switching routines for special displays, operating commands and manipulation of graphical data.
Other and more particular objects of the present invention will be manifest upon study of the following detailed description when taken together with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an isometric view of the graphical input-output device of the present invention,
FIG. 2 is a plan and elevational view of a typical emittersensor pair,
FIG. 3 is a logic diagram of a typical point defined by a light emitter-sensor pair,
FIG. 3A is a more detailed circuit diagram of a typical point,
FIG. 4 is a symbol list defining some of the symbols used in the drawings,
FIGS. 5A and 5B is a single line block diagram of the circuitry of the present invention showing the interconnection of the various control units used to operate the device,
FIG. 6 is a circuit diagram showing the connection of primary input register, operations decoder, B. AND and C AND gates, local memory, F AND and G OR gates, and memory OR gates,
FIG. 7 is a circuit diagram of control registers SR( 0) through SR(3) of the drawingboard processor unit,
FIG. 8 is a circuit diagram of control registers SR( 4) through SR( 6) of drawingboard processor unit,
FIG. 9 is a circuit diagram of the W control gates of the drawingboard processor unit,
FIG. 10 is a circuit of the X-input, X-output and X-parts registers as connected to the drawingboard,
FIG. 11 is a circuit diagram of the Y-output register and the XY-, Z'-, and the Z-registers for transmitting the graphical information to the computer,
FIG. 12 is an elevational view of a typical penlight used to place infon'nation into and erase information from the graphical device of FIG. 1 along with details of circuitry for connecting it to the device,
FIG. 13 is a circuit diagram of the input character gates register of the drawingboard processor unit,
FIG. 14 is a circuit diagram of an instruction logic device used to measure incremental variations in the graphical disp y.
FIG. 14A is a circuit diagram of a typical timing chain device used in FIG. 14,
FIG. 14B is a circuit diagram of a device to direct X- and Y- adders to add or subtract one binary digit from the address,
FIG. 15 is a diagram of typical pulse wave forms of the timing device of FIGS. 14, 14A and 14B.
FIG. 16 is a circuit diagram of a comer of the array showing a typical point and its interface with peripheral circuitry to the board.
FIG. 17 is a circuit diagram showing the X-decoder in greater detail,
FIG. 18 is a circuit diagram showing the Y-decoder in greater detail,
FIG. 19 is a circuit diagram showing the X-encoder in greater detail,
FIG. 20 is a circuit diagram showing the Y-encoder in greater detail.
DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to FIG. 1, the graphical input-output device of the present invention comprises, basically, a write and display board 20, i.e., input-output drawingboard 20, which is mounted on an electronic and power supply cabinet 21 having a control panel 22 on the front thereof.
A penlight 23 is electronically connected to board 20 by two or more conductors 86 and 86', 24 and 25 for control of the light output of the penlight as will be described below, and for control of information placed in the board. Board 20 further comprises modular emitter-sensor circuit units or points 26 shown typically in FIGS. 2 and 3 arranged in an array 35 (FIG. 1) of horizontal and vertical rows and columns respectively.
Referring to FIG. 2, a modular emitter-sensor pair or point 26 is shown in plan and elevation and comprises a compartment in block 27 containing local circuitry, on the top surface of which is mounted a light emitter 28 and a light sensor 29 along with other light sensors further described below. Light emitters 28 may be any light emitting means such as an incandescent or neon glow lamp, however, the present device is arranged to utilize a semi-conductor device such as a light emitting diode common in the art.
Light sensor 29 is, as used in the present embodiment, a semi-conductor device sensitive to electromagnetic radiation.
To protect emitter 28 and sensor 29 from damage, a transparent surface 30 is disposed over the entire surface of array 35.
FIG. 3 illustrates a simplified logic diagram for a typical point i.e., emitter-sensor pair circuit 26. Such a point" 26 comprises an X-sense diode 31 connected on its anode side to X-conductor 32 and a Y-sense diode 33 connected on its anode side to Y-conductor 34. The cathode sides of X- and Y- sensediodes 31 and 32 are connected in common to the output of AND gate 36 and the output of light sensor 29 through pointing circuit 50.
Light emitting diode 28 and one of the inputs to AND gate 36 are connected to the output of memory circuit 37. The other input of AND gate 36 is connected to READ conductor 38 while the two inputs to memory circuit 37 are connected to WRITE conductor 39 and ERASE conductor 40.
With reference to FIG. 3A, a more detailed circuit diagram of a typical point 26 is shown.
The reference numerals of corresponding parts of the circuit of FIG. 3 and 3A are identical.
The identification of each circuit .element and its value, where applicable, is listed in Table 1. The number-letter combination under Typeis the present industrial standard designation for the semi-conductor device used.
Table 2 is a listing of the values for resistors 172 and 173 necessary to change the state of the bi-stable circuit of FIG. 3A. The sensitivity range is generally descriptive. The measured values would range from about 100 foot-candles for an intenselight to about 0.5 foot-candles for shadow light.
TABLE 1 Ref. No. Type or Value Purpose 160 2N22 19 Computer write transistor 161 2N22l9 Computer erase transistor 162 IN 2175 Optical write transistor 163 1N2175 Optical erase transistor 164 2N3l35 Bi-stable pnp transistor (for memory) 165 2N22l9 Bi-stable npn transistor (for memory) 166 2N22l9 Driver transistor 29 1N2 175 Optical pointing transistor 167 2N4409 Inverting driver transistor 28 MVEIOO Light emitting diode 169 1N643 Bias diode 170 1N643 Bias diode 171 1N56AG Isolating diode 33 1N56AG Y-sense diode 31 1N56AG X-sense diode 172 K Enable sensitivity resistor 173 10 K Disable sensitivity resistor 174 100 ohms Light emitting diode (LED) current limiting resistor 175 10 K Transistor 166 current limiting resistor 176 10 K Bias resistor 177 1 K Transistor 167 current limiting resistor 36 SN7402 NOR gate Table 2 Value of Resistors Light Level l72'and 173 l K Intense 10 K Room lamp 100 K Dim 1 Meg Shadow From FIG. 3A," WRITE conductor 39 enters circuit 26 through transistor 160 while ERASE conductor 40 enters the circuit through transistor 161 for computer control of the WRITE-ERASE function. The same function can be performed using penlight 23 by activating light sensor 162 to write or light sensor 163 to erase.
Memory is achieved through bi-stable transistors 164 and 165 which lock in the on or ofi' status ofthe point, i.e., whether or not a current is flowing through light emitting diode 28.
To activate the point, penlight 23 is pointed at light sensing transistor 162 and light sources 88 (FIG. 12) are energized to shine on sensor 162 causing a current to flow through the transistor, applying a voltage to one side of light emitting diode 28 causing a current to flow therethrough.
To deactivate the point, penlight 23 is pointed at light sensing transistor 163 and light sources 88 are energized to shine on sensor 163 reducing its resistance to a value sufficient to lower the voltage across light emitting diode-28 to limit the current therethrough sufiicient to turn diode 28 off.
For consistency and understanding of thedrawings, FIG. 4 defines the symbols used in the drawings.
OR gate 41 of FIG. 4 is a semi-conductor device having two or more inputs and one output. A signal, i.e., a voltage pulse, on either of the inputs on the left will appear on the output (right) side of the device. AND gate 42 of FIG. 4 is a semiconductor device having two inputs, both of which must be activated, i.e., have a voltage on the input conductors, for a signal to appear on the output side.
Dtype flip-flop 43 is a bi-stable semi-conductor device having a signal input 44 and a clock" input 45, a reset input 46 and two logical complimentary out-put conductors 47 and 48.
Activation of clock input 45 will permit a signal on input 44 to pass to output conductors 47 and 48.
Activation of reset input 46 causes all flip-flops 43 to return to a logical zero or ofi"position.
Inverting amplifier 49 is a device common in the art for producing the logical compliment of a digital signal.
With respect to the entire system, FIGS. 5A and 58, shown on two sheets, is a single line block diagram showing theinterconnection of the basic electronic switching units which serve to control the How of information into drawingboard 20 and also to and from the computer (not shown )through drawingboard 20 for the manipulation of the data contained therein.
The computer that is used in conjunction with the device of the present invention can be any digital computer common in the art which can receive, manipulate and transmit informationcoded in a manner to identify individual bits of information, for example, in the form of voltage pulses on various combinations of conductors or lines leading into and out of the present device.
The blocks in FIGS. 5A and SBrepresent switching circuits which comprise basically combinations of ANDand ORgates and flip-flop devices with the exception of local memory 106 which may be any type of device common in the art which can temporarily store information. A magnetic core memory common in the art would be one example.
With particular reference to FIG. 5A, there is illustrated the circuits associated with drawingboard 20 used to place information into the board and read information stored in the board.
Basically, drawingboard 20 comprises a 16 by l6 array 35 of points" 26 having sixteen X-conductors 32 (FIG. 3 and 3A) arranged parallel and equally spaced in a common plane with sixteen Y-conductors 34 arranged parallel and equally spaced normal to X-conductors 32 in said common plane.
A point26 is connected at the intersection of each X- and Y-conductor 32 and 34, respectively.
Array 35, therefore, comprises 256 "points" 26 arranged in 16 horizontal and 16 vertical rows and columns, with each point" 26 comprising the elements of the circuit of FIG. 3A. FIG. 16 shows array 35 comprising read, write and erase gate registers 154, and 156, respectively, whose outputs are connected to conductors 38, 39 and 40 through read, write and erase point AND gates 157, 158, and 159, respectively.
Thus activation of any of the conductors 38, 39 M40 will cause data in array 35 to be, respectively, read written, or erased by the computer (not shown) from array 35.
It will be noted that through the use of penlight 23, as previously discussed and shown in FIG. 3A, an individual point" 26, may be read, written or erased by appropriate photoactivation of transistors 29, 162 or 163, respectively.
To the left and bottom of array 35 (FIG. 5A) are input sides 53Y and 53X. To the right and top of array 35 are the output sides 54Y and 54X.
The input circuitry for the device of the present invention comprises, for the X-sense (x-coordinate), X-input register 56 whose output is connected to X-input side 53X, X-input parts register 57 whose output is connected to the input side of X-input register 56 and whose various inputs are connected to drawingboard processor unit 100 (FIG. 5B).
The output of X-address decoder 58 is connected to the input of X-input parts register 57 while the input side of X-address decoder 58 is connected through XCD gates 115 to drawing board processor unit 100 (FIG. 5B).
In a like manner for the Y-sense (Y-coordinate), the output side of Y-input register 60 is connected to input side 53Y of array 35 while the input side of register 60 is connected to the output side of Y-input parts register 61. The output of Y-address decoder 62 is connected to the input side of Y-input parts register 61 while the inputs of both Y-address decoder 62 (through YDC gates 120) and Y-input parts register 61 are connected to drawingboard proccessor unit 100.
The output circuitry for the device of the present invention comprises, for the X-sense (X-coordinate), X-output register 64 whose input is connected to X-output side 54X, X-output parts register 65 whose input is connected to the output of X- output register 64.
It will be noted that the output of X-output register 64 is also connected to the input of X-address encoder 66 whose output is connected both to multiple input OR gate XOOR 150 and XEC gates register 81 (FIG. 17).
In a like manner, for the Y-sense (Y-coordinate), the input side of Y-output register 68 is connected to Y-output side 54Y, while its output side is connected to the input side of Y- output pans register 69.
It will also be noted that the output of Y-output register 68 is connected to the input of Y-address encoder 70 whose output is connected both to multiple input OR gate YOOR 151 and YEC gates register 124 (FIG. 18).
Both X- and Y-output parts registers 65 and 69 are connected to drawingboard output register 73 whose output is connected to the computer (not shown).
All registers, it will be noted, are connected to drawingboard processor unit 100.
DRAWINGBOARD PROCESSOR UNIT FIG. 5B shows the interconnection of the various block circuits contained in the drawingboard processor unit 100.
Basically, drawing board processor unit 100 comprises a primary input register 101, whose outputis variously connected to operations decoder 102, C AND gates register 103, B ANDgates register 104 and instruction logic circuit 152.
Operations decoder 102 is variously connected to local memory 106, F AND gates register 107, address code status register SR() 108, input part status register 812(1) 109, output parts status register SR(2)110, read status status register SR(3)111, labels" status register SR(4) 112, location storagestatus register SR()113, and memory bufferstatus register SR(6) 114 and instruction logic circuit 152.
Drawingboard processor unit 100 further comprises, input character gates register 116, W gates register 117, 6" OR gates register 118, and memory OR gates register MOR 1 19.
To describe the device of the present invention in detail, certain conventions will be used to organize the material. The letters Athrough Z are used to identify the lines or circuitsinterconnecting the various circuit units or blocks. For example, line A( 1) designates line "1 of circuit "A," X(07)designateslines 0 (zero)through "7 of circuit X.
Certain abbreviations may be used which will be self evident such as XII for X-inputs parts register; YOP" for Y-output parts register and SR for status register.
Since certain commands are required for various control functions, these are designated by the command number contained in a circle when shown on the drawings and preceded by an asterisk when discussed in the specification. For example, a command identified by 03" in a circle on a drawing is identified as *03" in the specification.
The arrows which are incorporated into the circuit lines represent the flow of information or data through drawingboard 20 and processor unit in accordance with the direction of the arrow.
As for detailed discussion of the circuit units of the present invention, it is apparent to one skilled in the art that the use of AND gates, OR gates and flip-flop devices in switching circuits is common in the art and the function of each individual circuit element can be followed by such person without further detailed explanation.
To describe in detail the individual circuit units of drawingboard processor unit 100, reference is made to FIG. 6 and beginning in particular to primary input register 101.
Primary input register 101 comprises a plurality, sixteen in the present embodiment, of flip-flop circuit units 121 having outputs A(0) through A( 15). The input signal enters register 101 in a manner such that the fust five bits," A(0) through A(4) of information are an encoded command signal; the next three bits, A(5), A(6), and A(7) are an encoded instructional signal also identified as lines [(0), I( 1) and K2), respectively; and the remaining eight bits are an encoded X-Y address signal for a particular point" 26, four bitsfor the X-address and four bits for the Y-address.
Operations decoder 102 comprises a set of input OR gates 122, a decoder unit common in the art which converts the on or ofFstatus of either lines A(0-4) or E(0-4) to a pulse or signal on any one of 00 to 37 (octal) outputs on 32 lines (decimal).
Command lines *01 through *37 are connected to the registers for control of array 35 The detailed operation of each command is described supra. I
B AND gates register 104 is used to bypass coded adderess information around local memory 106 while C AND gates register 103 is used to place coded address information into local memory 106.
The output of lines A(7) (also identified as line I(2)) and A'(7) of the instructional coded section of primary input register 101 are used to gate the flow of information through C and B"gates registers 103 and 104 respectively. The signal on line A'(7) is the logical compliment of the signal on line A(7 Local memory 106 can be any memory unit common in the art for storing bits" of information such as a magnetic core matrix and the like common in the art.
Local memory OR gates register MOR 119 comprises eight OR gates which control the flow of information from memory 106, instruction logic circuit 152 and B AND gates register 104into lines X'(0-3) and Y'(0-3).
F AND gates register 107 comprises all AND gates 134 and G OR gates register 118 comprising all OR gates 135 are used to control the flow of information into memory buffer" status register SR(6) 1 14 (FIG. 5B).
With reference to FIGS. 7 and 8, there is shown the detailed circuit diagram for status registers SR(0) through SR(6) reference numerals 108 through 1 14, respectively.
Basically, each status register comprises a column of bi-stable flip-flop devices and a column of AND gates 126.
Typically, two command lines 127 and 128 are connected to flip-flop devices 125. Line 127 is connected in common to the clock input terminals of each flip-flop device 125 for the purpose of transferring the status of the signal input lines into the register, and the other command line 128 is connected in common to the reset input of flip-flop devices 125 to reset all flip-flop devices to a logical zero orofl" status.
It will be noted that AND gates 126 are used to gate information out of thestatus registers upon appropriate activation of lines RSW(-7) of status register SR(3) 1 11.
Status registers SR(0-6), reference numerals 108 through 1 14, are identified as shown in Table 3 as follows:
3 memory bufier" codes With reference to FIG. 13, there is shown the detailed circuit diagram for character gates register 116 which comprises 32 AND gates 130.
Register 116 converts the coded address of a typical point26.. on lines X'(0-3) and Y(03) to activation of lines X(0-15) and Y(015) by appropriate activation of lines XIC(O-l and YIC(0-l For example, concurrent activation of lines Y(2) and XIC( 1) will causeline X(l4) to be activated.
FIG. 9 illustrates a detailed circuit diagram of W gates register-117 which coi'nprises eight lower OR gates 132 and eight upper OR gates 133. The lower OR gates 132 have input and output lines as tabulated in Table 4. The upper OR gates 133 have input and output lines as tabulated in Table 5.
TABLE4 Output Input Lines Lines W), W), 0( m) m) U). H). (1). 0), 0( U) U) L( 0), 0), G), 0( 0) M 0). C), H 0( H H). M); 0( 6), W 0(5), U (6). H6), 0(6). R( 0 0( (7)' TABLES Output input Lines Lines U- 11(8), 0) O). 0 0 0 U W U W 0 0 0), 0 (6) 0 (l5). R(
DRAWINGBOARD With reference now to FIGS. and 11, FIG. 10 is a logic diagram of the input andoutput register circuits for drawingboard 20. The input and output register circuits in the Y- direction are identical to those in the X-direction and, therefore, are not repeated in the drawing. Discussion of the X- input and output circuitry applies as well to the Y-input and output circuitry. FIG. 11 is a circuit diagram of drawing board 8 output register 73 as well asa circuit diagram of Y-output register 68 and Y-output parts register 69.
Referring-to FIG. 10, X-input parts gate register 57 comprises a set of sixteen X-parts ANDgates 75 and a set of six- 1 teen X-parts OR gates 76.
One side of the input to AND gates 75 is connected consecutively in groups of four, to lines X'(O-3). The other side of the input to AND gates75 is connected in common, in groups of four, to lines XIP(0-3). It can be seen, using this arrangement, that by selective activation of lines X'(0-3) and XIP(0-3), only one line or a combination of lines X(0-'l5) can be activated. Thus, combined with the Y-direction, one point or combination of points will be activated.
Input register 56 comprises sixteen bi-stable flip-flop devices 77 which act to control the flow of the information on the output lines 78 of input parts register 57 into array 35.
Command lines *01 and *02 for the X- and Y-coordinates are used to control the flow of such information. Command lines *10 and *11 (FIG. 5A)are used to reset X-input register 56 and Y-input register 60,.respectively, to a logical zero of ofi'"status.
X-output register 64, similar to X-input register 56 comprises sixteen bi-stable flip-flop devices 79 which act to control the flow of information out of array 35.
Line ROR to X- and Y-output registers 64 and 68 from OR gate 145 (FIG. 12) is used to control the flow of output information. Command lines *13 and *14 (FIG. 5A) are used to reset X-output register 64 and Y-output register 68, respectively, to a logical zero or off" status.
X-output pans gate register 65 comprises all AND gates 80. It will be noted that one side of the input to AND gates 80 is connected in common, in groups of four, to lines XOP(0-3). Thus by appropriate activation of lines XOP(03), information is gated out of X-output register 64 into drawingboard output register 73 (FIG. 1 1
Referring to FIG. 1 l, drawingboard output register 73 comprises XY OR gates register 82, Z-OR gates register 83 and Z- output register 84 which is connected to Y-output parts gate register 69 and X-output parts gate register 65 at the input side of XY OR gate register 82.
. Z-output register 84 comprises sixteen bi-stable flip-flop devices 85 used to transfer information from its input side to the computer (not shown). Command line *06 is used to con.- trol the flow of the information to the computer while command line *15 is used to reset all the bits of output register 84 to a logical zero or ofi state.
With reference to FIG. 5A and in particular to X-address decoder 58, Y-address decoder 62, X-address encoder 66 and Y-address encoder 70, the circuitry for these devices is common in the art and comprises AND gates Y DC 120, XDC 1 I5, YEC 124 and XEC 81 and inverting amplifiers such that the "on and off status combination of four input lines intoaddress decoders 58 and 62 causes activation of only one of 16 output lines of the decoder, and for encoder 66 or 70, activation on one of 16 input lines causes a particular combination of on-off states of four output lines of the encoder.
Typically in FIG. 19 is shown X-address decoder 58 connected to XDC gates register 115. XDC gates register comprises four AND gates 59 whose outputs are connected to X-address decoder 58.
One input side of AND gates 59 is connected individually to line X(0-3) while the other side is connected in common to line XDC from status register SR(0) 108.
In a similar manner, FIG. 20 shows Y-address decoder 62 connected to YDC gates register 120. YDC gates register also comprises four ANDgates 63 whose outputs are connected to Y-address decoder 62. A
One input side of ANDgates 63 is connected individually to lines Y'(0-3) while the other side is connected in common to line YDC from status register SR(0)108.
Typically, in FIG. 17 is shown X-address encoder 66 with output connected to multiple input OR gate XQOR and AND gates register XEC 81 comprising all AND gates 67.It