|Publication number||US3675003 A|
|Publication date||Jul 4, 1972|
|Filing date||Aug 27, 1970|
|Priority date||Aug 27, 1970|
|Also published as||CA923622A1, DE2140771A1|
|Publication number||US 3675003 A, US 3675003A, US-A-3675003, US3675003 A, US3675003A|
|Inventors||Snyder John Somerville|
|Original Assignee||Sybron Corp|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Referenced by (4), Classifications (7), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
O United States Patent [1 1 Snyder 1 July 4, 1972 54] SYSTEMS INVOLVING DIVISION 3,502,983 3/1970 lngle et a1. ..328/161 x 3,541,320 11/1970 Beall ..328/127 X  Inventor. John Somerv|l1e Snyder, Webster, NY. 3,473,043 10/1969 James I I I I I "32861 x  Assignee: Sybron Corporation, Rochester, NY. 3,538,320 11/1970 181180115 3,517,179 6/1970 Herndon... .....235/196 [221 Flled: lg-27,1970 3,514,700 5/1970 Kalin et 31.... .328/161 x 21 APPL 7 435 3,492,471 1/1970 Crowell.... .....235/196 X 3,525,860 8/1970 Barber ..235/195  US. Cl ..235/196, 307/251, 328/161, P i Examiner Eugene (113 11 235/151-3 Assistant Examiner-Jerry Smith [51 Int. Cl. ..G06g 7/16 Att0meyThc0d0re B. Roessel  Field of Search ..235/151.3, 183-184,
235/196, 150.51, 150.52, 195; 307/228-230, 251;  ABSTRACT 3 8/127 16L 330/69 :79:98? A system wherein division by zero is avoided. A numerator voltage is applied to a high gain amplifier having a negative feedback loo controlled b a denominator volta e which if 56 P Y 8 I Reierences Cited zero disables part of the feedback loop. The effect of this is TE STATES TE TS avoided by, in effect, replacing this part of the loop in response to the denominator becoming zero. 3,550,022 12/1970 Yareck ..328/161 3,566,092 2/1971 Grant et a1 ..235/196 X 7 Claims, 2 Drawing Figures NUMERATOR PATENTEDJUL 4 I972 3.675.003
22 SAWTOOTH I 2 2o DENOMINATOR Q 3 33 1Q REFERENCE NUMERATOR &
1 QUOTIENT SUB sue SUB ZONES ZONES ZONES I Q l 4 O2 WEB I 3 MOISTURE GAUGE ZONES I i t l WEB MOTION TRAVERSING EFFECTIVE GAUGE PATH MECHANISM CONTROL SAWTOOTH INTEGRATOR I7 F|G 2 mvsmon.
JOHN s. SNYDER BY%WI ATTORNEY SYSTEMS INVOLVING DIVISION BACKGROUND OF THE INVENTION 1. The field of the invention is in the art of computing instruments the functioning of which involves performing the operation of division, i.e., dividing a denominator into a numerator to obtain a quotient. Frequently, the numerator and denominator represent physical variables such as pressure, temperature, characteristics of materials, time, or the like, which may for one reason or another become zero. In particular, averaging a variable over time may involve division, and, where the averaging is performed piece-wise for a series of intervals, dividing by zero may be involved at the beginning of each interval.
. 2. Description of the Prior Art: In some forms of prior art computing instruments, the means providing the dividing operation includes a high-gain amplifier'for amplifying a numerator voltage, and there is a negative feedback loop around the amplifier which makes the amplifier output reflect the numerator voltage. The loop is controlled ultimately by a denominator voltage to make the feedback proportional to denominator voltage. As a result the amplifiers output voltage represents the numerator voltage divided by the denominator. When the denominator voltage is sufficiently small, it in effect makes the feedback zero, and as a result, the amplifier output can no longer correspond to its input. Summary: A computing instrument according to the present invention, is generally of the above-described type but, unlike the prior art, that part of the feedback loop controlled by the denominator voltage is in effect replacedby an element that maintains feedback in response to the denominator becoming zero or sufficiently small. The invention finds particular use in systems for averaging the moisture content over the width of a moving web of paper. In brief, a suitable moisture content measuring instrument scans across the paper, transversely of the direction of its motion. The average moisture content of a fraction of the width is obtained by integrating moisture content across the width of the fraction. This average is divided by the time which elapsed while moisture content was being measured in this fraction, and the resulting quotient here is the average moisture content of a strip of web, the width of which is proportional to the time of measurement, This process is repcated for the next fraction of web width, and then'for the next and the next, and so on. Consequently, there results a set of moisture content averages for a series of strips of web. However, each time averaging is begun in a strip, elapsed time is zero, so the division of the moisture content integrals by time is provided for in accordance with the present invention.
In particular, the elapsed time is determined by means of a capacity-type integrator, the capacity of which is discharged at the beginning of each strip, so for a brief interval corresponding to the beginning of a strip, feedback is maintained by the aforesaid element.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1. represents a dividing system according to the invention;
FIG. 2 represents an averaging system according to the invention.
In FIG. 1, numerator voltage e, and denominator voltage e are connected to non-inverting input terminals l and 2, respectively, of high gain difl'erential amplifiers l and 20 respectively. A feedback voltage 2 and a sawtooth voltage e are connected to the inverting terminals 11 and 22, respectively, of amplifiers l0 and 20. It will be observed that the connections specified here contemplate that all four voltages are negative in polarity.
Feedback voltage e is derived from the output voltage e at output terminal 4 of amplifier 10, via a negative feedback loop consisting essentially of capacitor 5 in parallel with the resistance between terminals 4 and 11, made up of resistors 6 and 7, and FETs 8, 9 and l2.
The gate electrodes of FETs (field effect transistors) 8, 9 and 12 are connected to output terminals 13, 14 and 15, respectively, of amplifiers 30, 20 and 40. FETs'9 and 12 are connected together, source to drain, with the drain of PET 9 being connected to circuit common CC, and the source of PET 12 being connected to output terminal 4. One end of each of resistors 6 and 7 is connected to the drain electrode of PET 8, the other end of resistor 6 is connected to output terminal 11, the other end of resistor 7 is connected to the source-drain connection of FETs 9 and l2,and the source electrode of PET 8 is connected to output terminal 4.
Amplifier 30 is a high gain differential amplifier having noninverting input terminal 3 and inverting input terminal 33, the former being connected to input terminal 2, and the latter being connected to a source of reference voltage.
Amplifier 40 is a unitary gain, inverting amplifier, the input terminal of which is the same as the output terminal 14 of amplifier 20.
The sources of the several input voltages are shown as boxes labeled SAWTOOTI-l, DENOMINATOR, REFERENCE and NUMERATOR. The output voltage e,, at terminal 4 is applied to some utilization apparatus (shown as a box labeled QUO- TIENT and connected to terminal 4) which may be suitable control, indicating, or like apparatus, the exact nature of which is not relevant here.
The purpose of SAWTOOTH, amplifiers 20 and 40, and FETs 9 and I2 is to make feedback voltage e correspond to the denominator voltage e For this purpose e is to be supposed to be a ramp" beginning at zero, its magnitude increasing linearly to a given magnitude equal to or greater than the highest magnitude that e can be expected to take on, and repeating at a given rate that is much greater than any rate at which e can be expected to vary its magnitude. Voltage 2 may on the other hand, be the output of some measuring device which senses a condition such as temperature, characteristics of materials, or the like, and causes the voltage e to have some predetemiined quantitative relationship to said condition. The voltage e may be of substantially the same character as voltage e Since amplifier 20 is a high gain differential amplifier, its response to e and e is to produce an output voltage e terminal 14, the sign of which depends on which of voltages e and e is larger. If at a given instant e, is larger than e then e will be positive, whereas if e is the larger voltage, then e will be negative. Further, the output voltage e of amplifier 40 will always be opposite in sign too, but of the same order of magnitude as voltage e The amplifier 20 is designed so that the voltages e and 6 always have magnitudes greater than the cutoff voltages of FETs 9 and 12. Because of this, and since e and e are always opposite in sign, one of the FETs will be on and the other off, at all times, though which is on and which is off will depend on which of e and e is the larger in magnitude.
When F ET 12 is on, there will be a feedback loop consisting of capacitor 5 in parallel with the series resistances of resistor 6, resistor 7 and the drain/source resistance of PET 12. When FET 12 is off, then input terminal 11 is grounded to circuit common via the series resistance of resistor 6, resistor 7, and the drain/source resistance of FET 9.
Supposing e to have a value greater than zero but less than the maximum value attained by the ramp, then the instant at which ramp voltage becomes just slightly greater than e corresponds to the magnitude of e Therefore, during any given ramp, the amount of time FET 12 is on is proportional to the magnitude of e Further, the overall gain of amplifier 10 is proportional to the reciprocal of that amount of time. Accordingly, e at terminal 4 is proportional to e,/e
The foregoing operation is known in the prior art, but it is also known in the prior art that such operation will not admit of e becoming zero, or indeed of decreasing to some minimum value not zero. The reason for this is that when e is trol of e At this point, since FET 9 is on, amplifier 10 and capacitor act as an integrator, and cause voltage c to reflect only the peculiarities of amplifier 10, such as its off set voltage, bias current, and so on, as will be recognized by those skilled in the art. While the time constant of discharge of capacitor C is fixed by choosing value of capacitor 5, and re.
sisters 6 and 7 such that capacitor 5 cannot discharge enough during any given ramp to matter, e varies slowly enough in comparison to the sawtooth voltage at e that if 2 becomes zero or nearly zero, it will likely remain so long enough to discharge capacitor 5 to the point where there is, in effect, no feedback at terminal 11, at which point amplifier will saturate.
The above-described effect of e becoming zero or too nearly zero is prevented by amplifier 30 and FET 8. During normal operation, i.e., e not equal to zero, or different therefrom by at least a predetermined amount, amplifier 30 is producing e with such magnitude and sign that FET 8 is cut- 05, in which condition its drain/source resistance is for practical purposes infinite, and therefore does not affect the operation of amplifier 10. As shown, a reference-voltage source (shown as a box labeled REFERENCE and connected to input terminal 33) provides a fixed reference voltage 12 which is set to just such value that when e is zero, or such non-zero minimum value such as will have the effect of zero, e will switch FET 8 on. Accordingly, when e becomes just slightly larger than e then e will change sign and switch FET 8 off. When FET 8 is on, there is feedback to terminal 11 via capacitor 5 in parallel with the series resistance of resistor 6 and the drain/source resistance of FET 8. While terminal 11 can still connect to circuit common via FET 9, resistor 7 is chosen to have such value in relation to the drain/source resistance of FET 8 that there is sufficient feedback voltage, at such times as FET 9 is on, at the connection between resistor 7 and the drain electrode of F ET 8 to control the output of amplifier 10, making e some convenient, predetermined fixed multiple e In particular, it is convenient to choose R to be sufficiently large that e is substantially equal to e,. at this time. Additionally, resistor 7 limits current drain to acceptable levels whenever FETs 8 and 9 are both on.
Various modifications in the system of FIG. 1 will be evident to those skilled in the art. For example, various reversals in the polarities indicated previously, or implied by the illustrated nature of the components, could be adopted. Thus, e and 2 could be positive voltages. In this case, terminals 2 and 22 would have to be the amplifiers inverting and non-inverting input terminals, or FETs 9 and 12 would have to be P- type, instead of N-type as shown.
Again, FET 12 could be replaced by a P-type FET in which case the amplifier 40 could be eliminated since the gate of the replacement could be connected directly to terminal 14.
The role of F ET's is to be essentially on-off switches having on-resistance negligibly small in comparison to the resistors 6 and 7, but havingoff-resistances large enough to be effectively open-circuits when gated ofi. In FIG. 1, drain and source electrodes are distinguishable, but this is not essential, especially since FETs are available in which drain and source are interchangeable.
In FIG. 2, MOISTURE GAUGE is moved by TRAVERSING MECHANISM moving at right angles to the web and the direction of WEB MOTION. The gauge is therefore moving in a zigzag effective path along which the moisture content is measured. Supposing web and gauge to move at constant rates, then it will be evident that theweb may be viewed as being divided up into longitudinal ZONES a, b, c and d, each .of which is divided up into SUBZONES, e.g., subzones a,, a a a and so on, of zone a, each of which subzone corresponds to a single determination of average moisture content. While zoning and subzoning depend in part on considerations such as intended use, interpretation, etc., of
the averages, they also may depend on the nature of the averaging process, as will be explained later on below.
Supposing the web to be moving and the moisture gauge to be traversing and measuring the web moisture, averages are determined, and zones and subzones are defined by means of what is essentially the divider system of FIG. 1, plus certain modifications. In order to avoid repetition, only so much of the FIG. 1 system is shown in FIG. 2, as is necessary to show the aforesaid modifications and the use of the FIG. 1 system in web moisture measurement. Insofar as FIG. 2 reproduces parts of FIG. 1, these parts are identified by the same reference numerals as in FIG. 1.
The moisture gauge is shown as connected to a box labeled INTEGRATOR replacing the box NUMERATOR of FIG. 1, and the DENOMINATOR box of FIG. 1 has been similarly replaced. The integrating function of the integrators is represented by capacitors l6 and 18, having FETs 17 and 19 connected across them. The voltages at terminals 1 and 2 in thisarrangement, represent the voltages, with respect to circuit common, to which the capacitors l6 and 18 charge.
The integrator having capacitor 16 is connected to the moisture gauge to integrate a voltage from the gauge, which voltage represents the moisture content of the web as seen by the gauge. Accordingly, the voltage at terminal 1 represents the time integral of the moisture gauge output voltage.
The integrator having capacitor 18 is connected to a fixed DC voltage source, shown as cell 23, to integrate the voltage of cell 23. Accordingly, thevoltage at terminal 2 is the time integral of the voltage of cell 23. As the voltage of the cell is fixed, its time integral simply represents elapsed time, or, ultimately, length of path of the moisture gauge with respect to the web.
It is evident that the quotient at terminal 4 represents an average value of moisture content in the paper web. However, the integrators cannot integrate indefinitely, due to the pro-' perties and practical parameters of real integrators. Therefore, periodically the capacitors must be discharged. This is provided for by CONTROL which, for example, is connected to the traversing mechanism to determine suitable instants during the travel of the moisture gauge, at which to discharge the capacitors. In this case, CONTROL emits a tum-on voltage pulse to FETs l7 and 19 at substantially the instant one subzone has been traversed by the gauge. This pulse lasts just long enough to discharge the capacitors 16 and 18 to the potentialof circuit common. After this pulse disappears, the FETs l7 and 19 revert to their off-resistances, and the integrators begin to integrate again.
When the capacitors discharge, the voltages at terminals 1 and 2 become zero or very small, so simultaneously with the capacitor discharging pulse, CONTROL emits a pulse which is applied to the gate of FET 8 via a terminal 130, for turning on FET 8. In FIG. 2, therefore, CONTROL and terminal correspond to amplifier 30 and terminal 13 of FIG. 1, and perform the same function with respect to FET 8.
The difference between the two Figures is ultimately how denominator voltage gets to be zero or sufiiciently nearly so. Thus, in FIG. 1, the occurrence of zero denominator voltage, however caused, is detected. In FIG. 2, zero denominator voltage is an incident of the averaging operation. As in practice, in FIG. 2, zero denominator voltage is not expected to occur except by reason of discharging capacitor 18, it is more convenient to have CONTROL provide for turning FET 8 on, than to provide distinct zero detecting means such as amplifier 30.
Preferably, the firing pulse on terminal 130 occurs slightly before the firing pulse for FETs 17 and 19, and expires a little while after them. The reason for this is that the time integrator is essentially a ramp generator which is supposed to produce a voltage beginning at zero, increasing from there at. a constant rate to a given value, and becoming instantaneously zero again upon achieving that given value. Actually, capacitor 18 does not discharge instantaneously to zero, and there is some uncertainty about the point at which the voltage on capacitor 18 thereafter begins to follow the desired ramp configuration. In effect, therefore, there is an interval overlapping the end of one ramp and the beginning of thenext ramp, in which the voltage at terminal 2 may get to zero, but otherwise deviates from the ideal. In the present invention, PE! 8 is on during this interval (which is marked at terminal 4, so to speak, by e having the predetermined value determined by resistor 7, namely, substantially the value of e,, which will be zero at some point in said interval) so no division occurs except when the voltage e has the desired ramp configuration. The importance of this is that to the extent that e deviates from the ideal, to corresponding extent there will be an error in the measure of elapsed time.
The successive ramps produced by the integrator including capacitor 18 form in effect a sawtooth voltage at the frequency of discharging the capacitors 16 and 18, and this frequency must be small in comparison to the sawtooth frequency at terminal 22, analogous to the restriction placed on variation in the denominator voltage in FIG. 1.
As is evident from the foregoing, the zoning of the web is basically due to the limited capacity of the integrators. For example, there are limits on the magnitudes of voltages involved in the operation of the practical instrumentalities making up the moisture gauge, integrators, and so on, so the maximum voltage that can be placed on capacitors l6 and 18 will be something less then one or another of those limits. However, the zoning is actually an advantage, because the output voltage wave form at terminal 4 is correlated with both the zones and the subzones. Accordingly, by examining the wave form at terminal 4, a wet spot on the web will be detected and can be localized to the zone or subzone in which it occurred. Also, if the use of the averages is to determine the overall moisture content of a large quantity of web, wet spot effect can be filtered out since the normal moisture content will be a few percent by weight of the paper in a normal subzone, whereas a wet spot in a subzone will produce a short peak, which will be all the more pronounced, the smaller the subzone.
The entities referred to as TRAVERSING MECHANISM, MOISTURE GAUGE, SAWTOOTH and INTEGRATOR are individually well-known in the art, so their particulars have not been described herein. As for CONTROL, it may be any sort of device which emits the appropriate control signals, e.g., pulses, at appropriate points along the moisture gauges travel. Given the program of operation described herein for CON- TROL, one skilled in the art, will be able to devise to specific forms thereof routinely, without exercising invention.
Having set forth my invention as commanded in Title 35 of the United States Code, I claim:
1. In a system involving division, wherein said system has an amplifier having high gain before feedback and a negative feedback loop interconnecting said amplifiers input and output for causing said amplifier to produce a first signal at its said output substantially in proportion to a second signal applied to its said input, said feedback loop having an element therein variable in response to a third signal applied thereto for causing said amplifier to produce said first signal in proportion to the magnitude of said second signal divided by the magnitude of said third signal,
and wherein said feedback loop has the property of providing no feedback as a result of variation of said feedback element in response to said third signal having substantially zero magnitude, and wherein said system has signal producing means connected to said feedback element for applying said third signal to said feedback element, and
said signal producing means has the property of, on occasion, providing said third signal at substantially zero magnitude,
the improvement comprising a second feedback element connected between said output and input of said amplifier independently of said first feedback element, said second feedback element being actuable between first and second states, said first state being one in which said second feedback element is ineffective to provide feedback of said output to said input, and said second state being one in which said second feedback element is effective to provide DC feedback of output to input said second feedback element being normally in sard first state; and
control means operative when the magnitude of said third signal is substantially zero to actuate said second feedback element to said second state.
2. The invention of claim 1, wherein said control means is responsive to said third signals magnitude becoming substantially zero, for actuating said second feedback element to said second state.
3. The invention of claim 1, wherein said control means is operative to periodically efiectively cause said third signals magnitude to become substantially zero, and, substantially simultaneously, to actuate said second feedback element to said second state.
4. The invention of claim 3, wherein said signal producing means includes a ramp generator for producing a ramp signal, and a sawtooth generator for producing a sawtooth signal, said ramp signal being said third signal, and said first feedback element being jointly controlled by said ramp signal and said sawtooth signal to such affect as to be substantially ineffective to provide feedback whenever said ramp signal is substantially zero.
5. The invention of claim 4, wherein said control means actuat'es said second feedback element to said second state for a time interval beginning before said ramp signal decreases to substantially zero and ending after said ramp signal has next begun to increase from substantially zero.
6. The invention of claim 1, wherein said signal producing means includes an integrator having capacity for having fourth signal stored therein such that the magnitude of said third signal represents the time integral of said fourth signal, and said system includes means for removing stored fourth signal from said capacity to such extent as to make said third signal have substantially zero magnitude.
7. The invention of claim 1 wherein said element responsive to said third signal is an FET and gating means connected to the gate of said FET for causing said FET to be cut-off except when said third signals magnitude is substantially zero; said gating means being responsive to said third signals magnitude becoming substantially zero for causing said F ETs drain/source resistance to take on a value capable of providing said predetemiined amount of negative feedback, said drain/source resistance being connected across the first said feedback element, whereby to provide said second feedback element.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3473043 *||Mar 25, 1968||Oct 14, 1969||Bendix Corp||Gain adjustment network for multiplying and dividing input signals|
|US3492471 *||Oct 16, 1967||Jan 27, 1970||Honeywell Inc||Time division multiplier|
|US3502983 *||Nov 20, 1968||Mar 24, 1970||Bell Telephone Labor Inc||Signal peak-to-average ratio detector|
|US3514700 *||May 15, 1967||May 26, 1970||Sybron Corp||Voltage ratio computer|
|US3517179 *||Jun 28, 1968||Jun 23, 1970||Honeywell Inc||Arithmetic circuits for division and square root extraction with field effect transistor in feedback network of amplifier|
|US3525860 *||Dec 2, 1966||Aug 25, 1970||Barber Alfred W||Analog multiplying/dividing devices using photoconductive means|
|US3538320 *||Oct 3, 1968||Nov 3, 1970||Us Navy||Integrated circuit electronic analog divider with field effect transistor therein|
|US3541320 *||Aug 7, 1968||Nov 17, 1970||Gen Electric||Drift compensation for integrating amplifiers|
|US3550022 *||Sep 4, 1968||Dec 22, 1970||Bendix Corp||Divider circuit|
|US3566092 *||Apr 26, 1966||Feb 23, 1971||Industrial Nucleonics Corp||Averaging computer|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US3875519 *||Dec 17, 1973||Apr 1, 1975||Sybron Corp||Ratio computing circuit|
|US4485673 *||May 13, 1981||Dec 4, 1984||Drexelbrook Engineering Company||Two-wire level measuring instrument|
|US5049878 *||Apr 10, 1989||Sep 17, 1991||Drexelbrook Engineering Company||Two-wire compensated level measuring instrument|
|EP0315268A2 *||Oct 31, 1988||May 10, 1989||Philips Electronics N.V.||A divider circuit arrangement and a dual branch receiver having such a divider circuit arrangement|
|U.S. Classification||708/844, 327/362, 327/360|
|International Classification||G06G7/00, G06G7/163|
|Mar 14, 1983||AS02||Assignment of assignor's interest|
Owner name: A CORP OF OK.
Owner name: FIFE CORPORATION
Owner name: SYBRON CORPORATION
Effective date: 19820909
|Mar 14, 1983||AS||Assignment|
Owner name: FIFE CORPORATION; A CORP OF OK.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SYBRON CORPORATION;REEL/FRAME:004113/0468
Effective date: 19820909