Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS3680048 A
Publication typeGrant
Publication dateJul 25, 1972
Filing dateMar 4, 1970
Priority dateMar 8, 1969
Publication numberUS 3680048 A, US 3680048A, US-A-3680048, US3680048 A, US3680048A
InventorsEzaki Joichiro
Original AssigneeTdk Electronics Co Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Core drive and biasing system
US 3680048 A
Abstract
A read/write drive circuit for a circuit having a driver and a plurality of read/write circuit units connected in parallel thereto, wherein when one desired circuit unit is driven with a potential of one polarity, a potential of the opposite polarity is applied to other circuit units, thereby preventing a flow of current through the other circuit units and through an inadvertent ground path including stray capacitances. A higher speed operation is feasible because no charging current flows through the other circuit units that are not driven.
Images(2)
Previous page
Next page
Claims  available in
Description  (OCR text may contain errors)

United States Patent Ezaki 1 51 July 25, 1972 [s41 CORE DRIVE AND BIASING SYSTEM 3,210,741 lO/l965 Cohler et al. ..340/l66 x 3,343,l30 9/l967 Petschauer et al.. ....340/l47 X [721 P 3,473,149 10/1969 Ashley ..340/147 [73] Assignee: TDK Electronics Company Ltd., Tokyo, 3,519,995 1970 Gfi /l66 Japan 3,525,983 8/l970 Fletcher.... .....340/l66 3,451,048 6/ l 969 Strehl ..340/l74 TB 1 Mitch 4, 1970 3,1 19,025 1 /1964 Lourie el al ..340/174 TB Appl' Primary Examiner-Donald .I. Yusko Armmey-Burgess, Ryan & Wayne [30] Foreign Application Priority Data March 8, i969 Japan ..44/l7724 [57] ABSTRACT A read/write drive circuit for a circuit having a driver and a [52] U.S. Cl. ..340/l66 R, 340/174 TB plurality of read/write circuit units nne ed in parallel [51] thereto, wherein when one desired circuit unit is driven with a 58 1 Field oiSenrch ..340/1 66, 173, 174 TB Potential of one p y. a Potential of the pp P y is applied to other circuit units, thereby preventing a flow of cur- [56] Reknnm cued rent through the other circuit units and through an inadvertent ground path including stray capacitances. A higher speed UNlTED STATES PATENTS operation is feasible because no charging current flows through the other circuit units that are not driven. 3,135,948 6/1964 Ashley ..340/l66 X 3,209,339 9/1965 Blaustein et a] ..340/l66 X 4 Claims, 4 Drawing Figures DRI #M D Ll WI K s1 -r-O DR2 l L2 ewfl L3 1;,

M Dw 03 Dw4 -1 1 i041 I DWS 05 DR6 S3 L6 PATENTEDJUL 25 I972 sum 1 or 2 FIG.|

PATENTEDJULZS i872 3.680.048

sum 2 or:

CORE DRIVE AND BIASING SYSTEM BACKGROUND OF THE INVENTION The present invention relates to generally a read/write drive circuit and more particularly to a drive circuit in which a plurality of read/write drive circuits are connected in parallel to a common driver.

In the conventional core matrix driving, an electrostatic capacitance forming a ground path between a drive wire and the ground presents always a serious problem. In a drive circuit in which a plurality of drive circuit units are connected in parallel to a common driver, upon driving a desired drive wire, it is charged to a capacitance equivalent to that between the drive wire and the ground.

In this case, other drive wires are also charged. Upon completion of driving, the charge may be discharged through for example bias resistors, but since the discharge time is always large, a high speed operation is very difficult.

SUMMARY OF THE INVENTION The present invention relates to a read/write driving system having a plurality of read/write circuit units connected in parallel to a common driver, in which a desired circuit unit is driven with a potential of one polarity while to the other circuits units that are not driven are applied a potential of the opposite polarity.

One of the objects of the present invention is to attain a higher speed operation of a core matrix.

According to one embodiment of the present invention, the

collectors of a read-out drive transistor and a write switchingtransistor are connected through load resistors to a positive voltage source while the emitters of the above transistors are connected to a read-out terminal and a switch terminal respectively. In a similar manner, the emitters of a write drive transistor and a read-out switching transistor are connected through load resistors to a negative voltage source while the collectors of the above transistors are connected to a write terminal and the switch terminal respectively. The resistance of the load resistors on the side of the positive voltage source is selected to be higher than that of the load resistors on the side of the negative voltage source. Therefore, when one selected circuit unit is driven, a potential at the connections of other parallel circuit units becomes lower than the ground potential so that the one selected circuit unit that is driven is applied with a potential of one polarity while the other units, with a potential of the opposite polarity. Therefore, no current flows through the other units that are not driven and the drive wires of the other units are not charged. Each of the circuit units includes a diode so that one of said diodes is forward biased while the remainder are actively back biased by maintaining the anode voltage less than ground.

BRIEF DESCRIPTION OF THE DRAWING FIG. I is a circuit diagram of a core matrix read/write driving circuit;

FIG. 2 is an equivalent circuit of FIG. I for explanation of the operation thereof;

FIG. 3 is a circuit diagram in accordance with the present invention illustrating one drive wire and a driving section; and

FIG. 4 is an equivalent circuit of the circuit of FIG. 3 for explanation of the operation thereof.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a circuit diagram of a core matrix driving circuit consisting of two pairs of read-out drivers and write drivers and three switch matrix. The drive wires L, to L pass through memory cores (not shown) and one end of each drive wire is connected to parallel circuits each consisting of a pair of first diodes Dr, to Dr,, and second diodes Dw, to Dw respectively. The other ends of the drive wires L, and L; are connected to a switch terminal 8,; the other ends of drives wires L, and L to a switch terminal 8 and the other ends of drive wires L and L,,, to a switch terminal S The anodes of the write pulse drive diodes Dr,, Dr and Dr, are connected to a common read-out terminal R, while the anodes of the write pulse drive diodes Dr Dr, and Dr,, are connected to a common read-out terminal R The cathodes of diodes Dr,-Dr,, are connected to their respective drive wires L, to L,. In a similar manner but reversed with respect to the diode connections, the write pulse drive diodes Dw,, Dw,, and Dw are connected to a common write terminal W, while the write pulse drive diodes Dw Dw, and Dw,, are connected to a common write terminal W Reference characters C, to C,, designate the grounding capacitances of the drives wires L, to L,, respectively.

FIG. 2 shows an equivalent circuit of the circuit shown in FIG. I when the drive wire L, is used for write drive. In order to drive the read-out pulse drive diode Dr, into conduction, a positive voltage is impressed from the read-out terminal R,. In this case, both of the read-out pulse drive diodes Dn, and Dr are driven into conduction and the grounding capacitors C C,, C and C,, are also charged. Upon completion of the readout, the capacitors C;, to C are discharged through bias resistors or the like, but the discharging time interval is very long so that it is very difficult to realize high-speed driving.

In FIG. 3 illustrating a circuit diagram of one drive wire and its driving section of one embodiment of the present invention, both of a read-out drive transistor Tn, and a write-in switching transistor Tr have their collector electrodes connected to a positive voltage source +V through load resistors r, and r respectively while their emitter electrodes are connected to a read-out terminal R, and a switch terminal S, respectively. In a similar manner, the emitters of a write drive transistor Tr, and a read-out switching transistor Tr, are connected to a negative voltage source V through load resistors r and r, respectively while their collector electrodes are connected to a write terminal W, and the switch terminal S, respectively. A reference character S, designates a drive wire.

FIG. 4 is an equivalent circuit of the circuit shown in FIG. 3 when the drive wire L, is used for read-out drive. In this circuit, the load resistor r, may be approximated to a resistor R, while the load resistor r,,, to a resistor R Assume in this circuit that a voltage between the drive wire L, and the ground be E, then E V R I l E=V+R,,,I (2) where I is the current flowing through the drive wire L,'; and I This means that R,,, R,,,, is the condition for obtaining E 0.

When the potential of the drive wire L, is negative relative to the ground potential, a negative potential is applied to the terminals of the diodes Dr and Dr connected to the terminal R, as is readily seen from FIG. 2, so that neither of the diodes Dr, and Dr, are driven into conduction. Consequently, the capacitors C to C,, are not charged.

The present invention has been so far described only regarding to the case in which the drive wire L, is used for readout drive, but it will be readily understood from the foregoing that other drive wires are used for read-out and write drives in a similar manner as described above. It will be understood that the system in accordance with the present invention is not only employed for driving a core matrix but also for an ordinary transmission line.

It will be seen that in the transmission line driving system in accordance with the present invention, no charging current is flown into a circuit that is not driven so that a high-speed driving may be realized.

I claim:

l. A read and write drive circuit system for a plurality of read and write drive circuits for a core memory. saidplurality of read drive circuits including groups of diodes having their anodes connected together to respective read drive lines, said plurality of write drive circuits including groups of diodes having their cathodes connected together to respective write drive lines, voltage divider means having points connected to respective ones of said read and write drive lines, and selection means for. selectively forward biasing one diode of one of said groups of diodes and reversely biasing the remainder of the diodes of the group, at least one of the divider points being maintained at a voltage level less than ground when a corresponding read line is energized and being maintained at a voltage level greater than ground when a corresponding write line is energized so that said forward biased diode carries current to the core memorywhile the remainder of the diodes of the selected group are actively back biased to prevent stray capacitance between the cathode of read diodes and ground and between the anode or write diodes and ground from being inadvertently charged.

2. A read and write drive circuit system as set forth in claim 1, wherein said selection means comprises a first driving transistor having collector and emitter terminals, and a second switching transistor having collector and emitter terminals, a

' source of positive voltage and a source of negative voltage,

said voltage divider comprising a first load resistor connected between said source of positive voltage and said collector of said first driving transistor, and a second load resistor connected between the emitter of said second switching transistor said selected drive circuit being connected to the emitter of said first drive transistor and said cathode of said diode of said selected drive circuit being coupled to the collector of said second switching transistor. g

3. A read and write drive circuit system as set forth in claim 2. wherein the magnitude of said positive and negative voltages are equal and the equivalent resistance between said emitter of said first driving transistor and said source of posi tive voltage is greater in value than the equivalent resistance between said collector of said second switching transistor and said source of negative potential.

4. A read and write drive circuit system as set forth in claim 3, comprising a read line and a corresponding write line and a switch terminal energized for pairs of corresponding read and write lines, a second driving transistor having emitter and collector terminals, said emitter of said first driving transistor and said collector of said second driving transistor connected tosaid read and write lines respectively, a first switching and said source of negative voltage, said anode of the diode of transistor having emitter and collector terminals, a third load resistor connected between the emitter of said second driving transistor and said source of negative voltage, a fourth load resistor connected between said collector of said first switching transistor and said source of positive voltage, said collector of said second switching transistor and said emitter of said first switching transistor connected together and to said switch terminal, and a write diode having an anode and a cathode, said anode of said write diode coupled to said switch terminal and said cathode of said write diode connected to said collector of said second driving transistor.

* i i l

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3119025 *Nov 30, 1961Jan 21, 1964Honeywell Regulator CoPulse source for magnetic cores
US3135948 *Aug 28, 1961Jun 2, 1964Sylvania Electric ProdElectronic memory driving
US3209339 *Oct 26, 1960Sep 28, 1965Rca CorpSwitching circuits
US3210741 *May 3, 1961Oct 5, 1965Sylvania Electric ProdDrive circuit for magnetic elements
US3343130 *Aug 27, 1964Sep 19, 1967Fabri Tek IncSelection matrix line capacitance recharge system
US3451048 *Oct 5, 1965Jun 17, 1969IbmDrive system for a magnetic core array
US3473149 *May 2, 1966Oct 14, 1969Sylvania Electric ProdMemory drive circuitry
US3519995 *Feb 15, 1967Jul 7, 1970Burroughs CorpBias restoration arrangement for digital circuit matrix
US3525983 *Aug 24, 1967Aug 25, 1970Honeywell IncCompressed selection matrix
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4069480 *Jan 3, 1977Jan 17, 1978Ferranti-Packard LimitedBlanking circuit for electromagnetic display
Classifications
U.S. Classification365/189.9, 365/243, 365/230.7
International ClassificationH03K17/66, H03K17/04, H03K17/60, H03K17/041, G11C11/02, G11C11/06
Cooperative ClassificationH03K17/04113, G11C11/06007, H03K17/662
European ClassificationH03K17/041D, G11C11/06B, H03K17/66B2
Legal Events
DateCodeEventDescription
May 27, 1983AS01Change of name
Owner name: TDK CORPORATION
Owner name: TDK ELECTRONICS CO., LTD.
Effective date: 19830301
May 27, 1983ASAssignment
Owner name: TDK CORPORATION
Free format text: CHANGE OF NAME;ASSIGNOR:TDK ELECTRONICS CO., LTD.;REEL/FRAME:004133/0509
Effective date: 19830301
Owner name: TDK CORPORATION, JAPAN