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Publication numberUS3680076 A
Publication typeGrant
Publication dateJul 25, 1972
Filing dateJul 13, 1970
Priority dateJul 13, 1970
Publication numberUS 3680076 A, US 3680076A, US-A-3680076, US3680076 A, US3680076A
InventorsDuffek Kenneth John, Nolan Thomas Hoyt
Original AssigneeWestern Electric Co
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Data display systems
US 3680076 A
Abstract
A digitally controlled raster-type data display system utilizes a special circuit for generating the diagonal-line portions of characters to be displayed on the display system comprising a time-delayed monopulser circuit actuated by a plurality of time-constant circuits combinationally selected by selection means within the display system. This results in high resolution of characters displayed while using less circuitry for character generation than previously taught by the art for an equivalent degree of resolution of displayed characters.
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Description  (OCR text may contain errors)

D United States Patent 11 1 3,680,076 Duffel: et al. 1 July 25, 1972 s41 DATA DISPLAY SYSTEMS 3,568,118 3/1911 Day .Q .340/324 A 3.474,438 l/ I969 Lauher ....340/324 A 1 WWW M 3,406,387 l0/l968 Werme ..a4o/324 A llcyt Nolan, Westmont, both of III.

73 A Wm W c [m Primary Examiner-John W. Caldwell I 1 8m: New York. y, Assistant Examiner-Marshall M. Curtis Anomey-R.J.Guentherand.lames Warren Fall: [22] Filed: July 13, 1970 [2|] Appl. No.: 54,399 ABSTRACT A digitally controlled raster-type data display system utilizes a special circuit for generating the diagonal-line portions of E (gl. .340/324 A, l78/DlG 3, 3| "s to be displayed f p yv y comprising a 58 sun. 340/324 315" 8 I9 22 time-delayed monopulser clrcult actuated by a plurality of l 1 mm 3 b 6 7 time-constant circuits cornbinationally selected by selection means within the display system. This results in high resolution of characters displayed while using less circuitry for character [56] RM cm generation than previously taught by the art for an equivalent UNITED STATES PATENTS degree of resolution of displayed characters.

3,l09,l66 /1963 Kronenberg et al. ..340l324 A M Clah, 5 Drawing figures 63A 561E471 ;69A V 638 77A 2 T r ,25 63C m Lam SLOPE 630 mien 6 V PULSER 76B 64B saa' s99 9- 7711' 65B 1? 2o %i5 5s 57 l ,1 MON/o 30 54 5a CONTROL V v DECODER PULSER v l 7| 1 1 1 v1 E0 BINARY ENC DER -23 T coumsn I BI 14 32 M5 TRANSLATOR DISPLAY I3 DEVICE PATENTEDJULZS I972 v SHEEI10F4 C50 C51 C52 C53 FIG. 2

CS0 CS1 CS2 CS3 A. J. DUFFEK 7. H, NOLAN W KP A T TORNE V INVEN TORS DATA DISPLAY SYSTEMS FIELD OF THE INVENTION This invention relates to digitally controlled data display systems and more particularly to character generators within such display systems for the generation of the desired alphanumeric characters.

BACKGROUND OF THE INVENTION Display systems of this type are known in the art. Generally, in such systems television type monitors are employed with standard scanning rasters such that the scanning beam produces a short slice of each character for each scan line. The desired alphanumeric characters are then built up in successive scans. In these systems the display area is divided into character blocks in each of which a character may be displayed. Each character block is in turn subdivided in elemental areas, arranged in columns and rows. As the electron beam scans the display device, it is modulated by the input signal from the display system character generator to brighten or leave dark individual ones of these elemental spaces, thus building up on the face of the display the desired character.

In this type of character display system there are two conflicting goals. One goal is to make these elemental areas very small so that the characters displayed can have a very fine degree of resolution for a given size character block. The other goal is to make the elemental areas relatively large, with a minimum number of such elemental areas in the character block, thereby minimizing the amount of logic circuitry required.

As the number of elemental areas within a character block decreases, the resolution of the characters displayed therein also decreases. This character degradation is first noticeable on the diagonal and curved line segments of the alphanumeric characters. Where only horizontal and vertical line segments are employed to make up the displayed characters, resolution problems arise in differentiating between such alphanumeric characters as A and R or B and 8. The character K is another character requiring good resolution because of the short diagonal lines included in the character.

Priorly, it has therefore generally been necessary in this type of system to increase the number of elemental spaces within a character block to reach a compromise between these two conflicting goals. For example, to obtain adequate resolution prior systems have subdivided the character block into over a hundred elemental areas, one prior system employing 256 such individual areas within the character block. The price for such fine resolution has of course been an increase in the complexity and amount of the logic circuitry required.

It is therefore an object of our invention to allow very fine resolution for diagonal lines in a character display system while still employing a relatively few elemental areas in a character block.

SUMMARY OF THE INVENTION In accordance with our invention this high degree of resolution for diagonal lines is obtained while still utilizing a relatively small number of elemental areas in a character block and thus without the circuit complexity priorly required for such resolution. Specifically, in one embodiment of our invention, only 40 elemental areas are contained in a character block, the 40 areas being defined by rows and four columns. This is attained in accordance with an aspect of our invention by providing a separate diagonal line generator circuit which generates the smaller time periods necessary to define the smaller elemental spaces for the display of diagonal lines.

In one specific illustrative embodiment of our invention, four resistor-capacitor networks may be combined in l6 combinations under control of the display system logic to generate l6 timing intervals. However, only 10 timing intervals are utilized in our illustrative embodiment as only 10 scan lines are utilized to display a character block.

In this specific embodiment, a monopulser provides a timedelayed output pulse equal in time duration to the time interval it takes the scanning electron beam to scan a single elemental space. The timing intervals generated utilizing the resistor-capacitor networks are used to time the delay before start of the output pulse from the monopulser and are such that on adjacent scan lines the monopulser output pulse is in fact shifted in time approximately one-third the time interval of an elemental space. Accordingly, the necessary finer resolution is obtained for the diagonal line segments of characters although the overall timing provided by the display system circuitry is coarse though sufficient to adequately display the vertical and horizontal segments of characters. Thus even though the desired fine resolution for the diagonal lines is achieved, less total logic circuitry is required to generate these characters than priorly used for an equivalent degree of resolution of displayed characters. 1

DESCRIPTION OF THE DRAWING The above and other objects and features of our invention will become more apparent upon consideration of the following detailed description in conjunction with the drawing, in which:

FIG. 1 isa graphical illustration of a single character block in a display system having only 40 elemental spaces with the character K displayed in accordance with prior display systems;

FIG. 2 is a graphical illustration of the same single character block having the character K displayed in accordance with our invention;

FIG. 3 is a simplified schematic representation of a generalized display system;

FIG. 4 is a schematic representation of one illustrative embodiment of our invention; and

FIG. 5 is a schematic representation of a diagonal line generator in accordance with this embodiment of our invention for incorporation in the display system of FIG. 4.

DETAILED DESCRIPTION l. The Single Character Block FIGS. I and 2 Turning now to the drawing, there is depicted in FIG. 1 a single character block having only 40 elemental spaces as defined by 10 rows, numbered 1 through 10, and four columns, numbered CSO through CS3. The definition of these rows and columns will be discussed below with reference to FIG. 3. For the moment, it is sufficient to recognize that prior display systems have the capability of generating, in accordance with specified inputs, blanking and unblanking signals such that the electron beam causes a display to be generated at specified elemental areas. Specifically, if such a prior system were to utilize only 40 elemental areas, in order to display the character K, the elemental areas to be utilized would, as shown in FIG. I, be those defined by all of column CSO; column CS1, rows 5 and 6; column CS2, rows 3, 4, 7, and 8; and column CS3, rows 1, 2, 9, and 10. As is apparent the resolution is very poor with the resultant character more being recognized as the letter K than being itself actually a letter K. This is because the number of elemental areas employed is too small for the prior display system techniques of generating the display.

In FIG. 2 the same character block having 40 elemental areas is utilized, but the character K displayed therein has been displayed in accordance with our present invention. As is readily apparent, the resolution is much better and the character more readily recognized. As can be seen, and in accordance with an aspect of our invention, the display elements for the diagonal lines in adjacent rows are displayed by less than a full column distance, even though each such display element is in fact a full column wide. 2. Generalized Display System and Definition of Terms-FIG. 3

Before describing the details of our invention wherein this finer resolution, as depicted in FIG. 2, is obtained even though only 40 elemental areas are employed in the character block, it will be helpful to describe the general control logiccircuitry utilized and to define the various terms to be utilized..This can be best done with reference to FIG. 3.

As there seen the display surface 10, which is ad vantageously the face of a cathode ray tube, as is known in the art, will have defined on'its face a series of register rows,

an oscillator 14, a binary counter which is made up of a series of subcounters 15A, 15B, 15C, 15D, and 155 driven by oscillator 14, and decoders 16, I7, 18, and I9 driven by the subcounters to break the display area of display device 10 into a multiplicity of rows in which characters maybe displayed,

. and into character blocks'within each row in which a single character may be displayed. Each row is referred to as a register. In addition each character block is subdivided into four 1 (not shown in FIG. 3) generating horizontal equalization and vertical "columns and then ten'hor'i'zontal rows or lines, as 1 discussed above, by thescanning beam of display device 10. The combination of the vertical and horizontal subdivisions of a character block define the smallestelement, the elemental space,of which there are forty within a character block.

, Decoders l7, l8, and 19 also function to define buffer areas between characters in a row,-rows of characters, and groups of rows of characters. The outputs from the decoders are the timing for the display system and are used to gate binary encoded data into the display system in proper order, control the generation of synchronization signals necessary for a video signaLdriving conventional television monitors, and control translation ofthe input binary encoded data into video signals to be displayed on television monitors, all in a manner taught by the prior art.

Oscillator 14 in thedisplay system is the one source of signal from which all timing functions are derived. Oscillator l4 drives a 16bit binarycounterls, "where the 1-bit character stage 15A is the lowest order bit of-the counter and the 1-bit field stage 15E is the highest order bit of the counter. An output from each of the sixteen stages of binary counter 15 is used to derive all necessary timing functions forthe display 1 system as discussed hereinafter.

Character decoder 16 has an oscillator input on lead 38 and an input from .the first stage of binary counter 15 on lead 35.

The first stage of binary counter 15 is called the character subcounter ISA. Subcounter 15A is connected by lead 35 to character decoder 16 which, under control of the oscillator 14 over lead 38 and the character subcounter 15A, functions to give single sequential outputs on four leads representing the four vertical columns into which a character block is subdivided. This defines the width of the elemental space described heretofore. w

A bit decoder 17 has six inputs on leads 37 from the binary counter 15. These are from the second through seventh order stages of the binary counter 15, which stages comprise the bit subcounter 15B. Sixty-four binary codedcombinations are available on leads 37, thereby subdividing display device 10 horizontally into 64 character block widthsfllhe bit decoder 17 converts these coded inputs into individual lead outputs vertical synchronization pulses, discussed further below.

A line decoder 18 has three inputs from the eighth through V g the IOth'stages of binary counter 15; these three stages of binary counter 15 comprise a line subcounter 15C. The eight binary coded output combinations from line subcounter 15C are also converted to individual lead outputs which are singly, sequentially energized. The eight output leads represent eight sequential scans of the electron beam of display device 10 which make up a horizontal area in which a row of characters may be displayed. As is known in the art, scanning interlace is.

used which effectively gives l6 scan lines of the electron beam to display a row of characters. Of the interlaced l6 scan lines, the top four and bottom two are used as vertical buffer spaces between reg'nter rows of characters. i

A register decoder 19 has five inputs from the eleventh through 15th stages of binary counter l5; these five stages comprise a register subcounter 15D, the 32 possible binary coded output combinations of which on leads 3l.are converted to individual lead outputs singly, sequentially energized representing each of the 32 horizontal areas on display device 10 in which a row of characters could possibly be displayed. The first and last four outputs representing the top and bottom most possible register rows of characters are not utilized, thereby leaving a buffer space at the top and bottom edge of display device 10, respectively. Additional outputs may be deleted a desired to create blank bands between groups of rows of characters for ease of reading the display or for any other reason. j The last stage of binary counter 15 comprises field subcounter lSE and gives an output-during each entire odd scan field to the diagonal line generator to enable one of four resistor-capacitor networks in diagonal line generator 25 in FIG; 4. This resistor-capacitor network enabled gives the smallest time period available, approximately one-third the time interv val of an elemental space, and allows for the generation" of smooth diagonal lines with the interlaced scanning. 3. Detailed Description-FIG. 4'

One specific illustrative embodiment of our'invention wherein a diagonal line generator 25 is incorporated in a data display system is depicted in FIG. 4. As is known in systems of this type, conventional television monitors maybe employed for the display device l0and, accordingly, vertical, horizontal,

and equalization synchronization signals are provided as well as the character display information and logic control signals. The various circuits depicted in FIG. 4 for these purposes are well known in the art and their specific details need not be described herein.

' In the specific illustrative embodiment depicted in FIG. 4 horizontal synchronization signals occur at the beginning of every scan line and, as bit decoder 17 divides each scan line into 64 time intervals, one per 64 individual leads, it is used to enable horizontal synchronization signals from synchronization generator 24 by energizing lead 44 at'the beginning of each scan line. Vertical synchronization signals occur at the beginning of every scan field and the concurrent signals from two of the decoders are needed to determine when television synchronization generator 24 is to generate the vertical synchronization signals. The first signal necessary to generate the vertical synchronization signals is from register decoder 19 which are singly; sequentially energized. Various single outdle of a scan line to drive a synchronization signal generator on lead 48, indicating the'topmost possible row of characters is being scanned; in this embodiment no characters are displayed therein and it serves as a blank border at the top of display device 10. The second signal necessary to generate vertical synchronization signals is from the line decoder 18 onlead '43 indicating when the first line is being scanned in the topmost possible row of characters. lnterlacing is obtained by resetting line subcounter 15C, register subcounter 15D, and

field subcounter to zero when inputs from line decoder 18 and register decoder 19 determine that the last. line of the last row is being scanned. Bit decoder 17 indicates when scanning is midway through the last line, andgfield subcounter 155 indicates the odd scan field is being scanned. This effectively skips one scan line during every other scan field. This also triggers generation of vertical synchronization signals from TV sync generator 24 midway through the first scanned line of even scan fields; otherwise vertical synchronization signals occur at the start of the first scanned line of the odd scan field.

Equalization synchronization signals occur during the last three and first six scan lines making up a complete scan field, and concurrent signals, at television synchronization generator 24, from the same three decoders as used for vertical synchronization signals, are needed. The signal on lead 50 from register decoder 19 indicates that the bottommost possible row of characters is being scanned, though in like manner it is used as a blank border at the bottom of display device 10. The signal on lead 34 from line decoder 18 indicates that the last line is being scanned in the bottommost possible character row. The signal on lead 44 from bit decoder 17 indicates where in the last scan line the equalization synchronization signals are to appear.

The synchronization signals output from television synchronization generator 24 on lead 58 are in proper time sequence to be mixed into the composite video signal by a video encoder 23 to drive conventional television monitors. Character display information is also mixed into the composite video signal by video encoder 23 after processing input binary encoded characters as discussed hereinafter.

Data to be displayed is applied over leads 26 from an external data source to the data input and translator 13 which generates the signals for the characters to be displayed. As is known in the art, the data input and translator circuit 13 may store data representing a row of characters as the electron beam scans a register row and provides an individual translation signal for each elemental space in each character block.

All characters displayed are made up from the possible available groupings of elemental line segments. in accordance with an aspect of our invention, these include not only horizontal and vertical groups of segments but also diagonal groups of such segments. One may consider that the translator circuit 13 includes a library of possible line segments from which the characters may be formed by appropriate control signals on output leads 6 from data translator 13 to video encoder 23, for all necessary vertical and horizontal segments, while control signals are applied on output leads 60, in accordance with our invention, to a diagonal line generator, described further below, for all diagonal line segments necessary to make up all characters.

Referring back now to FIG. 2, it may be worthwhile to digress a moment to discuss the generation of the horizontal and vertical line segments for the letter K there depicted. As there seen, there is a vertical line segment defined by column CSO entirely and a horizontal line state defined by columns CS1 and CS2 and line LS4. As is known, the video encoder requires concurrent signals, as at an AND gate therein, from the character decoder 16, over leads 57, from line decoder 18, over leads 45, and further, a signal on an appropriate lead 6 from translator 13, to cause display of the horizontal line segment for the letter K, while a character state zero (CSO) output lead from the character decoder 16 and a different translator output lead 6 are energized and applied to another AND gate in encoder 23 to display the vertical line segment of the character K.

4. Diagonal Line GeneratorFIG. 5

In accordance with out invention, the generation of video signals representing diagonal line segments, such as utilized by the character K, FIG. 2, is attained by diagonal line generator 25. These video control signals are applied to video encoder 23 over lead 59 to be assembled there into the composite video signal. One specific illustrative embodiment of a diagonal line generator in accordance with our invention is depicted in FIG. 5. As there seen, the circuit has, in fact, two diagonal line generators therein, a first generating the positive slope diagonal line segments that may be required and the other generating the negative slope diagonal line segments.

Each diagonal generator contains four capacitors 64, 65, 66, 67 that are enabled in 16 combinations by outputs from binary counter 15 over leads 9, 36A, 36B and 36C. Amplifiers 76, 77, 78, and 79 are provided for each lead from the binary counter, with additional inverting amplifiers 63 for the positive slope diagonal line generator. An additional timing capacitor 68 and timing resistor 69 are also provided for both the positive and negative slope generators for adjustment purposes.

Capacitors 64A and 64B are energized by the single output from field subcounter 155 which is energized for every odd scan field. Capacitors 65A and. 65B, 66A and 66B, and 67A and 67B are energized by the three output leads 36 from line subcounter 15C. These three outputs represent line states LSO through LS7 as the scanning beam displays a single register row of characters; as noted in FIG. 2, only line states LS2-LS6 are actually used.

Capacitors 65A and 65B, 66A and 66B, and 67A and 67B are energized in all eight possible combinations for both odd and even scan fields of display device 10. Capacitors 64A and 648 by their energized or unenergized states provide for the interlaced scanning, and depend on the field state of subcounter 15E. This produces a total of 16 different time-constant periods which may delay the pulse output of each monopulser 70 in 16 steps, thus creating the video signal for a diagonal line.

As can be seen in FIG. 5, the diagonal line generator circuit 25 also includes NAND gates 71, 72, 73, and 74 and NOR gate 75. A single time delay is used for each scan line and the monopulser supplies a pulse output for each character block as the beam performs a single scan, whether that output is needed or not. At the end of each character block, the monopulser 70 is reset, by a signal from the control decoder 20 over lead 62, thus restarting the time-delayed output for the subsequent character block.

Accordingly, the outputs 82 and 83 from the monopulsers 70 in the positive and negative slope diagonal generators are continuously being generated and are fed to the gates 71, 72, 73, and 74 along with outputs from translator 13 over leads 60A, 60B, 60C, and 60D by which diagonal line segments are gated to video encoder 23 as required to display a character. The four leads from translator 13 represent four conditions that select the desired diagonal line segments to display all characters on display device 10. Leads 60A, 60B, 60C, and 60D are energized to generate the upper half positive slope diagonal line, lower half positive slope diagonal line, upper half negative slope diagonal line, and lower half negative slope diagonal line, respectively, as they are needed to display a character. In the case of the letter K shown in FIG. 2, leads 60A and 60D are energized.

As the diagonal generators generate l6-step diagonal lines, of which only 10 are utilized, additional inputs to NAND gates 71, 72, 73, and 74 are required. These inputs come from binary counter 15 on leads and 81 which are only energized for line states zero through three (LSO through LS3) and line states four through seven (LS4 through LS7) respectively. Video encoder 23 allows only the diagonal line portions within a character block to be passed over lead 61 to display device 10.

In one specific illustrative embodiment wherein the character block was 1,020 nanoseconds long and a single elemental area was 255 nanoseconds long, the diagonal line generator was capable of providing output signals of elemental area length, i.e., 255 nanoseconds, at time intervals of 85 nanoseconds. Thus, in accordance with our invention, while the logic circuitry provided for the vertical and horizontal line segments could only provide a very coarse resolution of diagonal lines, namely only four possible different horizontal spaces at 255 nanosecond intervals, by the employment of a separate diagonal-line generator, much finer resolution, namely, 85 nanosecond intervals, was obtained.

in this embodiment capacitors 67A and 678 were 800 pf, capacitors 66A and 668 were 400 pf, capacitors 65A and 65B were 200 pf, capacitors 64A and 648 were 100 pf, and capacitors 68A and 688 were 2,000 pf. These capacitors determine, depending on the state of the line and field subcounters, as discussed above, the delay for that particular line segment alter the circuit is enabled. Thus, horizontal-line segments, of one column width, can be provided, which segments, however, need not commence at the start of a column timing.

It is apparent that various modifications may be made without departing from the spirit and scope of the invention. Thus, the particular number of segments available and the translations required may obviously be different than in the specific embodiment herein depicted.

What is claimed is:

l. A display system for displaying characters on a display device that exhibits a scan-line raster and wherein each character is displayedin one character block on said display device, said display system including a control circuit operating in synchronization with said scan-line raster and'controlling the generation of signals for thedisplay of horizontal and vertical line segments of said characters, the invention comprising pulse-generator means generating a single pulse output for each scan line of each character block on said display device, 7

a plurality of time-delay means selectively energized by said control circuit to determine the tum-on time of said pulse-generator means, and

means energized by said control circuit in response to signals indicating characters to be displayed on said display device for selecting particular ones of said pulse outputs for the display of line segments other than said vertical and horizontal line segments of said characters.

2. A display system for displaying characters on a display monitor exhibiting I a scan-line raster and wherein each character is displayed in a character block on said display monitor, said display system including an oscillator, 7

a counter driven by said oscillator,

decoder means responsive to outputs from said counter to define the scan-line raster and to divide said character blocks into rows and columns of elemental spaces selectively illuminated to display characters in said character blocks, t Y

a character generator responsive to signals indicating characters to bedisplayed on said display monitor and to said decoder means for generating signals for characters displayed on said display monitor, said signals including signals for vertical and horizontal line segments of said characters, and

a diagonal line generator responsive to said counter and said character generator for generating signals for diagonal line portions of characters to be displayed on said display monitor, the invention is said diagonal line generator comprising,

a plurality of time-delay means combinations of which are energized by said counter to produce predetermined time-delayed signals for each scan line of said raster, pulse-generator means energized by each of said timedelayed signals to generate a time-delayed pulse, and means responsive to said counter and said character generator for selecting particular time-delayed pulse outputs from said pulse-generator means for the display of' diagonal line segments of characters displayed on said display monitor.

3. The invention'in accordance with claim 2 wherein the invention in said diagonal line generator further comprises means in said pulse-generator means responsive to an output from saidd'ecoder means for resetting said time-delay means when each scan line ends scanning a character block,'said resetting means enabling said time-delay means to time the generation of another time-delayed pulse for a subsequently scanned character block.

I at other than said elemental spaces.

5. The invention defined in claim 4 wherein said plurality of time-delay means includes a first plurality of timedelay means for generating positive slope diagonal line signals for the character blocks and a second plurality of time-delay means for generating negative slope diagonal line signals'for the character blocks.

6. The invention defined in claim 5 wherein said first and second plurality of time-delay means are energized by said counter to produce uniform increments of time delay in the tum-on time of said pulse-generator means.

7. In a data display system for displaying'characters on a scan-line raster display device, the combination comprising logic means for defining on said display device character blocks of a predetermined number of elemental areas, said areas being arranged in rows and columns in said character blocks, i

a character generator responsive to signals indicating characters to be displayed on said displaydevice and to said logic means for causing individual ones of said elemental areas to be displayed to generate horizontal, and vertical lines in said character blocks,

means responsive to first signals from said logic. means-at the beginning of each scan of each of said character blocks for producing second signals selectively timeshified from each of said first signals, and

means responsive to said character indicating signals for selecting particular ones of said second signals for displaying other than horizontal and vertical lines in said character blocks. i I

8. In a data display system for displaying characters on a scan-line raster display device, the combination comprising logic means for defining on said display device character blocks of a predetermined number of, elemental areas, said areas being arranged in rows and columns in said character blocks, 1 t

a character generator responsive to signals indicating characters to be displayed on said display device and to said logic means for causing individual ones of said elemental areas to be displayed to generate horizontal and vertical lines in said character blocks, and line generator responsive to said character indicating signals and to said logic means for causing displays in said character blocks in said rows in other than said elemental areas to generate other than horizontal andvertical lines in said character blocks, said'line generator comprising means for producing a pulse equalin time duration to the time a scan line scans an elemental area, and time delay means energized by said logic means for delaying the initiation of said pulse.

9. In a data display system, the combination in accordance with claim 8 wherein said time-delay means comprises a plurality of time-delay networks each providing a different time delay.

with claim 10 wherein said time-delay means comprises a first plurality of said time-delay networks arranged to provide in'-,

creasing orders of time-delay for the displayof lines having positive slopes, and a second plurality of said time-delay networks arranged to provide decreasing orders of time delay for the display of lines having negative slopes.

12. In a display system for displaying characters on a display monitor exhibiting a television scan-line raster, each character being displayed in one character block onsaid display monitor and said character blocks being dividedinto elemental spaces selectively illuminated to display characters therein, the com-, bination comprising 10. In a data display system, the combination in accordance counter means,

oscillator means driving said counter means in synchronization with scan lines of said scan-line raster,

decoding means responsive to outputs from said counter means for dividing said scan-line raster into groups of scan lines defining rows of character blocks, dividing said groups of scan lines into character blocks, and dividing each of said scan lines into elemental spaces,

means for generating signals for vertical and horizontal line segments of characters displayed on said display monitor, said vertical and horizontal line generating means being responsive to outputs from said decoding means and an input signal to said display system indicating the character to be displayed,

means for generating signals for positive and negative slope diagonal line segments of characters displayed on said display monitor, said diagonal line generating means comprising,

pulse-generator means having a single pulse output for each said character space scanned by each said scan line,

a plurality of time-delay means determining the turn-on time of said pulse-generator means, said time-delay means being selectively enabled by said counter means in a sequence for each said scan line to produce uniform positive and negative increments of time delay in the turn-on times of said pulse-generator means, and the pulse output from said diagonal line generating means occurring at shorter time intervals than said elemental spaces to effectively create a larger number of said elemental apace divisions in said character blocks,

gating means connected to said pulse-generator means and responsive to said counter and said input character indicating signal to gate only those diagonal line signals necessary to display characters on said display device, and

video encoder means for combining outputs of said decoding means, said vertical and horizontal line segment generating means, and said gating means to produce a video signal to display characters on said display monitor.

13. The invention in accordance with claim ll further ineluding reset means energized by said logic means when each of said scan lines begins to scan each of said character blocks for enabling said time-delay networks to delay another pulse from said monopulser.

14. The invention in accordance with claim 13 wherein said display device is a television monitor having an interlaced scan-line raster and wherein said first and second pluralities of time-delay networks each include a time-delay network energized by said logic means only for odd scan fields of said scanline raster to provide for smooth negative and positive slope diagonal lines.

i t t i t

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3902476 *Apr 2, 1974Sep 2, 1975Unirad CorpScanning display for sampled data
US3918039 *Nov 7, 1974Nov 4, 1975Rca CorpHigh-resolution digital generator of graphic symbols with edging
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Classifications
U.S. Classification345/467
International ClassificationG09G5/28
Cooperative ClassificationG09G5/28
European ClassificationG09G5/28
Legal Events
DateCodeEventDescription
Mar 19, 1984ASAssignment
Owner name: AT & T TECHNOLOGIES, INC.,
Free format text: CHANGE OF NAME;ASSIGNOR:WESTERN ELECTRIC COMPANY, INCORPORATED;REEL/FRAME:004251/0868
Effective date: 19831229