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Publication numberUS3683359 A
Publication typeGrant
Publication dateAug 8, 1972
Filing dateApr 30, 1971
Priority dateApr 30, 1971
Publication numberUS 3683359 A, US 3683359A, US-A-3683359, US3683359 A, US3683359A
InventorsKleinschnitz Andrew J
Original AssigneeDelta Data Syst
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Video display terminal with automatic paging
US 3683359 A
Abstract
A video display terminal is provided having a refresh memory, a character generator and a display means. The refresh memory is utilized to enable the character generator to provide signals to the display means for displaying characters. The codes of the characters are stored in the refresh memory. The refresh memory has a capacity to have stored therein a plurality of contiguous lines of characters larger than the number of lines which can be simultaneously displayed on the display. Means responsive to the refresh memory are provided for enabling the display of a selected plurality of contiguous lines of characters from the refresh memory in the display means which includes selection means for changing the selected lines from the refresh memory which are displayed in the display means.
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Description  (OCR text may contain errors)

Waited States Patent 1 3,683,359

Kleinschnitz 1 Aug. 8, 11972 [54] VKDEO DISPLAY TERMINAL WITH AUTOMATIC PAGING Primary Examiner-David L. Trafton [72] lnventor: Andrew J. Kleinschnitz, Willow mwmeycaesar Bernstem Cohen Grove, Pa.

[57] ABSTRACT [73] Assignee: Delta Data Systems Corporation, I

comweus Heights, A video display terminal 18 provided having a refresh memory, a character generator and a display means. Filed: April 30, 1971 The refresh memory is utilized to enable the character [21] APPL NOJ 139,064 generator to provide signals to the display means for displaying characters. The codes of the characters are stored in the refresh memory. The refresh memory has [52] US. Cl. ..340/324 A, 340/1725 a capacity to havc stored therein a pluramy of com [51] Illl. Cl (7106f 3/14 tiguous lines of characters larger than the number of Fleld Of Search A lines can be simultaneously on the display. Means responsive to the refresh memory are [56] References cued provided for enabling the display of a selected plurali- UNITED STATES PATENTS ty of contiguous lines of characters from the refresh memory in the display means which includes selection 3,082,294 3/1963 Dean ..l 78/6.8 means for changing the selected lines from the refresh 3,406,387 10/1968 Werme ..340/324 A memory which are displayed i the display means 3,422,420 1/1969 Clark ..340/324 A 3,614,766 10/1971 Kievit ..340/324 A 10 Claims, 11 Drawing Figures DELETE PATH (OAITROL EDIT (OUTFOL CoMT/POL CONTROL TIM/N CONTROL VIDEO DISPZA Y (oMPl/ PATENTEDAuc a 1912 SHEET 1 [IF 5 INVENTOR I w W W m J J m. R w W ATTORNEYS- characters, the codes of which are stored in the refresh memory. These refresh memories usually require a memory storage location for each possible display character located on the display screen. A substantial portion of the messages which are stored in the refresh memories and displayed on the display do not require full lines of the display surface and, thus, waste positions in the refresh memory. For example, it is common to see display presentations'which use (50 percent) or less of the available memory locations of the refresh memory.

Systems have been provided which allow the use of a smaller memory for the typical application wherein smaller percentages of the display surface are used. In these video display terminals, the refresh memory utilizes characters to indicate the end of the line. Thus, each time the character representative of the end of the line is reached, a new line is begun on the display. A failing of these systems is, however, that they are limited in flexibility because they cannot utilize all of the available memory positions after the message has been placed within the refresh memory. Thus, if a message stored in the refresh memory is short enough that it does not fill the entire refresh memory but does use all lines of the display, the unused portion of the refresh memory cannot be utilized since the display capability cannot be expanded to display messages stored in the unused portion of the memory.

It is, therefore, an object of the invention 'to overcome the aforementioned disadvantages.

Another object of the invention is to provide a ne and improved video display terminal which utilizes a refresh memory with maximum storage capability for the amount of information to be displayed.

Another object of the invention is to provide a new and improved video display terminal which utilizes a unique organization of the data in the refresh memory to maximize storage capability and flexibility.

Another object of the invention is to provide a new and improved video display terminal which utilizes a refresh memory which enables the storage of more data in the refresh memory than can be displayed at one time on a display screen and means for selectively displaying portions of the data so that all of the data can 7 the character generator to provide signals to the display means for displaying characters, the codes of which are stored in the refresh memory. The refresh memory has' stored therein a plurality of contiguous lines of characters larger than the number of lines which can be simultaneously placed on the display. Means are provided which are responsive to the refresh memory for enabling the display of a selected plurality of contiguous lines of characters from the refresh memory in the display means. The means responsive include selection means for changing the selected lines from the refresh memory which are displayed in the display means.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

FIG. 1 is a schematic block diagram of a video display terminal embodying the invention;

FIG. 2 is a diagrammatic representation of the organization of the contents of the refresh memory;

FIG. 3 is a diagrammatic representation of the paging commands;

FIG. 4 is a diagrammatic representation of the selection of lines in the refresh memory which are displayed on the video display;

FIG. 5 is a schematic block diagram of a flip-flop which is used throughout the system;

FIG. 6 is a schematic block diagram of the logic circuitry used to execute a page start instruction;

FIG. 7 is a schematic block diagram of the logic circuitry utilized to execute a form feed instruction;

FIG. 8 is a schematic block diagram of the logic circuitry utilized to execute a page up instruction;

FIG. 9 is a schematic block diagram of a portion of the circuitry which is used in conjunction with a page down or page end instruction;

FIG. 10 is a schematic block diagram of the remaining logic circuitry used to execute a page down instruction; and

FIG. 11 is a schematic block diagram of the remaining logic circuitry used to execute a page end instruction.

Referring now in greater detail to the various figures of the drawings wherein like reference numerals refer to like parts, a video display terminal embodying the invention is shown in FIG. 1.

Basically, the video display terminal includes a keyboard 20, a data register 22, an input-output (I/O) control 24, a paging control 26, an edit control 28, a character decoder 30, a path selection control 32, a refresh memory (R.M.) 34, four registers 36, 38, 40 and 42, a line buffer 44, a character generator 46, a video display 48, a timing control 50 and horizontal and vertical drivers 52 and 54. The keyboard 20 is connected to data register 22 via party line 56. The video display terminal is also connected to a computer via the party lines 56 via incoming and outgoing lines 58.

Four groups of gates 60, 62, 64 and 66 are also provided. As will hereinafter be seen, the gates 60, 62 and 64 provide three return or recirculation paths to the refresh memory 34 and gates 66 enable an input path to the refresh memory from the data register. Data register 22 is connected via output lines 68 to a first input of each of gates 66. It should be noted that gates 60, 62, 64 and 66 as shown in FIG. 1 each represent a plurality of AND gates equal to the number of parallel bits in the refresh memory 34. This is, the refresh memory 34 preferably includes 7 bits in each stage thereof. Thus, a 7 bit binary coded representation of a character is shifted in parallel through the refresh memory 34. The characters are stored serially in the refresh memory.

The data register 22 also includes a plurality of input lines 70 which are connected to the output lines of register 40. Data register 22 is also connected via lines 72 to input-output control 24. The input-output control 24 is connected via lines 73 to the edit control 28 and paging control 26. Also connected to the edit control 28 and paging control 26 s character decoder 30 which is connected thereto via lines 74. Paging control 26 and edit control 28 are connected via lines 76 and 78, respectively, to the path select control 32.

The path select control 32 includes four output lines which are labeled, respectively, in FIG. 1, DELETE, NORMAL, lNSERT" and ENTER. The delete line 80 is connected to each of the AND gates 60 which form a delete path for the return of characters to the refresh memory. The normal line 82 is connected to each of the AND gates 62 to form a normal return path. The insert line 84 is connected to each of the AND gates 64 to form an insert return path and the enter line 86 is connected to each of the gates 66.

The outputs of each of the AND gates 60, 62, 64 and 66 are connected in multiple via input lines 88 to the refresh memory 34. The output lines of the refresh memory 34 are connected to the register 36 via lines 90. Register 36 is connected via output lines 92 to register 38. Register 38 is connected via lines 94 to register 40. Register 40 is connected via output lines 96 to register 42 and register 42 is connected via output lines 98 to AND gates 64. That is, each of the output lines of the register 42 is connected to a different one of the AND gates 64.

The output lines 92 of register 36 are connected via lines 100 to the character decoder 30. The output lines 94 of register 38 are connected via lines 102 to character decoder 30 and to'AND gates 60 via lines 104. In addition, output lines 94 of register 38 are connected via lines 106 to line buffer 44. The output lines 96 of register 40 are connected to AND gates 62 via lines 108 and. to character decoder 30 via lines 110. The output lines 112 of line buffer 44 are connected to character generator 46 and to the input of the line buffer 44 via lines 114.

Character generator 46 is connected via output line 116 to the video display 48. Timing control 50 is connected to the refresh memory 34 and each of registers 36, 38, 40 and 42 via lines 118. The timing control 50 provides shift pulses on lines 118 which are provided to the refresh memory and registers 36 through 42 to synchronously shift the data from the refresh memory 34 through the registers 36 through 42.

Each of the registers 36 through 42 are similar to one stage of the refresh memory 34. That is, each of the registers 36 through 42 is 7 bits long and, thus, equal to the number of bits in each stage of the refresh memory. Timing control 50 is also connected via lines 120 to line buffer 44, to character generator 46 via lines 122, to the horizontal driver 52 via lines 124 and the vertical driver 54 via lines 126. The horizontal driver 52 is in turn connected to the video display 48 via line 128 and vertical driver 54 is connected via lines 130 to the video display 48.

In operation, data can be provided to be displayed on the video display 48 via either the keyboard 20 or the computer. The data is provided via the party line 56 to the data register 22 which is in turn provided via the AND gates 66 to the refresh memory 34. The refresh memory comprises the refresh memory register 34 and registers 36, 38, 40 and 42. The refresh memory is connected serially to registers 36, 38 40 and 42 via lines 90, 92, 94 and 96.

The recirculation of the data into the refresh memory register 34 normally takes place after a character has been shifted through register 40 and then through gates 62 to the input lines 88 of the refresh memory 34. That is, the normal line 82 from the path selection control 32 is normally enabled to cause the enabling of gates 62 to pass the characters via lines 108 to the refresh memory 88. In addition, the characters are provided via register 38 to the line buffer 44 via lines 106.

The line buffer 44 has placed therein one line of characters stored in the refresh memory at a time. That is, each line represents a line of characters that is displayed on the video display 48. Thus, if a row of forty characters is displayable on video display 48, line buffer 44 includes 40 stages each having located therein a plurality of bits equal to the number of coded binary bits representative of a character. In the preferred embodiment, there are 7 bits per stage.

The line buffer 44 is used to address the character generator 46 in combination with the signals provided on line 122 from timing control 50. The video display 48 is preferably of the scan raster type so that the characters in line buffer 44 are constantly recirculated via lines 112 and 114 through the line buffer until the number of scan lines utilized in the video display for each line of characters has progressed through the video display 48.

Video display 40 preferably comprises a cathode ray tube video display which is controlled by the horizontal and vertical drivers 52 and 54. The timing control signals on lines and 122 from the timing control are so synchronized with the horizontal and vertical drivers 52 and 54 that the signals on line 116 drive the video display to provide a numerical or alphabetical representation of the characters stored in refresh memory 34 and line buffer 44.

Registers 36, 38, 40 and 42 are utilized in conjunction with the input-output control 24, paging control 26, edit control 28 and path select control 32 to enable revision or editing of the characters displayed on the video display 48.

The organization or manner in which the characters are stored in the refresh memory 34 is best understood in connection with FIG. 2. FIG. 2 is a diagrammatic representation of the organization of characters in the refresh memory 34. Thus, as shown in H6. 2, the refresh memory 34 is a recirculating memory as indicated by the feed-back loop 132. As the top of the refresh memory 34 is a control character which is indicated by the abbreviation STX which represents the start of the text in the refresh memory 34. A second control character identified by the letters ETX represents the end of text character. Thus, the beginning of the memory is indicated by the start of text character STX) and the last usable character in the memory is indicated by the end of text character (ETX).

It should, therefore, be noted that even though the refresh memory 34 has a fixed length, the length of a display message can be variable and is effectively fixed or limited by the characters STX and E'IX which define the outer limits of the usable display characters. The third control character of importance is indicated by the letters CR which represent a carriage return character and which are provided at the end of each of the contiguous lines of display data stored in the refresh memory.

In FIG. 2, each dash represents a character which is to be displayed on a given line of the video display 48. Thus, it can be seen that a plurality of dashes are provided between the uppermost character CR and the character STX. The carriage return character is, thus, used to indicate the end of each display line. It should also be noted that the first character of the second line of display is the memory location of the refresh memory immediately following the carriage return character or end of line for the previous line of display.

Because only the number of characters actually displayed on the line of the video display are stored in the refresh memory 34, maximum utilization of the refresh memory 34 storage space is achieved. That is, assuming that forty characters can be stored on a line of the video display, and it is desired that on a given line of the display only ten characters are needed, it can be seen that there is a saving of at least 28 character storage spaces in the refresh memory on the first line alone since only the STX and CR characters are required in addition to the characters which are to be displayed on the line.

With the organization of the memory indicated herein, the data in the refresh memory may represent a large number of lines of displayable information. For example, if the refresh memory is approximately 3,000 characters in length and the average number of characters on a display line is 20, the data in the refresh memory can represent 150 lines of displayed information.

Because of practical limitations of display systems and especially that of the cathode ray tube type, 150 lines of displayed information cannot be presented simultaneously. Moreover, it is not desirable to present this many lines of information to an operator at one time.

Thus, since the memory is capable of storing more lines of information than can be presented at one time on the video display 48, it is, therefore, necessary to have a means of selecting a portion of the display representation in the refresh memory. Accordingly, a control character which indicates start of display (SOD) is used. The SOD character is used to indicate where the first character to be displayed on the first line of the video display is located in the refresh memory. Thus, in order to change the selection of which lines of display information are to be presented on the video display, it is necessary to move the start of display character (SOD) to a location other than that of its present location in the refresh memory.

As indicated in FIG. 2, since the preferred embodiment of the video display 48 can simultaneously display 27 lines of characters, the SOD character in refresh memory 34 is provided directly in front of the 27 lines of characters in the refresh memory 34 which are displayed on the screen. Thus, 27 carriage returns are located within the bracket which indicates which of the lines is displayed on the screen as indicated in FIG. 2.

Thus, there are two important items of note with respect to the diagrammatic representation of FIG. 2. First, it can be seen that all of the characters outside of the STX and ETX characters are completely ignored by the display system. That is, the characters after the ETX character and before the STX character cannot be shown or displayed on the screen of the display 48. Next, since the number of lines displayed on the screens can be shorter than the number of lines stored in the refresh memory 34 at a time, only the number of lines which can be displayed on the screen are displayed directly after the recognition of the SOD character in the refresh memory 34.

As set forth above, since the refresh memory is capable of storing more lines of information than can be displayed atone time on the video display 48, it is necessary to have a means of selecting which portion of the display representation in the memory is presented on the video display. The SOD character is used to indicate where the first character to be displayed on the first line of the video display is located in the refresh memory. Thus, in order to change the selection of which lines of display information are to be presented on the video display, it is necessary to move the start of display character (SOD) to a point other than its present position in the memory.

To accomplish the movement of the SOD character, the following commands are issued by pressing the appropriate keys provided on the keyboard 20:

1. Page start 2. Form feed 3. Page end 4. Page up 5. Page down FIG. 3 is a diagrammatic representation which is provided to aid in visualizing the operations which are executed by the aforementioned commands. In FIG. 3, each of the rectangular boxes 134, 136, 138 and 140 which are shaded therein represent a window through which data represented in the refresh memory is viewed. This can also be understood in connection with FIG. 4 wherein a document 142 is provided having a plurality of lines 144 thereon of textual material. A window 146 which is represented in dotted lines is provided through which only 27 lines of data can be seen. The shaded rectangles 134 through 140 in FIG. 3 are represented by the window 146 shown in FIG. 4. It should be understood that if the document 142 is moved up or down behind the window 146 all of the data in the text represented on the document can be scanned. Since the window is considered to be stationary and the page movable, when the printed page or document 142 is moved up one line, this is defined herein as a page up operation. When the printed page 142 is moved down one line past the window 146, this is defined as a page down operation.

The three other commands, page start, form feed and page end are commands which when executed provide a very simple way for an operator to make large jumps in the positioning of the page behind the window. Referring to FIG. 3, it can be seen that the page start command is defined as moving the page to a point where the first character of the first line of the page is displayed in the first character space of the first line of the video display. Thus, as seen in FIG. 3, the page start definition requires that the SOD character be moved to the position directly following the character STX.

The page end command is defined as moving the page to the point where the last line of information in the refresh memory is displayed on the last line of the video display. Accordingly, as indicated by rectangle 140, in order to execute a page end command, the SOD is so positioned that the ETX character is on the last line of the display. In this respect, it should be noted that the ETX character is displayed on the video display as two vertical lines The form feed command is utilized to present only a single message on the video display 48 at a time. That is, in addition to the aforementioned characters STX, CR, SOD and ETX, an end of message character (EOM) can be placed at the end of a single message of data which is stored within the refresh memory. Thus, the display presents only the data between the character SOD and the character EOM on the video display. The end of message character EOM, thus, can be placed throughout the refresh memory at the end of each group of lines which are to be displayed simultaneously as a single message.

Therefore, after a first message is displayed, a form feed command causes the characters after the EOM character (1 in FIG. 3), which was last displayed, to be displayed next. The form feed command, thus, causes the start of display character SOD to be moved to the point following the next end of message character that is encountered in the refresh memory. Thus, as indicated in the FIG. 3, the window represented by rectangle 136 is moved to the position shown by rectangle 138 which directly follows the EOM character. Thus, in a form feed command, the SOD character is moved to the character position after the EOM character.

Referring back to FIG. 1, all data and commands enter the video display terminal in the form of coded characters of 7 bits each. Each character is entered into the data register 22 and the input-output control 24 is provided to decode the character and recognize whether it is data to be entered in the refresh memory 34 or a control character.

When data is to be entered, the input-output control 24 provides the proper signal to the edit control 28 where all entries of data into the memory are controlled. When it is determined that the character provided in data register 22 is a control character, the input-output control 24 provides the proper signals to either the edit control or the paging control in accordance with the type of command issued to the inputoutput control 24.

The edit control and paging control provide the proper logic signals to the path selection logic in the path selection control 32 which control the gates 60 through 66 which form a portion of the recirculating loop of the refresh memory 34. The control of the gates 60 through 66 enables the insertion and deletion of the data character within the memory as well as the replacement of data characters with new data characters and the movement of control characters within the refresh memory.

As set forth above, the refresh memory 34 preferred in the instant embodiment is a recirculating memory. As set forth above, each character in the refresh memory 34 passes through the registers 36, 38, 40 and 42 which enable the editing of the characters in the refresh memory. The registers 36 through 42 enable four types of operation which are substeps in the paging command previously referred to. Normal operation is caused by an enabling signal on the normal line 82 from the path selection control to gate 62 which enables the characters in the refresh memory to be routed via the registers 36, 38 and 40 to the refresh memory 34. Normal operation is utilized where the characters in the refresh memory are constantly being displayed on the screen of the video display 48.

A first operation called delete enables the removal of a character from the refresh memory without leaving a space between the previously preceding and following characters. This function, thus, closes up the data from the previous organization. This operation of deletion is performed by detecting when a character to be removed is at register 40. For example, when a control character such as SOD is to be removed from the refresh memory and the SOD character is in register 40, the character decoder 30 detects this condition and provides signals to the edit and page control which, in turn, provide signals to the path select control which cause the normal line 82 to be be de-energized and the delete line to be enabled. Thus, the character that is in register 40 is not re-entered into the refresh memory 34 and the character that is in register 38 immediately follows into the refresh memory the character that was ahead of the character in register 40 and which is presently in register 42.

Since gates 62 and 64 are disabled, the character in register 38 is placed directly into the last position of the refresh memory 34. The delete line 80 stays enabled until the ETX character indicating the end of the text reaches register 40 at which time the delete line 80 is disabled and the normal line 82 is enabled. This opera tion has the effect of providing an extra memory position after the ETX character which maintains the same number of positions in the refresh memory 34 as were provided previous to the delete operation. However, it should be noted that the data from one location has been removed and the remaining data closed up at that location.

The insert operation is performed in a similar manner. The insert operation requires the separation of existing data in the refresh memory and inserting a data character or control character in the position where the existing data has been separated.

in order to execute the insert operation, when a character after which it is desired to insert a new character has been entered into the refresh memory from register 40, at the next clock time the data is shifted in the registers so that the character following the one just entered into the refresh memory is located in register 40. The character to be inserted is presently located in the data register 22. The normal path via gates 62 is then disabled and the enter line 82 is enabled for entering data through gates 66 during the next clock time or shift pulse into the refresh memory.

The enabling of gates 64 and the disabling of gates 62 causes the character in register 40 to be inserted only into register 42 and not into the refresh memory. At the same time that the character in register is shifted into register 42, the enter line 86 is pulsed to enable gate 66 to pass the character in data register 22 via line 68 to input lines 88 of the refresh memory 34.

Where it is desired only to insert a space between two characters, the enter line 86 is not enabled and accordingly a blank character is placed into the refresh memory 88. Until the ETX character is detected in register 40, the normal line 82 remains disabled and the insert line 84 remains enabled. As soon as the ETX character is provided via register 42 to the refresh memory 34, the insert line 84 is disabled and normal line 82 enabled again. Thus, a character is effectively deleted from the unused portion of the refresh memory after the ETX character.

It should be noted that for each pass through the recirculating refresh memory, only one character can be inserted or deleted in the displayable area of the refresh memory. It is possible to perform more complicated editing functions such as the clearing of the whole line by issuing a single command by doing the delete operation repetitively until all of the characters on that line have been removed. Moreover, an entire line can be inserted between two lines by inserting between a carriage return and the next character in the refresh memory an additional carriage return character.

It shouldalso be noted that the characters in the refresh memory which are displayed on the video display are provided via register 38 to lines 106 which are connected to the line bufier 44. Thus, the editing of the refresh memory is not seen on the video display until a complete recirculation of the characters in the refresh memory 34.

The timing control recirculates the refresh memory 34 for each complete scan on the video display 48. Thus, after the last line has been displayed on the video display 48, the timing control 50 provides shift pulses on line 118 which cause the refresh memory to be shifted so that during the retrace time, the refresh memory is shifted around until the SOD character and each of the data characters provided on the first line are stored in the line buffer 44.

Thus, during the first line of the scan raster, each of the characters which are provided on the first line of the video display are located in the line buffer 44. After the line of characters has been displayed on the video display, the timing control again shifts the refresh memory 34 and registers 36 through 42 so that each of the characters after the first carriage return are pro vided in the line buffer 44. The second line of characters is then displayed on the video display 48.

It should be understood that the carriage return character indicates the end of the line and, thus, after a carriageretum is detected in register 38, blank spaces are provided to the line buffer 44 until the characters provided on the second line are shifted to the initial positions in line buffer 44 representative of the start of a line on the video display 48. This process continues until the last line displayed on the video display has been provided in the line buffer 44. The timing control then provides pulses on shift pulse line 118 to the refresh memory and registers 36 through 42 to cause the first line of data to be readied to be entered into the line buffer prior to the first scan line on the video display 48.

The paging control operations are basically comprised of the insert and delete operations. However, the function is to move the start of the display character to a new location within the displayable portion of the memory. That is, the portion of the memory between the ST'X and ETX characters is the displayable portion of the memory. As will hereinafter be seen, the movement of the start of display character is accomplished by first deleting the start of display character from its present location and inserting the start of display character in a new location which is determined by the logic of the paging control at a location depending upon the type of command which is issued.

As described above, the delete operation is performed by switching from the normal path to the delete path. Thus, where the start of display character SOD is to be deleted from the register, when the character is in the register 40, but before it has been entered into the memory, the path is switched from the normal path to the delete path. All characters following the SOD character are then entered into the refresh memory from register 38 until such time as the logic determines that it is desired to reinsert the start of display character into the refresh memory.

The insertion of the start of display character is performed when the paging control determines that the start of display character should be inserted between the characters which are in registers 36 and 38. The character ,is register 38 is loaded into the refresh memory through the delete path provided by AND gate 60. The same character is also shifted into register 40 and the character is register 36 is shifted into register 38. The code for the start of display character is then entered into register 40. The recirculating path is returned to the normal state before the next character is loaded into the memory. The character then loaded into the refresh memory is the start of display character SOD which is now in register 40 and takes its position in the refresh memory between the proper characters. This operation will be more completely understood in connection with the logic circuitry diagrams of the paging control utilized for the paging operations.

In FIG. 5, a block diagram is shown of a flip-flop that is used throughout the system. Flip-flop shown in FIG. 5 is known as a D-type flip-flop which is conventional in the data processing area, computer area and other areas of the digital electronics industry. The flipflop 150 includes a D input line 152, a clock (CLK) input line 154, a reset (R) input line 1 56, a set (S) input line 158, a Q output line and a Q output line 162. The operation of the flip-flop is such that when a signal is provided on the clock input 154 which changes from a negative to a positive signal, the leading edge of the signal causes a triggering of the state of the flip-flop 150 which causes the signal on the Q output line 160 of the flip-flop 150 to assume the same logic state as that applied to the D input line 152 of the flip-flop. It should be noted that this happens irrespective of the previous state of the flip-flop so that if the flip-fiop 150 was in the set state and a 1 input were provided to the D input 152, the Q output 160 would remain at a 1 input even though a clock pulse or leading edge were received at the clock input 154 of the flip-flop 150.

Similarly, if the leading edge signal on the clock input line 154 were received when the D input line 152 had a input thereto, the Q output line 160 would have generated therein a 0 output. The set input line 158 is a direct set line and overrides the clock input 154. Thus, if the flip-flop 150 is in the 0 state, a l or enabling signal on the set input line 158 causes the flip-flop to be set and the Q output line 160 to be at the 1 state. Similarly, a reset input line 156 overrides a clock input 154 and, thus a 1 on the reset input line 156 causes a reset of the flip-flop 150 and the consequent output signal on the Q output 162 to go to a l state and the output signal on the Q output 160 to go to a 0 state.

Referring now to FIG. 6, the logic circuitry to execute the page start command is shown therein. Basically, the logic circuitry in the paging control 26 which executes the page start command comprises a pair of flip-flops 200 and 202 and three AND gates 204, 206 and 208. AND gate 204 includes a first input line 210 which receives a page start signal (PST) from the inputoutput control 24 when a control character is recognized in the data register 22 indicative of a page start character being inserted into the data register from the keyboard or the computer.

The other inpgt to AND gate 204 is connected via line 212 to the Q output line of flip-flop 200. Output line 214 of gate 204 is connected to the D input line of flip-flop 200. The Q output line of the flip-flop 200 is connected to a line 216 and to a first input line 218 of AND gate 206. Line 216 is connected to the path select control and causes a delete instruction t be provided from the paging control 26 via lines 76 to the path selection control 32. The Q output line of flip flop 200 is also connected to the clock input line 220 of flip-flop 202. A true or positive signal (+V) is connected to the D input line of flip-flop 202. Line 222 which is connected to the reset input of flip-flop 202 receives a page complete signal (PG COMP) at the end of a page start command which indicates the operation has been completed.

The Q output line 224 of flip-flop 202 is connected to a first input line of AND gate 208. The second input line 226 receives an enabling signal upon the detection of the SOD character in register 40 by the character decoder 30. Similarly, the clock input line 228 of flipflop 200 also receives the signal from character decoder 30 that an SOD character has been detected in register 40.

The second input line 230 of AND gate 206 receives an enabling signal from the character decoder 30 when the STX character is recognized at register 40. As indicated in FIG. 6, where the numeral appears after either the character SOD or STX, it indicates that the character SOD or STX is recognized at register 40 by the character decoder 30. The same nomenclature is used hereinafter with respect to registers 36 and 38. The AND gate 206 provides an enabling signal on output line 232 when an STX 40 signal is received on line 230 and the flip-flop 200 is in the set state causing the high signal on input line 218.

The output of AND gate 206 when it is enabled is utilized to provide a signal on line 232 indicative of the fact that the page start logic should receive a signal indicative of a start of display at register 40 signal. That is, the legend in FIG. 6, PG SOD 40 indicates that the logic in FIG. 6 which is to receive the SOD 40 signal when the SOD 40 character is recognized in the register 40, should also receive enabling signals when AND gate 206 is enabled. Thus, an enabling signal is again provided on line 228 and line 226 to the clock input of flip-flop 200 and the AND gate 208, respectively. The output of AND gate 208 is connected to line 234 which receives a high signal when AND gate 208 is enabled by the signals on lines 224 and 226. The output line 234 is hardwired to register 40 to provide the SOD character in register 40 when AND gate 208 is enabled.

It can be seen that the operations to be performed by a page start command are to locate the start of display character, delete this character from the refresh memory, locate the start of text and insert the start of display character after the start of text character. Thus, when the page start command (PST) is received from the input-output control 24, it is applied to AND gate 204. Assuming that a previous page start command had been completed, the flip-flop 200 is in the reset state thereby causing line 212 from the Q output thereof to be enabled. Thus, gate 204 is enabled by the PST signal causing the line 214 to receive an enabling signal.

As soon as the SOD character is located in register 40, the character decoder 30 recognizes this condition and provides an enabling signal on the clock input line 228 to flip-flop 200 which causes flip-flop 200 to be set and thereby provide an enabling signal on line 216 to the path select control 32 which causes a deletion of the SOD character in register 40.

Referring back to FIG. 1, it will be remembered that the delete instruction causes the normal line 82 to be disabled and the delete line to be enabled. Thus, the SOD character in register 40 is deleted from the data in the refresh memory 34. The delete line 80 remains enabled until such time as the start of text character is received in register 40.

As soon as the STX character is in register 40, it is recognized by the character decoder 30 and provided to the paging control 26, AND gate 206 is enabled since the flip-flop 200 remains in the set condition. The output signal on line 232 is applied to both flip-flops 200 and AND gate 208 via lines 228 and 226. The signal on line 228 causes the flip-flop 200 to be reset as a result of the fact that the D input line 214 of flip-flop 200 has applied thereto a disabling signal. That is, as soon as flip-flop 200 is set, the Q output line 212 goes low causing the gate 204 to be disabled. Accordingly, upon receipt of the leading edge of the SOD 40 signal, the flip-flop 200 is reset.

When flip-flop 200 is reset, the signal on line 220 goes high thereby causing a leading edge to be applied to the clock input of flip-flop 202. Flip-flop 202 having the true signal at the D input thereof is set thereby causing the output line 224 to receive an enabling signal which causes the enabling of AND gate 208 which has applied thereto the signal from line 232.

The enabling of gate 208 causes an enabling signal on line 234 which causes the code of the SOD character to be inserted in register 40. The signal on line 234 is also applied to a suitable delay and then provided on line 222 to indicate that the page start operation has been completed. That is, the suitably delayed SOD 40 signal is used to complete the operation of the page start command and is provided on line 222 to reset flip-flop 202. Since both flip-flops 200 and 202 are in the reset condition, the circuitry is in the initial condition which enables the receipt of another page start command and the, execution thereof. The PG COMP signal provided to line 222 is also provided to the input-output control 24 and causes the disabling of the PST signal.

It should be noted that when the flip-flop 200 is reset, it causes the line 216 to be disabled which causes the edit control to return the path selection control to the normal path. That is, the delete line 80 is disabled and normal line 82 is enabled again. Thus, the SOD character which is placed in register 40 is the next character that is placed into refresh memory 34 via gates 62. It should also be noted that prior to the shifting of the SOD character in the refresh memory, the STX character is provided to the refresh memory via the gates 60 from register 38 so that the SOD character follows directly after the STX character in the memory.

The logic for executing the form feed command is shown in FIG. 7. Basically, it can be seen that the circuitry in FIG. 7 is substantially identical to that of the circuitry in FIG. 6. The form feed logic, thus, includes a pair of flip-flops 240 and 252 and three AND gates 254, 256 and 258. A first input line 260 is connected to AND gate 254 and receives the form feed signal (FF). The second input line 262 of AND gate 254 is connected to Q output line of fiip-fiop 250. The output line 264 of AND gate 254 is connected to the D input line of flip-flop 250.

The output line of flip-flop 250 is connected to a first input line 266 of AND gate 256 and to line 268 which is connected to the path select control 32 via lines 76. The second input line 270 to AND gate 256 is connected to the output of character decoder 30 and receives a signal thereon when the end of message EOM) character is recognized in register 40.

The output line 272 of AND gate 256 is connected to the clock input line 274 of flip-flop 250 and the input line 276 of AND gate 258. Both the clock. input line 274 and input line 276 also receive signals thereon indicative of the receipt of the SOD character in the register 40. The Qoutput line 278 of flip-flop 250 is connected to the clock input line of flip-flop 252. The 0 output line 280 of flip-flop 252 is connected to the second input line of AND gate 258. The output line 282 of AND gate 258 is hard-wired to the register 40 for providing the SOD character in register 40 when the AND gate 258 is enabled. The reset line 284 of flipflop 252 receives the page complete (PG COMP) signal for the form feed operation which is generated by the signal on line 282 of AND gate 258 and is then suitably delayed.

In operation, prior to the receipt of the form feed signal, the flip-flops 250 and 252 are in the reset condi tion. The receipt of a form feed signal on line 260, thus, causes the AND gate 254 to be enabled and the flipflop 250 is then set as soon as the SOD character is recognized in register 40. Upon the setting of flip-flop 250, the path select control is caused to have the normal line 82 disabled and the delete line 80 enabled. The SOD character is removed from the refresh memory. As soon as the EOM character is recognized at register 40, line 270 is enabled thereby enabling AND gate 256 which causes the FF SOD 40 signal to be generated on line 272.

The AND gate 254 which has been disabled by the setting of flipflop 250, thus, causes the flip-flop 250 to be reset as the leading edge of the FF SOD signal is provided on line 274 to flipflop 250. The resetting of flip-flop 250 causes the setting of flip-flop 252 which in turn causes the enabling of AND gate 258. The enabling of AND gate 258 results in the insertion of the character SOD in register 40 and also causes the delayed PG COMP signal on line 284 to reset the flipflop 252 thereby ending the form feed command. The PG COMP signal is also provided to the input-output control 24 to terminate the FF signal. It can, therefore, be seen that the SOD character was removed from the refresh memory and returned to a position following the next end of message character in the refresh memory. It should also be noted that when flip-flop 250 is reset, the signal on line 268 causes the path selection control 32 to change from the delete path to the normal path and thereby enables the insertion of the SOD character directly after the EOM character in the refresh memory.

Referring now to FIG. 8, the logic for the execution of the page up (PG UP) command is shown therein. The logic for the page up command is similar to the logic used inthe page start and fonn feed command shown in FIGS. 6 and 7, respectively. Thus, the page up logic includes a pair of flip-flops 300 and 302 and three AND gates 304, 306 and 308. The first input line 310 to AND gate 304 is connected to the output of the input-output control 24 via lines 73 and receives a page up (PG UP) signal when the page up command has been inserted into the data register 22 and recognized by the input-output control 24.

The second input 312 of AND gate 304 is connected to the 6 output of flip-flop 300. The output line 314 of AND gate 304 is connected to the D input line of flipflop 300. The Q output line of flip-flop 300 is connected to a first input line 316 of AND gate 306 and to line 318 which is connected to the path selection control 32. The line 318, when enabled, causes a delete operationin the path selection control.

The second input line 320 to AND gate 306 is connected from the character decoder 30 which provides an enabling signal thereon when the CR character is recognized in register 40. When AND gate 306 is enabled, it provides anoutput signal on line 322 which is received on the clock input line 324 of flip-flop 300 and input line 326 of AND gate 308. The clock input line 324 of flip-flop 300 also receives a signal thereon when the SOD character is recognized in register 40 from the character decoder 30.

The Q output line 328 of flip-flop 300 is connected to the clock input line of flip-flop 302. The D input line of flip-flop 302 is connected to a true signal source (+V) and the reset input line 330 receives a PG COMP signal thereon when the page up operation is complete. The Q output line 332 of flip-flop 302 is connected to the second input of AND gate 308 which, when enabled, provides an output signal on output line 334 which is connected to register 40 and is hardwired to provide an SOD character in register 40 when the AND gate is enabled. The output signal on line 334 is suitably delayed to provide the page complete (PG COMP) signal to line 330 and to input-output control 24 which terminates the PG UP signal.

In operation, flip-flops 300 and 302 are in the reset condition prior to the receipt of a page up command signal on line 310. AND gate 304 is enabled by the PG UP signal and causes the setting of flip-flop 300 upon receipt in register 40 of the SOD character. The setting of flip-flop 300 causes the signal on line 318 to go high which in turn causes the path selection control to disable the normal output line 82 and enable delete line 80, thus, causing the removal of the SOD character from the refresh memory.

The delete line 80 remains enabled until such time as the carriage return character CR is recognized in register 40 by the character decoder 30. Thus, as soon as the next CR character is received in register 40, the AND gate 306 is enabled thereby causing the resetting of flip-flop 300. This resetting of flip-flop 300 causes the Q output line to go high thereby causing the setting of flip-flop 302. The setting of flip-flop 302 causes the enabling of gate 308 which also receives the SOD 40 signal from the output line 322 of AND gate 306. The SOD character is then set into the register 40 in place of the carriage return character CR which is presently located therein. Since the flip-flop 300 is reset, the delete path is disabled and the normal path enabled causing the SOD character to be inserted on the next shift pulse into the refresh memory 34. It should be remembered that the CR character immediately preceded the SOD character into the refresh memory on the previous shift pulse via the delete path. The SET SOD 40 signal provided on line 334 is suitably delayed and provided to line 330 which thereby resets flip-flop 302 and completes the page up operation.

It can, therefore, be seen that the page up operation effectively removes the SOD character and provides it directly after the next carriage return character. This means that the page up operation efiectively causes the start of display character to be placed after the next succeeding line of storage of data in the refresh memory 34. It will be remembered that a page up operation is representative of a document being moved upwardly behind the window which represents the display.

The page down and page end commands require that the start of display character be moved to a location which in the case of the page down command is earlier in the refresh memory than its present location. In the page end command, it may also be required that the start of display character be inserted in a position which is earlier in the refresh memory than its present location. In order to accomplish the determination of the location at which the start of display character is to be reinserted, the circuitry which is shown in FIG. 9 is required.

The circuitry in FIG. 9 basically comprises a counter 350, a counter 352, a comparator 354 and AND gates 356, 358, 360 and 362. Counter 350 includes a counting (CT) input line 364 which receives counting signals from AND gate 358 which step the counter 350. The counter also includes input line 366 which is a preset (P) input line to preset the count in the counter 350 to l. Counter 350 also includes a reset (R) input line 368 which resets the counter to all zeroes when an enabling signal is provided on line 368.

Counter 350 also includes an output line 370 which indicates whether the total in the counter is either positive or negative. The count in the counter 350 is provided via lines 372 to the comparator 354. Counter 352 includes a counting (CT) input line 374 which steps the counter 352 each time a positive signal is received thereon from AND gate 356. A reset (R) line 376 is also provided to the counter 352 which causes the counter to be reset to all zeroes when an enabling signal is provided thereon.

A preset (P) input line 378 is also provided to counter 352 which presets the counter to a count of 27 when the line is enabled. Counter 352 also includes an output line 380 which is used to indicate whether the count in counter 352 is negative or positive. The count in counter 352 is provided via lines 382 to comparator354. The comparator 354, in addition to having input lines 372 and 382, includes an output line 384 which has a true or enabling signal (CTR=) generated thereon when the count in counters 350 and 352 are equal.

The output of AND gate 356 is connected to input line 374 of the counter 352. The gate 356 also includes a pair of input lines 386 and 388. Input line 386 is connected to the character decoder 30 which provides a signal on line 386 when the carriage return character CR is located in register 36. The line 388 is connected to the output of the page end logic circuitry and will be discussed in greater detail hereinafter. The output line of AND gate 358 is connected to the count line 364 of the counter 350. The AND gate 358 also includes a pair of input lines 390 and 392. Input line 390 is connected to the output of the character decoder 30 which provides an enabling signal on line 390 when the carriage return character CR is detected in register 36. Line 392 is connected to the output of the page down logic and will also be discussed in greater detail hereinafter.

The output line of AND gate 360 is connected to the preset input line 366 of counter 350. The AND gate 360 includes a pair of input lines 394 and 396. The first input line 394 is connected to the output of the character decoder 30 which provides a high signal on line 394 when the STX character is recognized in register 36. Input line 396 to the AND gate 360 is connected to the output of the page down circuitry. The output line of AND gate 362 is connected to the preset input line 378 of counter 352.

The AND gate 362 includes a pair of input lines 398 and 400. Line 398 is connected to the output of the character decoder 30 and receives an enabling signal when the character STX is located in register 36. Line 400 is connected to the output of the page end circuitry.

As the refresh memory is recirculating, the counter 350 is used -to count the number of lines starting with the start of the text character STX. Each time an STX is located in register 36, the AND gate 360 is enabled to preset the counter 350 to a ---1 via line 366. AND gate 360 is enabled as long as a page down command is weceived by the page down circuitry and, thus, the PGD signal is high and, thus, provides via line 396 an enabling signal to AND gate 360. Therefore, since the start of text character sets the counter to a -l, the counter 350 contains at all times the number which is one less than the number of lines indicated by the number of carriage returns that have reached register 36. As the refresh memory recirculates, each carriage return character received in register 36 causes counter 350 to be stepped as long as the PGD DELETE signal remains high to gate 358.

As the counter 350 is used to maintain the count of the lines less one that have passes through the register 36, counter 352 is used to determine the location where the start of display character is to be re-entered if a page end command is requested. As set forth above, the video display preferably includes 27 lines of characters. Thus, since a page end instruction requires that the SOD character be inserted 27 lines from the end of text (ETX) character, the counter 352 is preset to 27 so that the location of where the start of display character is to be inserted is located in counter 352. That is, in order to locate properly the position of the SOD character in a page end command, the counter 352 is preset to 27 each time the start of text character STX reaches register 36. The STX character continuously presets the counter as long as the page command signal is not received as indicated by the PGE legend adjacent line 400.

It can, therefore, be seen that during an operation other than the page down or page end command at the video display terminal, the two counters 350 and 352 are continuously predeterrnining the number of the line where the start of display character is to be inserted if either of these commands is requested.

The page down logic used in combination with the circuitry of FIG. 9 is shown in FIG. 10. As seen therein, the page down logic comprises a pair of flip-flops 402 and 404 and four AND gates 406, 408, 410 and 412, respectively. The AND gate 406 includes a first input line 414 which receives the page down (PGD) signal from the input-output control 24. The second input line 416 is connected to the Q output line of flip-flop 402.

The output of AND gate 406 is connected via line 418 to the D input of flip-flop 402.

The output line 420 of flip-flop 402 is connected to the path selection control 32 via line 420 and to AND gates 408 and 410 via line 422. The enabling signal on line 420 causes the path selection control to change from the normal to the delete path. The setting of flip-flop 402 also causes line 422 to enable gates 408 and 410. The second input line of AND gate 408 is connected to the output of the character decoder 30 which provides an enabling signal on line 424 when the STX character is received in register 36. The second input of AND gate 410 is connected to line 384 from FIG. 9 which is the output line of comparator 354 which indicates that the counters 350 and 352 are equal. The output line of AND gate 408 is connected to line 376 of counter 352 and the output signal provided on line 376 thereby causes the resetting of counter 352. The output line 426 of AND gate 410 provides a signal which'indicates that the page down command requires the SOD character be inserted in register 38. This signal is delayed one clock time in order to be connected to the clock input line 428 of flip-flop 402 and input line 430 of AND gate 412.

The O output line 432 of flip-flop 402 is connected to the clock input of flip-flop 404. The D input line of flip-flop 404 is connected to a source of positive voltage (+V) and the reset input line receives the page complete (PG COMP) signal for resetting flip-flop 404.

The Q output line 436 of flip-flop 404 is connected to the other input of gate 412. The gate 412 provides an output signal on line 438 which causes the setting of the SOD character in register 40. That is, line 430 is also hardwired to the register 40 for providing the SOD character therein.

The line 438 is also connected to a suitable delay so that the signal can be provided to line 434 of flip-flop 404 to reset flip-flop 404 when the page down operation has been completed and to the input-output control 24 to terminate the PGD signal.

In operation, when a page down signal is received on line 414, AND gate 406 is enabled thereby causing the line 418 to have a high signal thereon so that upon receipt of the SOD character in register 40, flip-flop 402 is set. As soon as flip-flop 402 is set, the Q output line 420 of flip-flop 402 causes the path selection control to be changed from the normal to the delete path. It should be noted that the PGD DELETE signal, which is obtained by inverting the PGD DELETE signal, provided to line 392 in FIG. 9 of AND gate 358 goes low as a result of line 420 going high. Accordingly, no further stepping of counter 350 is possible since the gate 358 is disabled by the low input on line 392.

Thus, the count in counter 350 indicates the line at which the SOD character was previously located minus one. Counter 350, thus, maintains the count of the lines at which the SOD character is to be inserted in order to effect a page down command. The enabling of line 420 of flip-flop 402 also causes the AND gate 408 to be enabled when the STX character is received in register 36. Thus, the receipt of the STX character in register 36 causes gate 408 to be enabled and thereby resets' counter 352 to all zeroes. The counter 352 is reset to all zeroes and is stepped by each of the carriage return characters CR which are received in register 36. Accordingly, when the count in counter 352 reaches the count in counter 350, the comparator 354 indicates on line 384 that the counters are equal which causes AND gate 410 in FIG. 10 to be enabled and thereby provide an output signal on line 426 which is delayed for one clock time and then applied to lines 428 of flip-flop 402 and line 430 of AND gate 412.

The receipt of the high signal on line 428 causes the flip-flop 402 to be reset since the AND gate 406 had been disabled previous thereto by the low signal on the 6 output line of the flip-flop. The resetting of flip-flop 402 causes the signal on line 432 to go high thereby causing the setting of flip-flop 404. The setting of flipflop 404 causes the enabling of AND gate 412 since the signal on line 430 has remained high.

The AND gate 412 provides an output signal on line 438 which causes the insertion of the SOD character into register 40. The suitably delayed signal on line 438 is then provided via line 434 to the reset input of line 404 and resets flip-flop 404. When the PGD DELETE signal goes low as a result of the resetting of flip-flop 402, the path selection control causes the delete path of the recirculation loop of the refresh memory to be disabled and the normal path to be enabled.

It can, therefore, be seen that in the page down operation, the start of display character is moved one line earlier in the refresh memory than its previous location. Accordingly, this has the effect of moving a document down with respect to a stationary viewing window as seen in FIG. 4.

The logic used in combination with the logic of FIG. 9 for the execution of a page end command is shown in FIG. 11. The page end logic utilizes three flip-flops 450, 452 and 454 and four AND gates 456, 458, 460 and 462. The D input line 464 of flip-flop 450 is connected to the output line of input-output control 24 which indicates the receipt of a page end (PGE) command from the data register 22. The clock input line 466 of flip-flop 450 is connected to the output of the character decoder which indicates the receipt of an ETX character in register 40.

Reset (R) input line 468 of flip-flop 450 receives a page complete (PG COMP) signal which indicates the end of the operation of the page end command. The Q output line 470 of flip-flop 450 is connected to the first input of AND gate 456. I"he other input of AND gate 456 is connected to the Q output line of flip-flop 452. The output line 472 of AND gate 456 is connected to the D input line of flip-flop 452.

The clock input line 474 of the flip-flop 452 is connected to the output of character decoder 30 and receives a signal thereon when the character SOD is received in register 40. As will hereinafter be seen, line 474 is also connected via delay means (not shown) to the output of AND gate 460. The Q output line of flipflop 452 is connected via line 476 to the path select control 32 to change the recirculation loop of the refresh memory 34 from a normal path to a delete path and via line 478 to AND gates 458 and 460. The Q output line 480 of flip-flop 452 is connected to the clock input line of flip-flop 454.

A second input line 482 of AND gate 458 is connected to the character decoder 30 which provides a high signal on line 482 when the STX character is recognized in register 36. The second input line of AND gate 460 is connected to output line 384 of comparator 354 in FIG. 9. The output line of AND gate 458 is connected to line 368 in FIG. 9 of counter 350.

AND gate 460 includes an output line 484 which is utilized to indicate that the SOD character should be located within the register 38. This signal is delayed one clock time and then applied to line 474 of flip-flop 452 and to an input line 486 of gate 462. The second input line to gate 462 is connected via line 488 to the Q output line of flip-flop 454.

Gate 462 is connected via output line 490 to the register 40 and the code for the SOD character is hardwired therein to enable the insertion of the code for the SOD character in register 40 when gate 462 is enabled. The signal on line 490 is delayed a suitable period of time for the transient signals to be quiescent and then applied via line 492 to the reset input of flip-flop 454. The D input of flip-flop 454 is connected to a positive voltage source (+V).

In operation, the page end (PGE) signal being provided by the input-output control 24 is received at the D input of flip-flop 450. Upon the receipt of the ETX character in register 40, the flip-flop 450 is set. The setting of flipflop 450 causes the Q output line 492 which is connected to line 388 in FIG. 9 to go low thereby causing the disabling of AND gate 356 therein.

The disabling of AND gate 356 causes the count in counter 352 to be fixed at the count which indicates the number of lines between STX and ETX minus 27. This, of course, is the number of lines from the start of text that the SOD character should be inserted so that a page end command can be executed.

The setting of flip-flop 450 also enables gate 456 which in turn causes the line 472 to have a high signal placed thereon so that the receipt of the start of display character in register 40 causes the setting of flip-flop 452. The setting of flip-flop 452 causes a high signal on line 476 which enables the delete operation of the SOD character by changing the recirculating path in the refresh memory from the normal path to the delete path.

The setting of flipflop 452 also causes the enabling of AND gate 458 and 460 so that upon the receipt of the STX character in register 36, AND gate 458 is enabled and thereby causes the resetting of counter 350. Counter 350 is then set to all zeroes and then is stepped by the receipt of CR characters in the register 36. When the count in counter 350 reaches the count in counter 352, comparator 354 indicates this condition by generating a CTR= signal on line 384 indicating that the two counters have an equal count which causes AND gate 460 in FIG. 11 to be enabled and, thus, provide an output signal on line 484 indicating that the SOD character should be in register 38. This signal is then delayed one clock time and provided via line 474 to the flip-flop 452 which causes the resetting of flipflop 452 as the output signal on line 472 is made low by the disabling output signal on the O output of flip-flop 452 when the flip-flop 452 was set.

The resetting of flip-flop 452 causes the setting of flip-flop 454 which in turn enables the AND gate 462. When AND gate 462 is enabled, the SOD character is inserted in register 40 and the signal on line 490 is then suitably delayed and provided as a PG COMP signal via line 492 of flip-flop 454 to reset the same. The PG COMP signal is also provided via line 468 to reset flipflop 450.

It should be noted that in each of the logic circuits which are used to execute the various paging commands, the PG COMP signal is also provided to the input-output control 24 in FIG. 1 to terminate the generation of the command signals.

It can, therefore, be seen that a new and improved video display terminal with automatic paging has been provided. The refresh memory used in the video display terminal is a recirculating memory with intermittent clock control. The organization of the data within the refresh memory enables substantially percent) use of the refresh memory storage capability. Moreover, the edit and page control enables the entire contents of the refresh memory to be displayed on the video display.

Moreover, the paging commands are easily executed and are a very powerful tool of the operator to have access to each portion of the refresh memory that is desired.

The keyboard of the video display terminal is also so chosen that the page up and page down buttons may be continuously depressed until the number of lines up or down in the refresh memory that are desired can be accomplished without intermittently pressing the page up or page down buttons. The page start, form feed and page end commands accomplish a very rapid removal of the start of display character from one position to a predetermined position in the refresh memory. These commands are accomplished rapidly by means of the logic circuitry utilized for the execution of each of the circuits.

Without further elaboration, the foregoing will so fully illustrate my invention that others may, by applying current or future knowledge, readily adapt the same for use under various conditions of service.

What is claimed as the invention is:

, 1. In a video display terminal having a refresh memory, a character generator and a display means wherein said refresh memory is utilized to enable said character generator to provide signals to said display means for displaying characters, the codes of which are stored in said refresh memory, said refresh memory having stored therein a plurality of contiguous lines of characters larger than the number of lines which can be simultaneously displayed on said display, means responsive to said refresh memory for enabling the display of a selected plurality of lines of characters from said refresh memory in said display means, and said means responsive including selection means for changing the selected contiguous lines from said refresh memory which are displayed in said display means.

2. The video display terminal of claim 1 wherein said refresh memory comprises a recirculating register.

3. The video display terminal of claim 2 wherein said recirculating register is connected by a return loop, said return loop having means for shortening and lengthening the recirculation path so that characters in said refresh memory can be inserted and deleted.

4. The video display terminal of claim 1 wherein control characters are provided in said refresh memory for indicating the end of a line of data so that all of said characters in said refresh memory are sequentially stored in said refresh memory.

5. The video display terminal of claim 4 wherein control characters are provided in said video display terminal for defining the start of the characters stored in the refresh memory, the start of the display portion of the characters stored in said refresh memory and the end of the characters stored in said refresh memory.

6. The video display terminal of claim 5 wherein said terminal includes control means for removing said character representative of the start of the characters to be displayed from one position and returning it to another position within said refresh memory.

7. The video display terminal of claim 6 wherein said control means comprises means for recognizing said start of display character when it is positioned in a predetermined portion of said recirculation path, means responsive to said control means for shortening the recirculation path whensaid start of display character is determined, maintaining said shortened path until such time as the desired position in said refresh memory for said start of display character is located in said recirculation path and lengthening said recirculation path at the desired position for insertion of said start of display character.

8. The video display terminal of claim 6 wherein said control means further include counting means for counting the number of end of line characters that pass through said recirculation path, said counting means including a pair of counters, the first of said counters being maintained at a count which enables the start of display character to be placed one line earlier in said refresh memory and a second counter being maintained at a count to enable the determination of the place ent f the tart of displa c aracter a p redet rme num rof mes 1n sai re res memory romt e control character for the end of the characters in the display memory.

9. The video display terminal of claim 1 wherein said terminal further includes a line bufier register, said line buffer register being utilized to address the character generator for displaying a line of characters on the display means.

10. In a video display terminal, a recirculating register having a variable length recirculation path, said recirculating register having stored therein the coded representation of a plurality of data characters and control characters, said control characters including a first character which indicates that each of said data characters in a predetermined plurality of rows of 7 characters immediately following said first character are to be displayed, means responsive to said recirculation path for determining the presence of said first character therein, said means responsive including means for shortening said recirculation path to remove said first character and means for restoring the length of said recirculation path to reinsert said first character in a different portion of said recirculating register with respect to the data characters and control characters stored therein.

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Classifications
U.S. Classification345/471
International ClassificationG09G1/02, G09G5/42
Cooperative ClassificationG09G1/02, G09G5/42
European ClassificationG09G1/02, G09G5/42
Legal Events
DateCodeEventDescription
Jul 29, 1983AS17Release by secured party
Owner name: DELTA DATA SYSTEMS CORPORATION, TREVOSE, PA., A PA
Owner name: PHILADELPHIA NATIONAL BANK, THE :
Jul 29, 1983ASAssignment
Owner name: DELTA DATA SYSTEMS CORPORATION, TREVOSE, PA., A PA
Free format text: RELEASED BY SECURED PARTY;ASSIGNOR:PHILADELPHIA NATIONAL BANK, THE;REEL/FRAME:004152/0845
May 22, 1981AS17Release by secured party
Owner name: DELTA DATA SYSTEMS CORPORATION, 2595 METROPOLITAN
Owner name: FIRST PENNSYLVANIA BANK N.A.
Effective date: 19810514
May 22, 1981ASAssignment
Owner name: DELTA DATA SYSTEMS CORPORATION, 2595 METROPOLITAN
Free format text: RELEASED BY SECURED PARTY;ASSIGNOR:FIRST PENNSYLVANIA BANK N.A.;REEL/FRAME:003853/0497
Effective date: 19810514
May 18, 1981AS06Security interest
Owner name: DELTA DATA SYSTEMS CORPORATION
Effective date: 19810514
Owner name: PHILADELPHIA NATIONAL BANK.THE, THE PHILADELPHIA N
May 18, 1981ASAssignment
Owner name: PHILADELPHIA NATIONAL BANK.THE, THE PHILADELPHIA N
Free format text: SECURITY INTEREST;ASSIGNOR:DELTA DATA SYSTEMS CORPORATION;REEL/FRAME:003853/0434
Effective date: 19810514