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Publication numberUS3683415 A
Publication typeGrant
Publication dateAug 8, 1972
Filing dateNov 9, 1970
Priority dateNov 13, 1969
Also published asDE2055999A1, DE2055999B2
Publication numberUS 3683415 A, US 3683415A, US-A-3683415, US3683415 A, US3683415A
InventorsJohn David Letheren, John George Lloyd
Original AssigneeSumlock Anita Electronics Ltd
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Calculating machines
US 3683415 A
Abstract
A calculating machine is disclosed employing interconnected integrated circuit. The integrated circuits are so arranged to minimize circuit connections therefrom comprising for example three single connections. This is achieved by means of gates within the integrated circuit chip and multiplexer which is operated from an external oscillator.
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Description  (OCR text may contain errors)

United States Patent 147 C, 340/147 CN,150, 318,413; 179/15 BS; 178/50, 69.5 R, 69 F, 69 G; 307/208, 213, 24]; 328/63, 72, 75, 201, 206

INTEGRATED CIRCUIT CONTAINER MULTIFLEXER Lloyd et al. Aug. 8, 1972 [54] CALCULATING MACHINES [56] References Cited [72] Inventors: John George Lloyd; John David UNITED STATES PATENTS Letheren, both of Uxbridge, Enl d 3,516,089 (3/1 970 Cooper ..340/4 1 3 3,384,873 5/l968 Sharma .340/147 X [73] Assgneeg i i Z": 3 3,308,434 3/1967 (ilasson etal ..l78/69.5X E x 3,402,404 9/1968 Burley etal .340/413 x 3,461,245 8/1969 Johannes et al. ..l78/50 x [22] Filed: Nov. 9, 1970 3,476,878 I l/l969 Oshima et al .il78/5O [21] Appl' 87898 Primary Examiner-Eugene G. Botz Assistant Examiner.lerry Smith [30] Foreign Application Priority Data Atmrney -Laurence R, Brown Nov. 13, 1969 Great Britain ..55 ,599/69 May 15, 1970 Great Britain ..23,612/70 [571 ABSTRACT I A calculating machine is disclosed employing inter- US. Cl- C, connected integrated circuit The integrated circuits [51] Int. Cl. ..H04q 9/04 are so arranged to minimize circuit connections Fieldofsealch 147 SY, therefrom comprising for example three single connections. This is achieved by means of gates within the integrated circuit chip and multiplexer which is operated from an external oscillator.

14 Claims, 17 Drawing Figures MULTIPLEXER INTEGRATED CIRCUIT CONTAINER PATENTEDMJ: smz 3.683.415

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CALCULATING MACHINES This invention has reference to calculating machines and has particular reference to electronic calculating machines embodying integrated circuits.

Electronic calculating machines have been marketed for several years. These machines originally included traditional electronic components. Subsequently some of these components were replaced by or used in conjunction with printed circuits and more recently these calculating machines have included integrated circuits. The integrated circuits, or chips as they are sometimes called, may be manufactured inexpensively but these chips have to be housed in suitable cans or containers so as to form integrated circuit packages and consequently connections have to be made within the containers between the circuits in the integrated circuit chips and the terminal leads on the outside of the containers so that connections can be made to other circuits of the calculating machine. These connections between the integrated circuit chip and the exterior of the integrated circuit container. are made by using a plurality of wires during the manufacture of the circuit in the container. During subsequent assembly of the calculating machine, connections have to be.v made from the terminal leads leading out of the integrated circuit container to other circuits of the calculating machine. The terminal leads and the cost of connecting such' terminal leads constitutes a relatively high percentage of the total cost of the integrated circuit part of the calculating machine because the cost of the package increases greatly as the number of terminal leads increases. Also, the size of each terminal lead necessary for robustness in use puts a limit on the number of terminal leads that can be connected to the chip of a given size so that, in order to exploit the reduction in circuit size which is possible with integrated circuits, the smallest possible number of terminal leads is desirable.

Where several integrated circuit packages are connected together to form a complete circuit, the number of terminal leads required to transmit signals between the circuits may rise to a very large number so that the integrated circuit packages used to form the complete circuit are expensive. Also, where several integrated circuit packages are connected together to form a complete circuit, it is necessary to synchronize the operation of the various integrated circuits by means of synchronizing signals.

It is an object of the present invention to provide a calculating machine embodying improved connections for the integrated circuits in such calculating machine.

According to the present invention there is provided a calculating machine including two integrated circuits which are connected to a source of oscillator pulses and which are connected together by a signal linefor the transmission of signal pulses there-between, each integrated circuit having plurality of pulse lines each of which connects a respective point on the integrated circuit to a common connection of the signal line through the conduction connections of a respective switch means, a counter circuit having a plurality of outputs each of which is connected to control connection of a respective switch means, and means for synchronizing the outputs of the counter circuit in the integrated circuit with the outputs of the counter circuit in the other integrated circuit; whereby, the synchronizing means causes the outputs of the counter circuits to be energized in a synchronized sequence so that the switch means in the respective integrated circuits are sequentially energized to connect the sequence the pulse lines in the respective integrated circuits to the signal line.

According to one aspect of the present invention a calculating machine includes a pair of integrated circuits between which signals are passed, each circuit including a plurality of gate parts and a plurality of circuit parts, the gate parts being adapted to be controlled by a respective predetermined time pulse to control the entry of received signals into the receive integrated circuit.

According to another aspect of the present invention there is provided a calculating machine including means for transmitting a signal from one integrated circuit to another integrated circuit along a single wire comprising a transmit circuit and a receive circuit, the transmit circuit having a transmitregister having a plurality of stages, a gate associated with each stage of the register to which gates a plurality of signals are addressed, means for applying a train of pulses to the register to apply pulses to the gates in sequence to open said gates in sequence and apply the signals applied to said gates to a signal line; and wherein there is included an additional gate to apply a signal to the signal line in alternate of the train of signals and the receive circuit having a receive register having a plurality of stages and a gate associated with each stage of the register to which gates the signals received from the single. wire are addressed, a pair of alternately operable input gates to the receive register to apply pulses to the receive register; whereby, if the signals are in synchro'nism the pulses are passed to the receive integrated circuit, but, on receipt of unsynchronous signals, the pulses are delayed until the two trains of pulses are in synchronism.

The switching means in the integrated circuits are preferably metal-oxide silicon (m.o.s.) switching transistors which have a control electrode and two conduction electrodes and which have the property that, when a negative potential is applied to the control electrode a short circuit exists between the two conduction electrodes, and, when a positive potential is applied to the control electrode, an open circuit exists between the two conduction electrodes.

The source of oscillator pulses is preferably an output from an oscillator connected to an input of the counter circuits The counter circuits are preferably in the form of ring counters.

The synchronizing means included in one of the integrated circuits preferably forms a synchronizing circuit including a nor gate circuit having an input connectedto one output of the counter circuit and having the output of the nor gate circuit connected by a pulse line to the common connection of the signal line through a switch means whose control connection is connected to the output of the counter circuit of the one integrated circuit. Another input of the nor gate circuit is connected to the output of a divide-by-two bistable circuit whose input is connected to another output of the counter circuit so that the synchronizing signal from the output of the nor gate circuit alternates between two voltage magnitudes, when the one output of the counter circuit is successively ener- .gized.

The synchronizing means included in the other of the integrated circuits preferably forms a synchronizing circuit including a nand gate circuit, a one nor gate circuit and another nor gate circuit whose input is connected to the output of the one nor gate circuit. The outputs of the nandgate circuit and the other nor gate circuit are connected together as the output connection through the conduction connections of a switch means to an input of the counter circuit of the other integrated circuit. The control connection of the switch means is connected to a first output of the counter circuit, which first output corresponds to the first output of the counter circuit in the one integrated circuit. The output of a divide-by-two bistable circuit are connected to an input of the one nor gate circuit and the nand gate circuits respectively. The input of the bistable circuit is connected to a second output of the counter circuit, which second output corresponds to the second output of the counter circuit of the other integrated circuit.

When the synchronizing circuit in the other integrated circuit receives the synchronizing pulses from the synchronizing pulses of the one integrated circuit, the other integrated circuit transmits a signal which depends on whether the logic level of the synchronizing pulse is the same as the logic level of the bistable circuit output. While the logic levels are the same, the output connection of the synchronizing circuit allows the counter circuit to operate; and, while the magnitudes are different, the output connection of the synchronizing circuit prevents the counter circuit from operating. The counter circuit of the other integrated circuit has a delay or delays in its operation, as a result of the action of its synchronizing circuit, until the counter circuits are in synchronism, when no further delays in operation occur.

A train of synchronizing pulses is generated in the synchronizing means in one of the integrated circuits during the time that the first counter circuit output in the synchronizing means is energized. These synchronizing pulses are transmitted along the signal line to the input of the synchronizing means of the other integrated circuit to ensure that the first counter outputs connected to the synchronizing means of the one and the other integrated circuits are energized in synchronism and, as a result, that the other counter circuit outputs also are energized in synchronism.

Constructional embodiments will now be described, by way of example, only with reference to the accompanying drawings, wherein:

FIG. 1 shows a block schematic diagram of two integrated circuits situated within respective containers and connected together by three single connections for the transfer of pulses between the integrated circuits;

FIG. 2 shows part of the container and part of the integrated circuit shown in the left-hand side of FIG. 1 and connected to the topmost single line;

FIG. 3 shows part of the container and part of the integrated circuit shown in the right-hand side of FIG. 1;

FIG. 4 shows a plurality of pulses employed in a second embodiment of a calculating machine;

FIG. 5 shows in greater detail some of the pulses shown in FIG. 4;

FIG. 6 is a diagrammatic representation of part of the circuit of the second embodiment of a calculating machine;

FIGS. 7. and 8 shows in greater detail part of the circuit shown in FIG. 6;

and FIG. 9 shows in tabulated form the sequence of signals supplied through the circuits shown in FIGS. 7 and 8.

As shown in FIG. 1, a pair of containers 2 and 4 which are, for example, in the transistor T05 configuration, contain the one and the other integrated circuits 6 and 8 respectively. The integrated circuits 6 and 8 each have eighteen pulse lines which form input or output lines and which are actually within the integrated circuits concerned, and which are grouped into three groups each of six lines 10,12 and 14 and 10', 12' and 14 in the containers 2 and 4 respectively. The corresponding groups of lines 10 and 10' 12 and 12' and 14 and 14 are connected to sets of gates 11 and 11, 13 and 13, 15 and 15' respectively hereinafter described and the groups of lines 10 and 10', 12 and 12', and 14 and 14' are connected together by the signal lines 16, 18 and 20 respectively. The number of inputs in one group of lines is equal to the number of outputs in the group of lines at the other end of the single line and vice versa.

In the container 2, a master multiplexer 22 has an input line 24 which is connected to the output of an oscillator 26 for the receipt of oscillator pulses GD. The master multiplexer 22 has eight output lines 27 and a synch. output 27a. Six of the output lines 27 are connected to the lines of the group of lines 10,12 and 14 respectively as hereinafter described. The seventh of the output lines of the master multiplexer 22 is connected as a seventh pulse line to the set of gates 11 and the eight of the output lines of the master multiplexer 22 is connected as an eighth pulse line to the set of gates 11 and as a seventh pulse line to the sets of gates 13 and 15 respectively. The six of the output lines of the master mixer 22 are connected to the respective control electrodes, or connections, of switch means in the form of metal-oxide-silicon (M.O.S.) switching transistors which are actually formed in the integrated circuit concerned, and which have conduction electrodes, or connections, which are connected in series with the respective input/output pulse lines of the groups of lines 10,12 and 14. Each of the six output lines of the master multiplexer 22 are connected to the control electrodes of the switching transistor of one of the pulse line of each of the groups of line 10, 12 and 14. The interconnections between the output lines of the master multiplexer 22 and the input/output pulse lines of the groups of lines 10, 12 and 14 are described later in greater detail.

Similarly, in the container 4, a slave multiplexer 28 has an input line 30 to the output of the oscillator 26 for the receipt of oscillator pulses GD. The slave multiplexer 28 has seven output lines 27'; six of the output lines 27' are connected to respective input/output pulse lines connected to the integrated circuit 8 in a similar manner to the six output lines of the master multiplexer 22. Seventh output line 27' of the slave multiplexer 28 is connected as the seventh pulse line in the group of lines 10, 12' and 14' and the sets of gates 11', 13 and 15'. An output line 27a of the slave multiplexer 28 is connected as the eighth line connected to the set of gates 11. The output line 27a is an input to the slave multiplexer 28 and transmits the synchroniznor gate circuits which for the inputs A and B give the output C shown in the Following table where logic l is Ve, and logic 0 is Ve.

TABLE 1 B C If the input is A only, the input B,

which is not connected, is equivalent to an input B =0 at all times, i.e., a single-input nor' gate circuit acts asaninvertercircuit.

The master multiplexer 22 also includes a plurality of nand gate circuits which for the inputs A and B give the output C shown in the following table 2, where logic 1 is negative and logic 0 is positive as before.

TABLE 2 In the master multiplexer 22, the square wave oscillator pulses GD are transmitted along the line 24 to give a direct output, 0 and, through a nor gate circuit 50, to give an inverted output 0 The outputs 0 and 0, are applied to the control electrodes of four metal oxidesilicon (M.O.S.) switching transistors 51 to 54 whose conduction electrodes are connected in series with five nor gate circuit 55 to 59 to form a closed-loop counter or register. The respective outputs of the four nor gate circuits 56 to 59 are connected to respective nor gate circuits 60 and 63 to give the outputs A,A;B,B;C,C; and D,;. The M.O.S. switching transistors 51 to 54 have the property that a negative voltage applied to a control electrode creates a short-circuit between the conduction electrodes and a positive voltage applied to a control electrode causes the creation of an open-circuit between the conduction electrodes.

Thus the sequential application of the outputs {6 and a: to the closed-loop counter circuit formed by the M.O.S. switching transistors 51 to 54 and the nor gate circuits 55 to 59 causes the following truth table shown in table 3 to be followedby the outputs of A, B, C and D. The outputs slot and decode will be explained later.

In the top line of the truth table if the M.O.S. transistors 51 and 52 connected to the output 0, are in the open-circuit condition, the M.O.S. transistor 52 and 54 connected to the output 0; are in the short-circuit condition. If the output D is equal to 1, then the output C is equal to 0. If it is assumed for the moment that B is equal to 1, then A is equal to 0 as initial conditions. The successive operations of the outputs 0 and 0g cause the outputs A, B, C and D to follow the table shown and after eight changes return to the initial condition. These eight changes of output are repeated sequentially and are labelled slots 1 to 8 as shown. The decode column in the table are the outputs which identify the slots and these outputs are applied to the pairs of nand' and nor gate circuits and 71, 72 and 73, 74 and 75, 76 and 77, 78 and 79, 80 and 81, and 83 and 84 and 85 which are connected to the slot output lines marked 1 to 8 respectively. The slot output lines 1 to 3 and 5 to 8 are connected to the respective control electrodes of the M.O.S. switching transistors 90, 91, 92, 93, 94, and 96 which are connected to corresponding input/output pulse lines 1 to 3, 5 to 7 and synch respectively. The output lines 1' to 3 and synch are connected together to the input of a nor gate circuit 97 which is connected through a M.O.S. switching transistor 98 to a common connection of the signal line 16. The input of the nor gate circuit 97 is also connected to one of the conduction electrodes of a pair of M.O.S. switching transistors. 99 and 100 respectively whose other conduction electrodes are connected to a negative voltage -Vdd and whose control electrodes are connected to the slot output line 8 and slot output line 4 respectively. The three input pulse lines 5, 6 and 7 are connected to the output of a hor gate circuit 101 whose input is connected to the common connection to the single line 16.

The output of the nand gate circuit 84 of the slot output line 8 is connected to an input of a nor gate circuit 106 whose output is labelled synch. The synch output is connected to one of the conduction electrodes of the M.O.S. switching transistor 96 which 5 is controlled by the slot output line 8. The other input of the nor gate 106 is connected to the output of a divide-by-two bistable circuit 108 whose input is connected to the output B of the nor gate circuit 61. The circuitry previously described is a synchronizing circuit for generating a synchronizing pulse, or synch pulse, when the slot output line 8 is energized. The successive synch pulse alternates between a positive magnitude (logic 0) and a negative magnitude (logic 1), when slot 8' is successively energized as described later. The synch' pulse is transmitted along the signal line 16 to ensure that the slot output lines 1 to 8 in the master multiplexer 22 and the slave multiplexer 28 are energized in synchronism as described hereinafter.

The FIG. 3 shows the slave multiplexer 28, part of the integrated circuit 8, the group of lines 10', and the set of gates 11 which are connected to the single line 16. Those parts of the circuits shown in FIG. 3 which are identical to those shown in FIG. 2 have the same reference number with the addition of a dash. The circuits shown in FIG. 3 are identical to the circuit shown in FIG. 2 apart from two differences. The first difference is that the pulse lines 1, 2 and 3 are output lines in FIG. 2 and are input lines in FIG. 3; while the pulse lines 5, 6 and 7 are input lines in FIG. 2 and are output lines in FIG. 3. The second difference is that there is a synchronizing circuit connected between the input of the nor gate circuit 101' and the input of the nor gate circuit 55 for synchronizing the slot output lines 1 to 8 of the master multiplexer 22 and the slave multiplexer 28.

The synchronizing circuit includes a two-input nand gate circuit 120 and a two-input nor gate circuit 121 which each have an input connected to the input of the nor gate circuit 101'. The nor gate circuit 121 is connected to a nor gate 123. A divide-by-two bistable circuit 124 has an output connected to the other inputs of the nand gate circuit 120 and the nor gate circuit 121 and has an input connected to the output B of the nor gate circuit 61. The outputs of the nand gate circuit 120 and the nor gate circuit 123 are connected together to form a common output of the synchronizing circuit which output is connected through the conduction connections of a M.O.S. switching transistor 126 to an input of a nor gate circuit 55'. The control conductor of the switching transistor 126 is connected to the nor gate circuit 85' which is the slot output line 8.,

The synchronizing circuit operates as follows:

When the oscillator pulses GD from the oscillator 26 are applied to the master multiplexer 22, the slot output lines 1, 2, 3, 5, 6 and 7 are energized during the corresponding slot times in the sequence shown in the truth table of table 3 so as to connect in sequence the pulse lines 1, 2, 3, 5, 6 and 7 of the groups of lines 10, 12 and 14 to the signal lines 16, 18 and 20 respectively. The slot output line 4 is energized at slot 4 time in its correct place in the sequence to transmit a negative voltage to the control electrode of the switching transistor 100. The short-circuit condition of the switching transistor 100 is created to apply the negative voltage -Vdd to the output pulse lines 1, 2 and 3 to ensure that the remains of any data passing along these pulse lines from the integrated circuit when the 3 pulse line were energized at slot 3 time is prevented from interfering with the information on the input pulse lines 5, 6 or 7. The output line 8 is energized at slot 8 time to put the switching transistors 96 to and 99 into the short-circuit condition. The output of the hand gate circuit 84, which output is the logic at slot 8 times is an input of the nor gate circuit 106; the other input of the nor gate circuit is the output of the divide-bytwo bistable circuit 108 which output according to the truth table shown in table 3, alterrlates between logic 0 and logic I when the slot output line 8 is successively energized. Thus, the output of the nor gate circuit 106, which is the synchronizing pulse output, alternates as previously described and the alternating synchronizing pulses are transmitted through the switching transistor 96 to the input of the nor gate circuit 97. The input of the nor gate circuit 97 trys to go to a potential of -Vdd, i.w. a logic 1, because the switching transistor 99 is in the conducting condition; however, the voltage of the synchronizing pulse output from the nor gate circuit 106 determines the actual voltage level of the input to the nor gate circuit 97. If the synchronizing pulse is at logic 1 when the input to the nor gate circuit 97 is logic l and if the synchronizing pulse is at logic 0 the input to the nor gate circuit 97 goes to logic 0 despite the effect of the logic I signal from the switching transistor 99. The alternating synchronizing pulses applied to the input of the nor gate circuit 97 are applied to the signal line 16 through the nor gate circuit 97 and the switching transistor 98, which both act to invert the synchronizing pulses.

The train of synchronizing pulses alternating between logic 0 and logic l are transmitted along the signal line 16 and is applied to the inputs of the nor gate circuit 101, and 121 the nand gate circuit and the switching transistor 98. The effect of lack of synchronism between the synchronizing pulse of the master multiplexer 22 and the slot 8 output line of the slave multiplexer 28 upon the operation ,of the nor gate circuit 97, 97, 101 and 101' and the switching transistors 98 and 98' is complicated. Because of the complicated effect and because the other circuits need not be described for an understaing of the synchronizing operation, only the effect of the synchronizing pulse upon the nand gate circuit 120 and the nor gate circuits 121 and 123 is described. The nand gate circuit 120 and the nor gate circuits 121 and 123 receive alternate logic 0 and logic l synchronizing signals on one of their inputs and their other inputs receive a logic 0 or logic l from divide-by-two bistable circuit 124. The resultant truth table for the inputs of the nand' gate circuit 120 and the nor gate circuit 121 and the common output of the hand gate circuit 120 and the nor gate circuit 123, which output is the output connection of the synchronizing circuit, is shown as Table 4.

TABLE 4 by 2' Mind nor synch pulse bistable output gate 120. gate 121.

0 0 l l 0 l l 0 l 0 1 0 l l O 0 nor common gate 123 output 0 0 l l l l l 0 Because of the loading of the gate circuits 120 and 123 the effect of a simultaneous logic l and logic 0 at the common output is to cause the common output to go to logic 0. Thus, the common output is at logic 0 when the inputs to the nand gate circuit 120 and the nor gate circuit 121 are all the same, and the common output is at logic l when the inputs are not the same.

When initially turned on, the slot output lines of the master multiplexer 22 and the slave multiplexer 28 are energized in a random relationship. The master multiplexer 22 is free running and consequently transmits a synchronizing pulse along the signal line 16 every time the slot output line 8 is energized, as previously described. The slot output lines of the slave multiplexer 28 are energized in sequence by the master oscillator 26 until the slot output line 8 is energized, when the control electrode of the switching transistor 126 allows the signal of the common output, i.e., output connection of the synchronizing circuit, to be transferred to one input of the nor gate circuit 55'. If the output connection of the synchronizing circuit is at logic 1 signal, then this output is transferred to the input of nor gate circuit 55. Then the output of the nor gate circuit 55 remains at logic whether either a logic l or a logic 0 is applied to the other input of the nor gate circuit 55'. In other words, a logic l on the output connection of the synchronizing circuit blocks the operation of the nor gate circuit 55' so that the counter circuit of the slave multiplexer 28 remains with the slot output line 8 energized. When a logic 0' signal appears on the output connection of the synchronizing circuit, the counter circuit energizes the slot output line 1 and so on according to Table 3 until the slot output line 8 and the switching transistor 126 are energized again. If the output of the synchronizing circuit is at logic l, the counter circuit of slave multiplexer 28 again waits untli this output connection is at logic 0. After a few cycles of the counter circuits of the master and slave multiplexers, the two multiplexers reach the synchronized state in which the slot output line 8 of the slave multiplexer 28 is energized in coincidence with a logic 0 at the output connection of the synchronizing circuit and the operation of the counter circuit of the slave multiplexer 28 is no longer halted by the synchronizing circuit.

The M.O.S. switching transistors 98', 99' and 100' and the nor gate circuit 97 in the slave multiplexer 28 are operated by the slot output lines 4 or 8 in an identical manner to that previously described with respect to the MOS. switching transistors 98,99 and 100 and the nor gate circuit 97 in the master multiplexer 22. I

The circuits previously described operate so that the input or output pulse lines connected to corresponding slot output lines of the master multiplexer 22 and the slave multiplexer 28, when operating in synchronism, are sequentially and continuously energized to send signals between the integrated circuits 6 and 8 along the signal lines 16, 18 and 20.

The number of signal lines between the integrated circuits may be one or more.

The number of integrated circuits that may be interconnected by a signal line may be two or more.

The number of input or output pulse lines connected to a common connection of a signal line may be two or more.

The whole circuit within the containers 2 and/or 4 may be formed into a single integrated circuit of any shape or circuit layout.

The main advantage of the invention is to allow a synchronizing signal to be sent between two integrated circuits in the same direction as the other signals between the two integrated circuits. Since the gate circuits used in the integrated circuits can only be at logic 0 or logic I, in order that the synchronizing signal may be readily identified by the synchronizing circuit of the slave multiplexer 28, the synchronizing signal is generated so as to alternate between logic 0 and logic I when the slot output line 8 of the master multiplexer 22 is successively energized. The possibility of synchronizing the slave multiplexer 28 with data pulses rather than the synchronizing pulse originating from the master multiplexer 22 is avoided by using the alternating logic 0' and logic 1 pulse pattern for the synchronizing pulse because this alternating signal pattern is never generated by any other data pulse source.

This ready identification of the synchronizing pulse allows a system to be constructed with the signals going down the signal lines in both directions. This is an important advantage in the construction of practical systems using several M.O.S. integrated circuits and a large number of signals. v v

Referring to FIG. 4 of the drawing there is shown a first pulse GD, which comprises a master clock signal pulse used in a calculating machine. Such a calculating machine, may, for example, be of the kind described in British Pat. Specification No. 1042785. In such a calculating machine aclock pulse GD (FIG. 4(b) is applied to a decade counter circuit and this circuit emits a respective pulse P0, P1 P9, as shown in FIG. 4(0), (d) and (e) respectively, each having a time interval equivalent to a single GD pulse. Such a decade counter circuit may be of the kind described in British Pat. Specification No. 1130011. Each P9 pulse is used to generate a 9s pulse (shown in FIG. 4 (I) which is applied in turn to a further count-up-to-lO circuit (not shown) whereby a further train of pulses T1 T2, T3 T10 is emitted as shown in FIG. 4 (g), (h), (i) each one of the pulses T1, T2, T3 T10 having a time interval corresponding to the time interval of 10 GD pulses.

The present invention utilizes a pulse train of which the positive part of each GD pulse (and of the Pulses P0 P9) is sub-divided into a plurality (say 7) GDi pulses (as shown at FIG. 4 (a). The GD and GDi pulses are shown enlarged at FIGS. 5 (a) and 5 (b) respectively.

The calculating machine to which the present invention is applied may be of the kind embodying a dynamic register which register includes a plurality of integrated circuits sometimes referred to as chips. These chips include a plurality of layers of material supplied in sequence and in a predetermined pattern to the chip to represent an electric circuit. Such a circuit may consist of for example capitors, transistors etc. In making connections between one chip and another in the circuits of the calculating machine it is necessary to connect the chips by connecting wires and to pass signals from one chip to another along such connecting wires such signals being in the form of pulses representing a binary coded signal. Such binary signals are made up of a section of marks (that is passage of current) or spaces (that is no current flowing). As shown in FIG. 6 of the drawings there is represented diagrammatically a first chip and a second chip 132 the chips being connected by a connecting lead 133. Each of the chips 130 and 132 includes a time pulse division multiplex circuit shown diagrammatically as 134 and respectively. If one considers the chip 130 as being a transmit circuit and the chip 132 the receive circuit a plurality of signal lines S1, S2, S3, S4, S5, S6 are passed to the time division multiplex circuit 134 together with a timing pulse line T and these are passed in turn through the connection 133 to the time pulse multiplex circuit 135 associated with the chip 132. It is arranged that the timing divisional multiplex circuits 134 and 135 operated in sychronism (as will be hereinafter described). Furthermore it is arranged that the transmit division multiplex circuit 134 addresses each of the signal lines S1 to S6 in turn so that a representation of each of these signals in turn is passed along the line 133 to the time division multiplex circuit 135 in turn serves to pass a representation of the signals received to the circuits which are intended to receive such signals. These are represented by the lines S1 S6 on the chip 132. A timer circuit T serves to ensure that the time division multiplex circuit 134 remains in time with the time division multiplex circuit 135.

Referring to FIG. 7 of the drawings there is shown I the transmit time pulse division circuit or synchronizing circuit. On FIG. 7 there is shown a dynamic register or counter 140 which has seven count stages 141 to 147 respectively. The seven stages of the register 140 are supplied with a series of 7 GDi pulses from a pulse train of GD pulses of which the individual GD pulses are subdivided into a pulse train GDi as shown in FIG. 4 (a) and (b) and FIG. (a) and (b) from a pulse generator 148. The pulses GDi from pulse generator 148 are connected to the shift input of the register 140 to cause a train of seven GDi pulses to be applied to the stages register 140 so that the output from the stages 141 to 147 of the register 140 may be passed along the respective output lines 151 to 157 and along the lines 161 to 166 which are connected to the lines 151 to 156 respectively. The lines 151 to 157 are connected to an input of the two-input and logic gates 171 to 177 respectively. The gates 171 to 177 have outputs 181 to 187 to the input of a seven-input or logic gate 188 whose output is connected to the line 133. The lines 161 to 166 are connected to the respective inputs of a six-input nor gate 170 whose output line 178 is connected to the input of the register 140. The operation of the nor gate 170 is such that all of the inputs 161 to 166 of the gate 170 must be at logic 0, which is earth or negative potential, before a logic 1, which is positive potential, appears at the output of gate 170. If a logic 1 appears on an input gate 170, the output of the gate 170 becomes logic 0. Thus if the register stages 141 to 146 are cleared to logic 0, a logic 0 will appear at the output of gate 170 and successive shift pulses will transfer this logic l successively to the stages 151 to 157 and transfer logic 0 signals behind the logic l signal until the logic 1 signal is transferred to the register stage 147, when the logic 1 signal will appear at the output of the gate 170 to repeat the cycle. The first GDi pulse register 140 may be passed along the respective output lines 151 to 157 and respective output lines 161 to 166 to an input of respective twoinput AND gates 171 to 177 and the input of an nor gate 170 respectively. The first pulse applied from the pulse generator 148 causes a logic 1 signal to be passed along the line 151 a second GDi pulse causes a logic 1 signal to be passed along the line 152 on receipt of this second GDi pulse and a third GDi pulse causes a logic 1' signal passed along the line 153 etc. These logic 1 signals pass along the line 151 to 156 to the respective AND gates 171 to 176 whose other inputs are connected to the pulses along the respective pulse lines S1, S2, S3, S4, S5, S6, these pulses being pulses received from the corresponding S1 S6 lines of the associated chip 130 as represented in FIG. 6. If a logic l pulse signal is received along the pulse line S1, when a logic 1 signal is applied from the stage 141 of the register 140 along the line 151 at the same time, an output logic l signal will be passed from the gate 171 along the output line 181 connected to an input of the or logic gate 188 and the logic l output of the logic or gate 188 appears on the output line 133 it will be apparent that because the pulses (GDi) from the pulse generator 148 are applied along lines 151, 152, 153 156, in sequence these pulses will be received by the or gate 188 in sequence and passed from the output line 133 to the time division multiplex circuit of the chip 132 (FIG. 6).

The seventh stage 147 of the register 11 has an output line 157 which is connected to the AND logic gate 177. A connection is made by a line 190 from the line 157 to the input ofa bistable circuit 192 which permits alternate logic I pulses from the seventh stage 147 of the register to be transmitted as timing pulses along a line 194 from the set output of the bistable circuit 192 to the and logic gate 177. By this means the timing pulses emitted from the seventh stage of the register 140 constitutes alternate mark (logic 1) pulses and space (logic O') pulses added on-to the train of six pulses which are transmitted from the or' gate 188 and correspond to the signals on the lines 51, 52, 53, 54, 55 and 56 (FIG. 2).

Referring to FIG. 8 of the drawings there is shown a receive register 200 consisting of 6 signal stages 201 to 206 respectively and one timing stage 207. A pulse generator, which preferably is the same pulse generator as the pulse generator 148 which applies pulses to the register 140, or at any rate is synchronized with the pulse generator 148, applies GDi pulses as shift pulses to the register stages 201 to 207 of the register 200. The stages 201 to 206 of the register 200 are connected by an output line 21 1, to 216 respectively to an input of a two-input and gates 231 to 236 respectively. The other inputs of the gates 231 to 236 are connected to a common line 238 which is connected to the connecting lead 133 by which the signals are received from the chip 130. The output signals of these and gates 231 to 236 respectively constitutes a train of pulses made up of respective output signals S1, S2, S6. The output lines 211 to 216 from the register stages 201 to 207 of the register is connected to the lines 221 to 226 respectively and these common lines are connected as inputs to a pair of eight input nor gates 240 and 242. The connecting lead 133 is connected directly to the first of these gates 240 and is connected to the second of these gates 242 through an invertor circuit 244. The output from the gates 240 and 242 are connected to the input of the first stage 201 of the register 200. The input to the first stage 201 of the register is also connected to the input of a bistable circuit 246 whose outputs are connected to inputs of the gates 240 and 242 respectively so as to alternatively supply a control pulse to the gates 240 and 242 whereby these gates are caused to operate alternatively.

When the train of signals is received along the line 133 the first 6 pulses constitutes a signal to be applied along the lines S1, S2 S6 whereas the seventh signal constitutes the timing signal T. For the first set of signals S1, S2 S6 the gate 240 operates to pass the input pulse to the register 200 and then the timing signal causes the appearance of a logic 1 pulse at the common output line of the gates 240 and 242 so that the outputs of the bistable circuit 246 change so that for the second set of signals S1 S6 the gate 240 operates to pass the input pulse to the register 200. Operation of these gates is effective under the control of the bistable circuit 246. When the timing pulse T is transmitted to the nor gates 240 and 242, and if the receive circuit 132 is in synchronism, the inputs 221 to 226 of the gates 240 and 242 are at logic 0. If the connecting line 133 is at logic 0, the inputs of the gates 240 and 242 connected to the connecting line 133 are at logic and logic l respectively. If the outputs of the bistable circuit 246 are at logic 0 and logic 1 respectively such that a logic 0 output appears at the nor gates 240 and 242 when the timing pulse T is transmitted from the transmit circuit 130, the register 200 does not receive a logic 1 signal to apply in sequence to the gates 231 to 236 until the next timing pulse T. When the next timing pulse T is transmitted from the transmit circuit 130 to change the input to one of the gates 240 or 242 so that all of the inputs of one of the gates are at logic 0, a logic 1 appears on this gate to cause this logic 1 signal to be applied sequentially to the gates 231 to 236 during the signals S1 to S6 which occur after this next timing pulse.

If the output lines S1 to S6 of the receive circuit 132 are out of synchronsim with the output lines S1 to S6 of the transmit circuit 130, then one of the inputs 221 to 226 to nor the gates 240 240 and 242 will be at logic I so that a logic 0 will appear at the output of the gates 240 and 242. The logic 0 output of the gates 240 and 242 will remain until the shift pulses GDi continuously applied to the register 200 shift the logic l output in the register 200 to the timing register stage 207 whereupon the lines 221 to 226 will all be at logic 0 at the correct point in time for synchronism so that the outputs of the bistable circuit 246 and the timing pulses from the transmit circuit 130 ensure that the circuit 132 will synchronize with the transmit circuit 130 after a minimum time equal to the duration of 6 GDi pulses'(which is a short space of time in the operation of the train).

The sequence of operation of the transmit circuit 130 and receive circuit 132 is shown in tabular form in FIG. 9.

By this invention we are able to transmit along a single line a series of signal pulses followed by a timing pulse which is received in such a way as to control the circuits.

What we claim is l. A calculating machine including transmitting and receiving integrated circuits for transmitting and receiving, between which signal pulses in a plurality of signal channels are passed on a set of interconnecting signal line leads fewer in number than the signal channels, a source of timing pulses, each circuit including a plurality of gates coupled between each lead and a corresponding plurality of signal channels and a plurality of circuit parts connected for transmitting the signals from said channels in a cyclic sequence and for synchronizing the signal pulses between said transmitting and receiving circuits once for each cycle of transmission of signals in response to predetermined timing pulses, at least one of the gates being adapted to be controlled by said predetermined timeing pulses to control the entry of received signals into said receiving integrated circuit.

2. A calculating machine according to claim 1, wherein the plurality of gates in the pair of integrated circuits includes a plurality of gate circuits which connect a plurality of signal lines to a common signal line between the transmit integrated circuit and the receive integrated circuit.

3. A calculating machine according to claim 2, wherein the plurality of circuit parts compriseing a synchronizing circuit include said source of timing pulses and a counter circuit connected thereto for counting as an endless loop, input circuits for the plurality of gate circuits connected to respective outputs of the counter circuit whereby the oscillator pulses cause the counter circuit to energize the gate circuits in sequence under the control of the predetermined time pulse.

4. A calculating machine according to claim 3, including a bistable circuit operated by an output of said counter circuit, wherein the predetermined time pulse is generated along a signal channel in the transmit integrated circuit by the output of said bistable circuit whereby successive predetermined time pulses alternate between one signal level and another signal level.

5. A calculating machine according to claim 4, including a further bistable circuit operated by an output of said counter circuit and a further pair of gate circuits, wherein the counter circuit of the receive integrated circuit is controlled by said further bistable circuit and said further pair of gate circuits, means providing one of the further gate circuits an inverted output compared with the output of the other gate circuit, the pair of said further gates having a circuit connecting their outputs to the input of the counter circuit and having an input connected to the common signal line from said transmitting integrated circuit and having another input connected to an output of the further bistable circuit, said circuits comprising means operating if the predetermined time pulse signals are in synchronism so that the signals transmitted along the signal lines of the transmit integrated circuit are transmitted along the corresponding signal lines of the receive integrated circuit; and if the predetermined time pulse signals are not in synchronism, the counting operation of the counter circuit of the receive integrated circuit is stepped under the control of the predetermined time pulse signals until the predetermined signals are in synchronism.

.6. A calculating machine according to claim 5, wherein the counter circuits are registers having a plurality of stages; and wherein the means transmitting the signals in cyclic sequence comprise a plurality of twoinput and logic gates having one input connected to an output of a respective register stage and means connecting the other input to these gates in the transmit integrated circuit to the respective signal lines and in the receive integrated circuit to a common signal line between the transmit and receive integrated circuits; and wherein the transmit integrated circuit includes an or logic gate whose inputs are connected to respective outputs of the and logic gates and whose output is connected to the common signal line between said integrated circuits.

7. A calculating machine according to claim 5 wherein the one gate having an inverted output of the pair of gates comprises an invertor circuit whose input is connected to the common signal line and whose output is connected to an input of the one gate of the pair of gates; and wherein the pair of gates are a pair of or logic gates whose outputs are connected to the input of the register.

8. A calculating machine according to claim 7, wherein the first mentioned plurality of gates include a plurality of switch means, each switch means having conduction connections by which the signal lines are connected to the common signal line and having a con trol connection which is connected to an output of the counter circuit, and means operating said switch means whereby when a negative potential is applied to the control electrode a short circuit exists between the two conduction electrodes, and when a positive potential is applied to the control electrodes, an open exists between the two conduction electrodes.

'9. A calculating machine according to claim 5,

wherein the counter circuit with one of the gate circuits having an input connected to the synchronizing circuit comprise a plurality of gate circuits and a plurality of switch means, each of the switch means having conduction connections by which successive gate circuits are joined together in series to form an endless loop and'having control electrodes in which alternate control electrodes are connected to the output of the pulse source and in which the remaining control electrodes are connected to the output of an inverter circuit whose input is connected to the output of the pulse source; and means operating the foregoing whereby a pulse signal is circulated around the counter circuit by the pulses from the pulse source under the control of the synchronizing circuit.

10. A calculating machine according to claim 5, including switch means with a control connection, wherein the synchronizing means included in the transmit integrated circuit includes a nor gate circuit having an input connected to one output of the counter circuit and having the output of the nor gate circuit connected by a pulse line to the common connection of the signal line through said switch means by control connection means connected to the output of the counter circuit of the one integrated circuit, a divideby-two bistable circuit, means connecting another input of the nor gate circuit to the output of said divide-by-two bistable circuit, means connecting its input to another output of the counter circuit to operate so that the synchronizing signal from the output of the nor gate circuit alternates between two voltage magnitudes, when the one output of the counter circuit is successively energized.

11. A calculating machine according to claim 10, wherein the synchronizing means included in the receive integrated circuit forms a synchronizing circuit including a nand gate circuit, a one nor gate circuit and another nor gate circuit whose input is connected to the output of the one nor gate circuit, a circuit including means connecting the outputs of the nand-gate circuit and the other nor gate circuit together as the output connection through the conduction connections of a switch means with a control connection to an input of the counter circuit of the receive integrated circuit, means connecting the control connection of the switch means to a first output of the counter circuit in the receive integrated circuit, which first output corresponds to the first output of the counter circuit in the transmit integrated circuit, a receive divide-by-two bistable circuit with an output connected to an input of both the one nor gate circuit and the nand gate circuits, and with the input connected to a second output of the counter circuit which corresponds to the second output of the counter circuit of the other integrated circuit, and means providing whereby, when the synchronizing circuit in the receive integrated circuit receives the synchronizing pulses from the synchronizing circuit of the transmit integrated circuit, the synchronizing circuit line of the receive integrated circuit transmits a signal which depends on whether the logic level of the received synchronizing pulse is the same as the logic level of the bistable circuit output, and providing while the logic levels are the same, that the output connection of the synchronizing circuit allows the counter circuit to operate; and, while the magnitudes are different, the output connection of'the synchronizing circuit prevents the counter circuit from operating, the foregoing means providing in the counter circuit of the receiver integrated circuit a delay in its operation, as a result of the action of its synchronizing circuit, until the counter circuits are in synchronism, when no further delays in operation occur.

12. A calculating machine according to claim 5, wherein a train of synchronizing pulses, are generated in the synchronizing means in the transmit integrated circuit during the time that the first counter circuit output in the synchronizing means of the receive integrated circuit is energized, means transmitting these synchronizing pulses along the signal line to the input of the synchronizing means of the receive integrated circuit to ensure that the first circuit outputs connected to the synchronizing means of the transmit and the receive integrated circuits are energized in synchronism, and, as a result, that the receive counter circuit outputs also are energized in synchronism.

13. A calculating machine including means for transmitting a signal from one integrated circuit to another integrated circuit along a single wire comprises a transmit circuit and a receive circuit, the transmit circuit having a transmit register having a plurality of stages, a gate associated with each stage of the register, means addressing a plurality of signals to these gates, means for applying a train of pulses to the register to apply pulses to the gates in sequence to open said gates in sequence and apply the signals applied to said gates to a single line; and wherein there is included an additional gate and means connecting it to apply a signal to the signal line in alternate of such train of pulses and the receive circuit having a receive register having a plurality of stages and gates associated with each stage of the register to which the signals received from the single wire are addressed, a pair of alternately operable input gates to the receive register and means connected thereto to apply pulses to the receive register in such a manner that if the signals are in synchronism, the pulses are passed to the receive integrated circuit, but, on receipt of unsynchronous signals, the pulses are delayed until the two trains of pulses are in synchronism.

14. A calculating machine including two integrated circuits which are connected to a source of oscillator pulses and which are connected together by a signal line for the transmission of signal pulses therebetween, each integrated circuit having plurality of pulse lines each of which has means connecting a respective point on the integrated circuit to a common connection of the signal line through a respective switch means having a control connection, a counter circuit having a energized in a synchronized sequence so that the said switch means in the respective integrated circuits are sequentially energized to connect in sequence the pulse lines in the respective integrated circuits to the signal line.

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Referenced by
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US3943488 *Jul 16, 1974Mar 9, 1976Fischer & Porter Co.Multiplex telemetering system
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Classifications
U.S. Classification708/190, 377/111, 377/76, 377/104, 377/73, 377/117
International ClassificationH04J3/04, H03K19/0175, H01L23/48, H03K5/135, G06F1/22, H03K19/00, G06F13/42, H03K5/156, G06F1/04
Cooperative ClassificationH04J3/047, H03K5/135, G06F1/04, H03K19/00, H01L23/48, G06F1/22, G06F13/423, H03K19/017545, H03K5/156
European ClassificationH01L23/48, H04J3/04D, H03K19/0175C, H03K19/00, H03K5/156, G06F1/04, H03K5/135, G06F1/22, G06F13/42C2S