|Publication number||US3693163 A|
|Publication date||Sep 19, 1972|
|Filing date||Oct 2, 1970|
|Priority date||Oct 2, 1970|
|Also published as||DE2105836A1|
|Publication number||US 3693163 A, US 3693163A, US-A-3693163, US3693163 A, US3693163A|
|Inventors||Irvin D Johnson, Eduard P Kaufmann, Mauro G Togneri|
|Original Assignee||Marathon Oil Co|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (10), Classifications (9), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
United States Patent Johnson et al.
[ Sept. 19, 1972  COMPUTER SET POINT STATION  Inventors: Irvin D. Johnson, Englewood, Colo.;
Mauro G. Togneri, Houston, Tex.; Eduard P. Kaufmann, Burghausen,
Germany Pn'mary Examiner-Harvey E. Springbom  Assignee: Marathon Oil Company, Findlary, Attorney-Joseph C. Herring, Richard C. Wilson, Jr.
Ohio and Jack L. Hummel  Filed: Oct. 2, I970 57 ABSTRACT PP 77,510 A device for interfacing a computer with an analog control system to control processes. The controlling 52 us. Cl. ..34o/172.s Computer changes P0int values 51 Int. Cl. ..G05b 15/00, G06f 3/00 Comm] Swim by addressing the individual  Field of Search ..34o/172.5, 146.1 Zeroing the set P value and inserting the new value.
[561 17 Claims, 7 Drawing Figures UNITED STATES PATENTS 3,58] ,289 5/1971 Wilhelm et al. ..340/l72.5
'MULTlC0NDUCT0R CABLE 1 SET POIN; INPUT GATING CONDUCTOR3Z l COMPUTER SET POINT 2O STATION MEMORY lNTERLOCK OSCILLATC? Dl6lTAL-TO-ANALOG COMPUTER" 3 '7 A CONIYIEGZTAEPIQD LOW 2i 3| 38,39 CLOCK CONDUCTOR 33-\D/A OUTPUT LINE ADJUSTMENT l ZERO cououcron CONDUCTOR 65 VARIABLE V Q g; .::.s:% 2%l'l3zlS 53,156? TERMMUFF, comm. LOGIC ADJUSTMENT FAIL-SAFE 27 1 L 4| MONITOR [40 1: LL OMPARATOR F63 ADDRESS 82 *9 25a LOGIC $235 compurzn CT STATUS CONDUCTOR LAMP ANALOG CONTROLLER CONDUCTOR PATENTEDsEP 19 1912 3,693,163 SHEETIOF'! EX i k m 9 N (O 1 A I I l wl N 1 4 l V 9h & \1
INVENTORS IRVIN D. JOHNSON MAURO G. TOGNERI INVENTORS IRVIN 0. JOHNSON MAURO G.TOGNERI PMENTEDSEP 19 I972 sum 5 (IF 7 PATENTEI JSEP 19 9 BB1 AVAILABLE COPY SHEET 8 0F 7 INVENTORS IRVIN D. JOHNSON MAURO G TOGNERI fiEDU R P. KAUFMANN BY .4
PATENTED EP 1 912 3.693; 1 63 SHEET 7 BF 7 INVENTORS IRVIN D. JOHNSON MAURO G. TOGNERI E AR RKAUFMANN M COMPUTER SET POINT STATION CROSS REFERENCES TO RELATED APPLICATIONS The only related pending patent application of which the inventors are aware is Ser. No. 623,015 filed Mar. 14, 1967, now US. Pat. No. 3,548,169 issued Dec. 15, 1970.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to methods for control of physical and chemical processes, particularly by digital computers controlling analog type actuators, e.g., valves by acting through the interfacing device of the present invention.
2. Description of the Prior Art The most commonly used device for providing an interface between a digital computer and an analog actuator, e.g., a valve, is a motor driven potentiometer such as those available commercially from a number of manufacturers. See for example, Spec. Sheet 98570-81 1 1-58, Taylor Instrument Co., Rochester, NY. These potentiometers are subject to wear because they involve moving parts, particularly parts in slidable contact. Further, these potentiometers require considerable computer time since the computer must address the potentiometer during the entire period over which the potentiometer adjustment occurs.
SUMMARY OF THE INVENTION The present invention avoids completely the need for moving parts by using, in preferred embodiments, entirely solid-state devices. The invention can be utilized as the interfacing device between a computer and a standard analog control system. In this method the output from the interfacing device of the invention operates as the set point input to a standard analog controller, preferably a recorder-controller. Alternatively, the devices of the invention can be used directly as direct digital control units by sending their output directly to the control valve or other analog device to be actuated.
Other advantages of the invention are:
1. Automatic bumpless transfer from manual set point adjustment to computer set point adjustment.
2. Digital memory, capable of holding value indefinitely.
3. Parallel input from computer. The memory in the unit can be updated in less than 1 millisecond.
4. High and low limits can be set to prevent the process from exceeding safe limits.
5. Maximum "rate of change" is settable in the unit to prevent a step-function from upsetting the process.
6. Fail-safe monitor-if the unit fails, the set point is automatically transferred back to the local set point adjustment in the analog controller. Controller and computer indicate such failure immediately.
7. Controller status lamp comes on only after the computer actually addresses the unit providing positive check on operation.
8. Computer address of the unit is wired into card position so identical units are interchangeable.
9. Minimum computer outputs, e.g., 21 and time (1 millisecond per unit) to control up to 1,024 units or more.
l0. Galvanic isolation between the computer including the invention and the process controllers with associated equipment.
Briefly stated, the invention involves methods and devices for converting output from a digital computer to operate an analog control system by successively changing the digital set point values in two or more analog control stations by first addressing the individual analog control station, then zeroing the set point value of the particular control station addressed and inserting the new digital set point value into the control station addressed.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the control system of the present invention operating on the physical components of a process system.
FIG. 2 is a block diagram of the components of the control system of the present invention.
FIG. 3 is a diagram of the circuitry of the set point input valve gating 19 and of the memory 20 and digitalto-analogue converter 21 shown in FIG. 2.
FIG. 4 is a diagram of the circuitry of the DC-DC converter 25, rate of change adjustment 43, oscillator 26, and high low limit adjustment 24, of the control system in FIG. 2.
FIG. 5 is a diagram of the circuitry of the variable address terminal 14, address logic 15, of the control system shown in FIG. 2.
FIG. 6 is a diagram of the circuitry of the control logic l6, and analogue comparator 18, shown in FIG. 2.
FIG. 7 is a diagram of the circuitry of the fail-safe monitor of control logic 16 of the control system shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. I, the control system of the present invention is used to control a typical process system in which components A and B flow into reactor 1. Component A flows through orifice plate 2. Differential pressure transducer 3 measures differential pressure (and thus flow) across the orifice plate. Flow controller 4 is an analog type of flow controller having a conventional remote set point input connected to computer set point station (CSPS) 5. Controller 4 is connected to flow control valve 6 through current-to-pressure converter 7.
A similar set point station (CSPS) 8 is connected to a similar current-to-pressure converter 9 and pneumatically operated control valve 10, all acting on component 8. Pressure transducer 11 and flow transducer 3 are both connected back to computer 12 which acts through the system of the invention to control the process. The temperature transducer 13 is also connected to the computer to feed back the temperature of reactor 1.
In operation, the system of FIG. 1 causes component A to flow through orifice plate 2 causing a differential across flow transducer 3 which is transmitted back to computer 12. Similarly, component B flows past pres sure transducer 11 which transmits a signal back to computer 12. The temperature transducer 13 measures the temperature in reactor 1 and transmits the temperature signal back to computer 12.
The computer analyzes these three inputs of flow, pressure and temperature, respectively, and, following a conventional process control program, calculates the optimum setting for flow control valve 6. The computer then digitally addresses CSPS 5 and, when the computer has addressed and been connected to that set point station, zeroes any previous digital set point contained in CSPS 5 and then transmits the new recalculated optimum set point into the memory of CSPS 5. CSPS 5 then gradually changes the digital set point in analog controller 4 until it conforms with the newly calculated optimum set point which is contained in the memory of CSPS 5. This gradual changing of the analog controller set point avoids bumps or discontinuities in process control. Analog controller 4 correspondingly adjusts its electrical output signal which is converted to a pneumatic signal by amperage-to-pressure converter 7 so that valve 6 gradually moves to a new position. Simultaneously, analog controller 4 continuously senses the flow from flow transducer 3 and continues to move valve 6 until the flow through orifice plate 2 equals the newly calculated optimum set point.
After computer 12 has addressed, zeroed and transmitted the new set point to set point station 5, it breaks the connection with CSPS 5 and addresses computer set point station 8. The previous set point value in CSPS 8 is zeroed and a new digital set point value (calculated approximately simultaneously with the optimum set point value for CSPS 5 and stored briefly in the memory of computer 127, is inserted into CSPS 8. Computer set point station 8 then transmits an amperage signal which is converted to pressure in converter 9 and transmitted to valve 10. Thus, CSPS 8 acts directly upon valve 10 and varies its position. The computer receives the new pressure signal from transducer 11, compares it to the newly calculated optimum pressure, readdresses, rezeroes and readjusts the digital set point in set point station 8 as necessary until the signal received from pressure transducer 1] equals the newly calculated optimum pressure. It should be noted that the set point which the computer transmits to CSPS 8 is in terms of valve position and the computer itself determines whether or not this valve position is the correct position to achieve the optimum pressure. This "direct digital control" is in contrast to the computer cascade analog control system" which is controlled by computer set point station 5. CSPS 5 resets an otherwise independent analog control loop to optimize the value at which it controls with the rest of the system. Set point station 8 merely positions the valve and the computer itself checks on whether this position provides the optimum pressure. While the control system used on component A has the advantage of being self-sufficient in case of computer failure, the direct digital control utilized for the pressure control on component B ofiers major economic advantages by the elimination of the additional cost of the analog control loop.
Referring to FIG. 1, it will be noted that a single multiconductor cable 29 connects the computer with both computer set point control stations. The use of this single multiconductor cable with the CSPS terminals connected in parallel is perrrtitted by the addressing feature of the invention.
The circuitry of CSPS 5 or 8 (which are identical except for the hard wired addresses" discussed below) is shown schematically as a block diagram in FIG. 2. The circuitry of each of the blocks of FIG. 2 is shown in more detail in FIGS. 3 and following which are discussed later in this application.
In FIG. 2 computer 12 is connected to variable address terminal 14 which contains a hard-wired" address which constitutes the digital address of the particular set point station. The variable address 14 is connected through address logic 15 to control logic 16 which feeds a "ready" signal back to the computer through interlock l7, and which also receives the reset signal to provide bumpless" transfer from local (noncomputer controlled) operation to computer controlled operation. The circuitry of elements 14 through l5, 16, 17 and 18 is shown in more detail in FIGS. 5, 6 and 7, respectively.
Control logic 16 is connected to set point input gating 19 so that when the particular CSPS is addressed through elements 14 and 15, control logic l6 responds by signalling set point input gating l9 and resets CSPS memory 20. This permits the incoming signal from line 22 to enter through gating 19 into memory 20. Since the signal from the computer is in digital form, it is necessary to provide a digital-to-analog converter 21. On transfer from local to computer set-point, the analog controller set-point is initially sent to comparator 18 for comparison with the set point which was previously set on the analog controller 4 while in the local mode. In normal operation, the output form the digital-to-analog converter 21 feeds through rate of change adjustment 23, high and low limit adjustment 24 and DC-to-DC converter 25 into the remote set point located in analog controller 4. Oscillator 26 provides a ramping to element 20 on the switch-over from local to computer control, provides a clocking pulse to control logic l6 and provides a chopping of the DC signal from DC to DC converter 25 in order to provide isolation of the output from that element. Fail-safe monitor 27 returns the analog controller 4 to the local mode upon any failure within the computer control system. (This fail-safe feature is inoperative in direct digital control.) Computer status lamp 28a is lit whenever the CSPS is under computer control.
FIG. 3 shows the circuitry of set point input value gating 19, memory 20, and digital-to-analog converter 21. In FIG. 3, the digital memory circuit systems F-l through F-ll are bistable circuits (flip-flops") which permit two modes of operation. In the first mode of operation, a one" signal enters through zero conductor 31 and conductor 32 is strobed (that is, its voltage is raised from a high to a low value for a short time period, e.g., 15 milliseconds). This strobing opens NOR-gates G-l through 6-10, allowing signals from the multiconductor cable 22 (composed of 10 separate conductors 22-A through 22-!) to enter corresponding flip-flops F-l through F40. Transistors T-0 through T-l0 then translate the binary value, which has entered, into an analog value which is transmitted through operational amplifier A-l into digital-toanalogue (D/A) output line 33, also shown on FIGS. 2, 4, and 6. A voltage divider comprising resistors 34 and 35 and relays b-6 and b-9 closes the loop and provides a feed-back signal for monitoring by the computer. The above-described mode is conveniently termed the computer-control mode" of the CSPS and is the normal mode during operation of the control system.
The second mode of the memory section of the CSPS is utilized in switching from local control to computer control, and is termed the scaling up mode of the CSPS memory. The memory is placed into the scaling up mode by a zero pulse arriving through count-enable conductor 38 and a zero-one-zero counting pulse arriving through clock conductor 39. The flip-flops F-l through F-lO begin counting the clock pulse from conductor 39 and continue to count until the voltage output of D/A output 33 becomes equal to the voltage of the controller set point in conductor 40. This equality is determined by feeding both of these voltages to comparator 18. When comparator l8 senses that the two voltages are equal it sends a high value through the conductor 48 which is normally at a low voltage, discontinuing the clock pulse input to line 39. The signal to count-enable conductor 38 is automatically discontinued approximately 150 milliseconds after it begins. This second mode permits bumperless transfer from local to computer control. The entire scaling up" mode will usually be accomplished in less than 100 milliseconds.
In FIG. 3, flip-flop F 11 is an overranging logical device utilized in the scale up mode" to permit overranging of the set point value up to as much as 200 percent of the set point value transmitted by the computer. Its function is to prevent constant recycling which would result from a minor discrepancy between the values in conductors 33 and 40, respectively.
FIG. 4 shows the circuitry of rate of change adjustment 43, high and low limit adjustment 24, DC-to-DC converter 25 and an oscillator 26.
In FIG. 4, resistor 42 and capacitor 43 limit the maximum rate of change at which the output from D/A output conductor 33 is transmitted to operational amplifier A-2 located within the DC-to-DC converter 25. A switch 44 permits selecting various alternate capacitors 43-A through 43-C to vary the maximum rate at which the signal is inputted to operational amplifier A2. In general, the input period rate will be in the range of from one second to one-thousand seconds, but is not narrowly critical and will preferably be matched to accommodate the rate of change encountered in the process which is being controlled. Transistor 45 compares the voltage on the slider arm 46 of a variable potentiometer which had previously been preset to the lower limit of the range of computer control. For example, the rate of the potentiometer can be set at a value corresponding to 50 percent of the control value and the computer will not control the process if the value of that parameter falls below 50 percent of the control value. If the computer attempts to input to the CSPS a control point which is lower than the lower limit preset into potentiometer slider arm 46, the control point corresponding to the lower limit will automatically be inputted into controller 4. Similarly, transistor 47 compares the voltage being inputted to operational amplifier A-2 with the voltage of the slider arm 48 of a variable potentiometer, thus providing a high level limit on the range of computer control. Normally, the values of the high and low level will be selected according to the safe range which the parameter may have in the process.
Control station 4 is galvanically isolated from the CSPS by means of transformer 49 (having secondaries 49b, shown on FIG. 7 and 49a, shown in FIG. 4), in
order to permit the control station output to float without reference to ground and to isolate the control station 4 from any short within the CSPS. To permit the galvanic isolation, the DC signal from operational amplifier A-2 is converted to AC by transistors 50 and 51 which are driven by oscillator 26, outlined with broken lines in FIG. 4 and also shown in block diagram F IG. 2. Within oscillator 26, resistor 52, capacitor 53, unijunclion transistor 54 and base resistors 55 and 56 form a unijunction relaxation oscillator having an output of 20 Hz which is divided by 2 and squared by flip-flop F-l2. The output from the flip-flop is amplified by bufier amplifiers 57 and 58. Isolation is provided by capacitor-resistor pairs 59-60 and 61-62. An unlimited signal is fed through conductors 63 to control logic 16. The necessary rectification of the AC signal from transformer 49 is provided by a rectifier 64 and the rectified signal is sent to controller 4 through conductors 65-A and B. Relays B-4 and B-5 provide an output monitor to the computer in a manner similar to that provided by relays B-6 and B-9 (shown in FIG. 3). All of the output monitor relays are actuated simultaneously and thus may be combined electrically, if convenient.
Relay B-3 bypasses resistor 42 to provide fast in put through operational amplifier A-2 when the CSPS memory is in the scale-up mode described above.
FIG. 5 shows the circuitry of the variable address 14 and the address logic l5. Terminal block 14 is wired with the unique digital address of the CSPS. The address shown wired in FIG. 5 is l l l." The terminals labeled 1 through 128 connect through multlconductor address cable (similar to cable 22) with the corresponding terminals of the computer ECO" (electronic contact operate) which comprises a series of switches operated in response to the programming of the computer.
While the IBM model 1800 computer is utilized with the particular control system described herein, virtually any digital computer equipped with a suitable ECO and having memory and other data processing ability adequate to control the physical system, can be util ized.
A specific description of the IBM 1800 computer and its "ECO" appears in the Physical Planning Manual for the IBM 1800, file number l800-l5, form number A26-5922-1, particularly pages 48-50, published by IBM, San Jose, Calif. 951 I4.
In FIG. 5, the address logic 15 contains the logic gate necessary to decode the address. NOR gates 67A through 67D decode the address from variable address 14. If the address signal from the computer ECO is identical with the address hard wired into the variable address 14, the NOR-gates of the address logic 15 output a signal to address-select conductor 66 (also shown on FIG. 2). This signal continues so long as the computer ECO continues to transmit the address, generally for about ID to 15 milliseconds. This pulse closes the contact on monitor relays b-4, b-S, b-6 and b-9, causing feedback to the computer through these relays. The signal in conductor 66 also is transmitted to control logic 16 causing the control logic to permit response to the reset signal (if any) on conductor 28 (shown in FIG. 6). The signal on conductor 66 also causes control logic 16 to be responsive to any set point value which may be transmitted while conductor 66 is energized. In
operation, control logic 16 does not respond to any reset pulse or any new set point unless both such signals are preceded by a signal corresponding to the address hard wired into variable address 14. Only when an address signal corresponding to the address of variable address 14 is first received, decoded by address logic l and conductor 66 energized, does control logic 16 respond to reset signals transmitted through conductor 28 or new set points transmitted through conductor 22. Pull-up resistors 68 and 69 can have 1,000 ohms or other suitable values.
it is this addressing characteristic of the circuitry which permits all of the CSPSs to be connected to the computer in parallel by means of a single multiconductor cable.
FlG. 6 describes the circuitry of control logic l6 and (outlined with dotted line) comparator 18. Hold up resistor 70 and NOR-gates 71 and 72 permit control logic 16 to respond to a reset signal on conductor 28 only when address select conductor 66 is energized. in operation, conductor 66 is energized upon an appropriate address being received by variable address 14 and address logic l5. NOR-gate 72 then has an output of zero. The reset signal from conductor 28 and the zero signal from NOR-gate 72 are both received by NOR-gate 71 which responds by energizing conductor 73 with a signal which is inverted by buffer amplifier 74 and transmitted to value gating conductor 32 which conducts the signal to set point input value gating 19, also shown in F I05. 2 and 3.
Capacitor 75, NOR-gate 76, buffer amplifier 77 and resistor 78 together form a single-shot multi-vibrator. in response to the energizing of conductor 73, this single-shot multi-vibrator sends a short duration pulse (approximately 0.1 millisecond) to zero conductor 31, also shown in FIG. 3. This pulse resets CSPS memory to zero. NOR-gates 79, 80, and 81 form a latching circuit. in response to an output signal from NOR-gate 72, NOR-gate 79 transmits a signal to NOR-gate 80 which, in conjunction with NOR-gate 81, acts as a latch to continuously energize conductor 82 causing computer status lamp 28a (shown in FIGS. 1 and 7) to light, indicating that the particular CSPS has been addressed and is under computer control. During addressing by the computer, the signal from conductor 66 also goes to NOR-gate 83 energizing conductor 84 which energizes relay coils 8-4, -5, -6, and -9, closing the corresponding relays b-4, 5, 6 and -9, causing feedback signals as described above.
Conductor 85 connects to one side of NOR-gate 81 and one side of NOR-gate 86 which outputs through resistor 87 and time-delay capacitor 88 into one side of NOR-gate 89 which itself outputs into one side of NOR-gate 79, previously described. When the local controller is in the local position conductor 85 is energized at a "one" level, thus NOR-gate 79 prevents the lighting of the computer status lamp.
NOR-gate 90 outputs through capacitor 91 and resistor 92 to one side of NOR-gate 76, previously described. Elements 91, 92, and 76 thus comprise a single shot multivibrator which generates a 0.l millisecond signal in zero conductor 31, resetting the memory of control logic to zero at the instant when controller status conductor 85 is deenergized by manually switching the controller from local to the computer control mode.
NOR-gate 93, capacitor 94, NOR-gate 95, resistor 96 together comprise a single shot multivibrator generating a 150 millisecond pulse into one side of NOR-gate 97 at the instant that conductor is deenergized by manually switching to the computer control mode.
This pulse goes to NOR-gate 97 and buffer amplifier 98, bringing count-enable conductor 38 to a zero logic level for 150 milliseconds, permitting control logic memory to operate in the scale-up mode. The same pulse from bufier amplifier 98 also gates NOR-gate 99. NOR-gates 99 and 100 are in parallel so that the pulse to NOR-gate 99 gates NOR-gate 100 admitting the IQ KHz signal to clock conductor 39. The pulse from NOR-gate 97 also passes through resistor 10! energizing relay coils 8-1, 8-2, and B-3 (shown in FIG. 7).
The circuitry of comparator 18 is outlined with a dotted line in FIG. 6. When conductor 102 is energized with a one signal, relay coils 8-], 8-2 and B-3 (shown in FIG. 7) operate transfer contacts b-] and b-2, (shown in FIG. 6) and b-3 (shown in FIG. 4). Operational amplifier 103 then receives a voltage pulse from capacitor 104. This voltage pulse which is indicative of the set point value then set in the analog controller, is compared with the output from the digital-to-analog converter 21, which is inputted to the operational amplifier 103 acting through scaling resistors 105 and 106. So long as the voltage pulse from capacitor 104 (the controller set point value) is greater than the digital-toanalog converter output in conductor 33, operational amplifier 103 will output a zero signal through resistor 126 into one side of NOR-gate 100 admitting the IQ KHz signal from conductor 63 to clock conductor 39. This causes scaling up of the value in the CSPS memory 20. A zener diode 127, connected to ground limits the voltage between operational amplifier 103 and NOR- gate 100.
When control logic memory 20 is in the scale-up mode, activating (closing) relay b-3 allows capacitor 43 to charge rapidly through resistor 109 (both shown in FIG. 4). 0n initial transfer to computer control mode, this allows rapidly bringing the output of the CSPS on conductors 65-a and 65-h into equality with the locally set set-point on conductors 40-0 and 40-h, thus providing bumpless" transfer from the local to the computer control mode.
FIG. 7 shows the circuitry of interlock l7 and a remaining portion of the circuitry of control logic l6.
Relays b-l through b-7 and b-9 have been previously discussed above.
A warning of failure of a CSPS is provided by conductor 107 which energizes relay coil B-8 sending a continuous signal indicative of failure to the controller and returning the controller automatically into local mode. A pulse is directed back to the computer through conductor 107 at the start of each time when the CSPS is addressed by the computer. Various accessory circuits may be added to provide "ready" or additional "failure" signals to the computer which can be programmed to respond in accordance with various emergency procedure programs.
When line 107, described above, is energized, NPN- transistor 110 admits current to conductor 1 ll sending a ready" signal back to the computer. Output to controller 4 is monitored by the second of the secondary windings 49-8 of the transformer (the primary and other secondary of which are shown in FIG. 4). This output is rectified by bridge rectifier 112 and fed to operational amplifier 113 and compared with a reference voltage established by resistors 114 and 115. if the output voltage drops below the preset limit set by the resistors, operational amplifier 113 will latch in the up mode due to the positive feed back through diode 116 and resistor 117, thus placing a positive voltage on conductor 118 and deenergizing relay coil B-S, turning on monitor failure lamp 119, indicating failure of the particular CSPS.
Conventional commercially available circuitry components may be employed with the invention. For example, the operational amplifiers can conveniently be Model No. SQ 10A manufactured by Nexus of Canton, Mass. and described in their brochure PB-l03a- 9/66( 1966914 manufactured by Fairchild, and flip-flops can be Model No. 923 manufactured by Fairchild and described in their brochure BR-BR-00l5-29-100M, Library of Congress Cat. No. 75-8731 l( 1969), control stations can be Model No. 940R, manufactured by Taylor and described in their brochure 98569Sl( 1969), File ll-SA. Conventional power and ground connections to the various components should be supplied where conventionally required, e.g., to the NOR-gates. In general, the conventional techniques of computer control of set points and direct digital control by computer are applicable to the present invention, see, for example, Computer Control of Industrial Process by ES. Savas, McGraw-Hill (1965), Computer Process Control by Lee A. Gaines, and Mathematical Modeling in Chemical Engineering by R. G. E. Franks, John Wiley and Son I967).
MODIFICATIONS OF THE INVENTION It should be understood that the invention is capable of a variety of modifications and variations which will be made apparent to those skilled in the art by a reading of the specification and which are to be included within the spirit of the claims appended hereto. For example, all of the CSPS can be linked in parallel to a continuous loop multi-conductor cable, expanding over a large area employed by the process plant, which is connected back to itself just prior to the connection to the computer. Such a loop will continue to provide control to each of the CSPS spread throughout the plant, even if it is broken at any single point along its length. Further, the loop can be extended by merely breaking the loop and adding sections where desired without taking any of the CSPS out of service. As has been previously stated, the CSPS can be utilized for direct digital control rather than operating through an analog station as described in some portions of the specification. Instead of the multiconductor cable, a single conductor cable may be utilized if a shift-register" is installed in each CSPS. Such a shift register receives the address signal as a series of pulses from the signal conductor and directs each pulse to a different logical component of the shift register. After all pulses have been received, they are then simultaneously transmitted to the CSPS which then operates as described above for a multiconductor cable installation. By utilizing a carrier wave signal to conduct the pulses into the shift register, the ordinary utility wiring can be used to carry the signals. CSPSs can then be plugged into any normal convenience outlet in the installation affording a high degree of portability where desired.
An analogous design using AND-gates in place of the NOR-gates can be substituted; a very wide variety of process components as well as machines can be controlled by the invention, the collectors and emitters of the individual transistors can be transposed in the circuitry.
What is claimed is:
1. Apparatus for interfacing a digital computer with a control system comprising in combination,
a. a digital computer controlling the system in response to inputs received from various sensors indicative of conditions within various points in the system, said computer having means for outputting a selective digital address signal and associated command signals,
. a multiplicity of control stations, each of said control stations having means for controlling at least one variable of the system in response to one of said command signals indicative of a desired control point value for that variable,
c. common cable means for receiving said selected digital address signal and associated command signals outputted by said computer means, said cable means being connected to a plurality of said control stations,
. prewired address means in each of said control stations which is distinct from similar prewired addresses of other of said control stations,
d. comparator means in each said control stations for comparing the address outputted by said computer with said prewired address,
f. address logic means for permitting said digital command signals to be transmitted from said computer to said memory means, within a particular control station, when, and only when, said command signals are associated with an address signal corresponding to the prewired address of said particular control station,
g. zeroing means in each said control station for ze roing said memory means in response to an appropriate zero command signal from said computer,
h. memory means in each said control station for storing said desired control point value transmitted from said computer.
2. The apparatus of claim 1 wherein there is further provided:
i. rate of change limiting means for controlling the transmission of said signal from said memory to said control station so that the control value signal inputted to said control station changes at a rate not in excess of a predetennined maximum rate of change whereby said new digital control value is gradually applied to said system.
3. The apparatus according to claim 2 wherein the rate of change limiting means comprises capacitive means having a preselected time constant corresponding to the desired maximum rate of change.
4. The apparatus according to claim 1 wherein the signal outputted by said computer is transmitted to said comparator by means of a multi-conductor cable connected to a plurality of said address comparators.
5. The apparatus according to claim 4 wherein said address signal is binary in character and each binary bit is transmitted through a separate conductor.
6. The apparatus according to claim 5 wherein each binary bit is carried on both a bit conductor and a notbit conductor and wherein redundancy checking means is provided to check the bit-signal for correspondence with the non-bit signal.
7. Apparatus according to claim 4 wherein said multi-conductor cable is looped back upon itself so that two alternate paths are provided for transmitting said computer signal to said control station.
8. The apparatus according to claim 1 wherein the control station is a direct digital control station which actuates means for controlling said system variable and whereby the value of said variable is measured by a sensor which transmits said value to the computer and not to any localized control station.
9. The apparatus according to claim 1 wherein the control station is an analog control station and wherein the signal received from said memory adjusts a set point on an analog control loop and wherein the value of said system variable is determined by a sensor which transmits said value back to said analog control station.
10. In a process for converting output from a digital computer to operate a control system by changing the digital control point value in the memory of a desired control station via a common cable means to which a plurality of said control stations are connected, the improvement comprising:
a. transmitting via said common cable an address signal which causes the desired control station to become responsive to a command signal,
b. transmitting a command signal to zero the set point value of said desired control station, and
c. thereafter transmitting a command signal to insert the new digital control point value into the memory of said desired control station.
II. A process according to claim including the step of said computer transmitting signals from said comparator by transmitting each digit of said signal over a separate conductor of a multi-conductor cable and wherein said signals are transmitted to a plurality of said comparators, each connected to the conductors of said multi-conductor cable.
12. A process according to claim 11 wherein said address signal is binary in character and each binary bit is carried by a separate conductor.
13. A process according to claim 12 wherein each binary bit is carried on both a bit conductor and a not-bit conductor and wherein redundancy checking means is provided to check the bit-signal for correspondence with the non-bit signal.
14. A process according to claim 10 wherein the control station is an analog control station and including the additional step of the signal received from said memory causing adjustment of a set point on an analog control loop, and determining the value of said system variable by a sensor which transmits said value back to said analog control station.
15. A process according to claim 10 including the additional step of said memory continuously transmitting said new digital control values to said control station until said digital control value is zeroed in response to a zero co m d i al from said c uter, sai zero commar ifi si g nal b i ng accompanie or prece ed by a proper address signal.
16. The process of claim 15 wherein the transmission of said signal from said memory to said control station is limited by rate of change limiting means so that the digital control value signal inputted to said control sta tion changes at a rate not in excess of a predetermined maximum rate of change whereby said new digital control value is gradually applied to said system.
17. A process according to claim 1 wherein the control station is a direct digital control station and the control station actuates means for controlling said system variable including the additional step of measuring the value of said variable by a sensor which transmits said value to the computer and not to any localized control station.
UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,693,163 Dated Sept. 19, 1972 lnventofls) I.D.Johnson, E.P.Kaufmann, M.G.Togneri It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:
Col. 3, line 31: "the memory of computer 127" should read the memory of computer l2)- Col. 9, line 17: (1966914 manu" should read:
-- (1966) NOR-gates can be Model No. 914 manu- Col. 10, line 33: "d." should read e.
Si ned and sealed this 1st day of May 1973.
EDWARD M. FLETCHER, JR. ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents DEW PC7-1050 USCOMM-DC scan-Pen 9 U S GOVEPNHENY PRlNYlNG OFFICE 1,59 O-]65-Jll.
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|U.S. Classification||700/9, 700/10|
|International Classification||G05B15/02, G05D11/13, G06F19/00, G05B15/00, G06F13/00|
|Jun 13, 1983||AS||Assignment|
Owner name: MARATHON OIL COMPANY, AN OH CORP
Free format text: ASSIGNS THE ENTIRE INTEREST IN ALL PATENTS AS OF JULY 10,1982 EXCEPT PATENT NOS. 3,783,944 AND 4,260,291. ASSIGNOR ASSIGNS A FIFTY PERCENT INTEREST IN SAID TWO PATENTS AS OF JULY 10,1982;ASSIGNOR:MARATHON PETROLEUM COMPANY;REEL/FRAME:004172/0421
Effective date: 19830420