|Publication number||US3699397 A|
|Publication date||Oct 17, 1972|
|Filing date||Mar 30, 1971|
|Priority date||Mar 30, 1971|
|Publication number||US 3699397 A, US 3699397A, US-A-3699397, US3699397 A, US3699397A|
|Inventors||Kuck John H|
|Original Assignee||Us Navy|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (2), Classifications (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
[ 1 Oct. 17, 1972 FLUX-DRIVER CIRCUIT FOR PHASED ARRAY Primary Examiner-J. D. Miller Assistant Examiner-Harry E. Moose, Jr.
 Inventor: John H. Kuck, Silver Spring, Md. Anmey R. S- Sciasica Q. E Hodges and J. I  Assignee: The United States of America as Rosenblatt represented by the Secretary of the Navy  ABSTRACT  Filed: March 30, 1971 A flux driver circuit supplies a pair of control pulses to a magnetically controlled analogue microwave phase  Appl 129312 shifter used in a phased array antenna system. The flux driver circuit system first delivers a reset pulse  US. Cl ..317/l23, 3l7/DIG. 4, 317/148, which drives the magnetic material to saturation in 343 100 SA, 343 354 one direction and then supplies a set pulse which 51 Int. Cl. ..H0lh 47/22 drives the magnetic material in the pp direction  Field of Search ..3l7/DIG. 4, 148, 123; and to a predetermined desired flux level when the 343/100 SA, 854, 754 radar system changes from the transmit to the receive mode and a new predetermined flux level is desired in R f d the phase shifters, the reset-set cycle is again repeated.  e erences e The level of magnetic flux in the phase shifter is con- UNITED STATES PATENTS trolled by a DC. command voltage supplied to the circuit. Provision is made for reversing the polarity of the H 2/1958 McLean et a1 17/148 X applied reset-set voltage when switching the antenna 3,237,088 2/1966 Karp et a1. ..3l7/DIG. 4 between the transmit and the receive modes. 3,438,044 4/1969 Elia et al ..343/854 3,484,785 12/1969 Sheldon et al. ..343/854 X 15 Claims, 2 Drawing Figures I Zi Zi IT 1 |3 i I i4 43 I 2o 39 23 I I 25 I AND OR SELECTOR OR I VOLTAGE i 'NTEGRATOR COMPARATOR GATE GATE I SWITCH GATE I AMPLIFIER U I l l I J L I I ll I i 1 l DUMP .FL .FL i i CIRCUIT 3 5-; (TRAILING EDGE) i C i l Jl i T l l I l SELECTOR 37 3. OR I L SELECTOR 0R i i VOLTAGE n SWITCH at GATE i I SWITCH GATE I I AMPLIFIER I R I (LEADING EDGE) I V I I I A l5 [7 L l l |L I T c I T R 7 27./ I SELECTOR mi/E T iER SWITCH *2 29 2s I R l i l i f 33 L A B PHASE SHIFT PHASE SHIFT DRIVER DRIVER 1 I FERRITE PHASE SHIFTERS PATENTEDncI 11 m2 SHEET 2 BF 2 INVENTOR.
JOHN H. KUCK I '/'I ATTORNEY FLUX-DRIVER CIRCUIT FOR PI-IASED ARRAY BACKGROUND OF THE INVENTION Non-reciprocal magnetic phase shifters are widely used in phased array antenna systems. These nonreciprocal phase shifters must be reset between the transmit and receive modes. A provision must be made therefore, for reversing the polarity of the pulse pairs when switching the antenna between the transmit and receive modes.
SUMMARY This invention relates to a flux driver circuit for supplying control pulses to the magnetically controlled analogue microwave phase shifters employed in a phased array antenna system. The function of the driver circuit is to deliver two closely spaced constant voltage pulses of opposite polarity to a magnetically controlled analogue microwave phase shifter. The pulses must be of proper durations so that the magnetic material in the phase shifter is first driven into saturation in one direction by the reset pulse and is then driven in the opposite direction with a variable pulse width set pulse. The width of the variable pulse width set pulse is proportional to a level of D.C. command voltage corresponding to the predetermined flux level to be established in the phase shifter. A microwave phase shift introduced by the phase shifter is a function of the magnetic flux and is therefore a function of the command voltage too.
The flux driver circuit may be summarized as follows. At the inception of any mode, i.e., transmit or receive, a reset gate pulse is externally delivered to the flux driver circuit. The reset gate pulse is channeled through a reversing switch to either one of two parts of a voltage amplifier. The voltage amplifier, responsive to the alignment of the reversing switch and to the reset gate pulse delivers a pulse of the appropriate positive or negative polarity. Immediately after the reset gate pulse is terminated, at phase shifter saturation, a set gate pulse is applied externally to the circuit driver. As the desired predetermined flux level in the phase shifter is variable, a D.C. command voltage externally applied to the phase shifter is used to control the degree of phase shift during the set gate pulse interval. Feedback is employed between the phase shifter and the driver circuit and the set pulse is terminated when the desired level of flux is reached within the magnetic phase shifter.
As this device is non-reciprocal, a reversing switch is used whose switching alignment is responsive to external signals keyed to the transmit mode and the receive mode time intervals. The reversing switch causes a reversal in the polarity of the reset and set pulses relative to the polarities of these pulses during the preceeding cycle. For example, if the polarity happened to be positive for the reset pulse and negative for the set pulse during the transmission mode, the reversing switch would reverse the polarity of the voltage amplifier output so that during the receiving mode the polarity of the reset pulse would be negative and the polarity of the set would be positive. Non-reciprocity means that the magnetic flux of the phase shifter must be reversed when the direction of propagation of RF energy to the phase shifter is reversed as in the case of transmit and receive modes.
Certain specific features of the invention include an integrator whose input is the voltage across the phase shifters when the set pulse is applied. The integrator circuit delivers an output proportional to the change in flux across the phase shifters and when the integrator output voltage matches the D.C. command level voltage, the set pulse is terminated.
This circuit has an advantage of being a more efficient flux driver as the width of the reset pulse is controlled to a minimum duration necessary to saturate the phase shifter.
Accordingly, it is one object of this invention to establish predetermined flux levels within a phase shifter of a phased array.
It is a second object of this invention to deliver two closely spaced constant voltages of opposite polarity to a magnetically controlled analogue microwave phase shifter to drive the phase shifter to saturation in one direction and then drive it to a predetermined flux level in the opposite direction.
It is a third object of this invention to reverse the polarity of the set and reset pulses between the receive and transmit modes.
It is a fourth object of this invention to control the width of the variable set pulse in the predetermined level of flux in the phase shifter by means of an external applied D.C. command voltage.
These and other objects of the invention will accordingly become evident when the following description of the preferred embodiment is read.
BRIEF DESCRIPTION OF THE DRAWING FIG. 1 shows the flux driver in block diagram. FIG. 2 is a time diagram of the outputs of the circuit elements shown in the FIG. 1 block diagram.
DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 1 and 2, the flux driver will be described with reference to its operation and the operation of its particular elements, shown in the block diagram of FIG. 1, and whose outputs are shown in the time diagram of FIG. 2. The flux drivers basic components are the set generator, enclosed by the box in dashed lines and designated generally by the numeral 1, the reset generator, enclosed by the box in dashed lines and designated generally by the number 2, the reversing switch, enclosed by the box in dashed lines and designated generally by the numeral 3 and the voltage amplifier 4, enclosed by the box in dashed lines.
As a starting point in time for the purpose of explaining this invention, the onset of the radar system's transmit mode is chosen as t The flux level of the phase shifters during the preceeding receive mode is modified and reset to a desired transmission level mode in two steps (1) a reset gate pulse is generated to drive the phase shifters into saturation and then a set pulse is generated to drive the phase shifters .to the predetermined flux level for transmission. Saturation is attained by generating a reset gate pulse signal at t as shown in line A of FIG. 2, and by inputting the reset gate signal into a dump circuit 11. Dump circuit 11, triggered by reset gate pulse erases the memory" of integrator 13, and brings the output of integrator 13, shown in line F of FIG. 2, to zero. The reset gate pulse is simultaneously fed into the reset generators differentiating circuit 15, which generates a pulse coincident with the reset gate pulse leading edge at t (shown in line B of FIG. 2). The output of differentiator 15, is inputted to the reset generators or gate 17. Or gate 17, responsive to the pulse generates a pulse (shown in line C of FIG. 2). The output ofor gate 17, is fed in parallel to differentiator 19, which emits a pulse at t.,, FIG. in line D of FiG. 2, in response to the trailing edge of the gate pulse, and to the selector switch 21, within the reversing switch 3. The selector switch 21 is programmed during the transmit mode to switch the or gate signal from gate 17 to or gate 23. The signal pulse from or gate 23 is then inputted to voltage amplifier 25, which emits a negative going reset pulse (line E of FIG. 2) through bus 27, (line I of FIG. 2) to phase shifter drivers 29 in parallel.
The negative going pulse shown in FIG. 2, lines E and I, produces a corresponding voltage at the monitor output 31, of the phase shift driver. This monitor output is channeled to phase inverter 33, which produces a signal of positive polarity appropriate to keep or gate 17 turned on. Selector switch 35 is programmed in the transmit mode to connect input terminal A to output terminal C. Selector switch 35 is programmed during the transmit mode so the signal from the phase shift drivers 29 is channeled through the phase inverter to or gate 17. The signal from the phase shift driver monitor output 31 then maintains or gate 17 on, after the termination of the reset pulse at t and until saturation of the phase shifters is attained at t,,.
At the point of saturation the impedance of the phase shifters will be approximately zero and the voltage across the phase shifter will also be approximately zero, as will be the signal at the input to or gate 17. This approximately zero signal at the phase shifter is below the or gate threshold and turns or gate 17 off, terminating the reset pulse from voltage amplifier 25, at time Differentiator 19, producing a pulse (shown in line D of FIG. 2) at the trailing edge of the signal from or gate 17 at t, is fed into or gate which produces a narrow width pulse. This pulse is connected to or gate 41, through programmed selector switch 39, producing a spike at the output set voltage amplifier 26 (line H of FIG. 2) and on line 27 (line I of FIG. 2). The spike at the output of voltage amplifier 26 is seen immediately after the termination of the reset pulse at is useful in the transition between the reset and set opposite polarity pulses.
Immediately after the reset pulse drives the phase shifter to saturation and the spike (shown in line H) is produced at the output of voltage amplifier 26, the set gate pulse is initiated and fed into the input of and" gate 43, of set generator 1. A D.C. level is maintained at the input to comparator 45. This D.C. level is proportional to the flux level to be generated in the phase shifter during the set pulse cycle for the transmission mode. The comparator is a digital device producing a signal when the output of the integrator is less than the D.C. set control voltage and producing no signal when the output of integrator 13 is equal to the D.C. set control voltage. As shown in line F of FIG. 2, at t when the reset gate pulse brings the output of the integrator to zero, the output of comparator 14 undergoes a step increase at t representing a digital change from 0 to l After t a 1" output signal appears at the output of comparator 14, as shown in line G of FIG. 2.
The and gate 43, responsive to the set gate pulse shown in line A of FIG. 2, at 1 and comparator 1" output (line G of FiG. 2) produces a pulse signal at its output (line J of FIG. 2) which is fed into or" gate 20. Or gate 20 output is fed to selector switch 39, of reversing switch 3, programmed during the transmit mode to direct the signal pulse from or gate 20 to or gate 41. The signal output from gate 41, shown in line K, is fed into voltage amplifier 26, which produces a set output pulse shown in lines H and I of FIG. 2. This positive pulse is conveyed on bus 27, (shown in line I of FIG. 2 at t to phase shifter drivers 29, connected in parallel. Selector switch 37 is programmed during the transmit mode to transmit the positive going pulse at the monitor output 31 of the phase shifter drivers, from terminal A to terminal C, through to the integrator 13. The output of integrator 13 (shown in line F), being I edt over the time period t to t is shown in line F of FIG. 2. Comparator 45, as explained, is a digital device and has a digital output signal 1 (shown in line G of FIG. 2) for as long as the output of integrator 13 is less than the D.C. set control voltage (shown in line F of FIG. 2). At t when the output of integrator 13 reaches the level of the D.C. set control voltage the comparator digital output returns to 0, turning off the signal fed to and gate 43, turning off and gate 43 and or gate 41 and ultimately turning off the set pulse from voltage amplifier 26. The level of flux in the phase shifter is now proportional to the D.C. level of the set control voltage and the phase shift induced by the phase shifters will be the phase shift required to produce the desired effect in the radar beam during the transmit mode.
At termination of the transmit mode at t a reset pulse is once again generated to saturate the phase shifters preparatory to driving the phase shifters to the level of flux required during the receiving mode. The system is seen to function in establishing the flux levels for the receive mode as explained above in connection with the transmit mode. The differences are that the reset and set pulse polarities are reversed in relation to those generated in the transmit mode.
The reset gate pulse generated aft is inputted to dump circuit 11, as in the transmit mode. The dump circuit, as explained above, erases the memory of integrator 13, and this may be done simply by shorting the output of integrator 13 to ground. Differentiator 15, generates a pulse in response to the leading edge of the reset pulse shown in line B at t The pulse is fed into or gate 17, which produces a pulse shown in line C, fed in parallel to differentiator 19, and selector switch 21 of reversing switch 3. Selector switch 21 is programmed during the receive mode to channel the pulse of or gate 17, through to or gate 41. Or gate 41 in turn generates pulse to turn on voltage amplifier 26. The output of voltage amplifier 26 is a reset pulse as shown in line H of FIG. 2, in phase with the preceeding set pulse and which is fed to the phase shifter drivers 29. The output of phase shifter drivers 29 produces a voltage at monitor output 31, and across the phase shifters. The voltage at monitor output 31 is fed back through feedback signal bus 28, through programmed selector switch 35, to or" gate 17. Selector switch 35 is programmed during the receive cycle to connect the signal at terminal B to terminal C. The output signal on feedback bus 28, channeled through selector switch 35, maintains or" gate 17 on and maintains the output of voltage amplifier 26, constant until phase shifter saturation is attained. At saturation the output of the voltage across the phase shifters drops below the threshold level of or gate 17, turning off or gate 17 and terminating the receive mode pulse at r,,.
Immediately following the termination of the reset cycle a spike of opposite polarity to the reset pulse is generated followed by the onset of the set pulse as explained above, in connection with the transmit mode. The D.C. set control level is adjusted during this receive cycle to be proportional to the predetermined level of flux desired in the flux driven phase shifters for the receive mode.
At the initiation of the set pulse at t the output of the integrator 13 is zero, and the output of the comparator is the digital output signal I. This signal in combination with the set gate pulse turns and gate 43 on and a pulse signal is generated at the output of the and gate, and at the output ofor gate 20, shown in line J of FIG. 2. The and gate signal is channeled through selector switch 39 of reversing switch 3, programmed during the transmit mode to channel the output of or gate through to or gate 23. Or gate 23, generates a pulse which is fed into voltage amplifier 25, to produce a negative going pulse at its output (line E of FIG. 2) and on bus 27 (line I of FIG. 2). This negative going output is conveyed on bus 27, through to phase shifters 29 connected in parallel. The output of phase shifter driver 29, at monitor output 31, is conveyed by feedback signal bus 28, to phase inverter 33. The inverted pulse appearing at programmed selector switch 37 is connected from terminal B to terminal C, and to the input of integrator 13. The output of integrator l3 begins to rise at as shown in line F of FIG. 2. When the output of integrator 13 reaches the level of the D.C. set control at t,, the output of comparator 14 drops to zero, turning off and" gate 43, and turning off the set pulse for the receive mode.
At the termination point, t,, of the set pulse for the receive mode, the level of flux within the phase shift is at a sufficient level to give the desired phase shift response to the received signal.
It can be seen that this apparatus can be used to change the level of flux in a magnetic phase shifter by adjusting the level of D.C. command voltage at the input to comparator 14. The relative polarities for the output of the voltage amplifier are shown for one type of phased array where the direction of flux within the phase shifters are opposite relative to the transmit and receive modes. It is seen that the polarities of the voltage amplifiers and 26 vmay be rearranged to be suitable for the characteristics of the particular phased array used with this system.
Obviously many modifications and variations of the ,present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
What is claimed is:
1. A system for driving a non-reciprocal magnetic analogue phase shifter, in a phased antenna array, to predetermined flux levels, comprising:
a reset generator connected to the phase shifters for driving said phase shifters into saturation;
a set generator connected to the phase shifters for driving said phase shifters in a reverse direction from saturation and to said predetermined magnetic flux level; and
said reset generator being responsive to the flux level of said phase shifters and driving said phase shifters until said phase shifters reach saturation.
2. The system of claim 1, including a reversing switch having an input connected to said set and reset generators and its output connected to said phase shifters for inverting the polarity of the transmission mode reset and set driving signals relative to the receiving mode reset and set driving signals.
3. The system of claim 2, wherein: a control voltage is applied to said set generator corresponding to said predetermined flux level; and
said set generator responsive to said control voltage and said phase shifter flux level drives said phase shifters until said phase shifter flux level corresponds to said control voltage.
4. The system of claim 3, wherein said reversing switch output is connected to a voltage amplifier; and
said voltage amplifier output being connected to said phase shifters and being a pulse of a predetermined polarity in response to the alignment of said reversing switch.
5. The system of claim 4, wherein said reset generator comprises an or gate having first and second inputs;
said or gate having an output connected to said reversing switch and providing a pulse to said reversing switch in response to a reset gate pulse at said first or gate input;
said reversing switching the output of said reset generator or gate to said voltage amplifier;
said voltage amplifier generator having an output pulse in response to said or gate pulse of a first polarity and driving said phase shifters toward saturation;
a feedback loop connected at one end to said phase shifters and connected at its other end to said second input of said reset generator or gate; and
said reset generator or gate having an output in response to said voltage across said phase shifter until said phase shifter voltage drops below said reset generator or" gate input threshold level, turning off said or" gate output.
6. The system of claim 5, wherein said set generator comprises an integrator, a comparator, and an and gate;
said comparator having a first and second input;
said first comparator input being said control voltage;
said comparator having a second input connected to said integrator output;
said comparator output being connected to a first input of said and gate;
said integrator output going to zero in response to said reset gate pulse;
said comparator having a digital output signal corresponding to l or and having its l signal output when said integrator output is less than said DC control voltage;
said and gate having an output pulse in response to said set gate pulse signal at its first input and said comparator l output at its second input;
said and gate output being connected to said reversing switch;
said voltage amplifier responsive to said reversing switch alignment, delivering a pulse output opposite in polarity to said reset pulse output;
said feedback loop being connected to said set generator integrator;
said integrator having an output proportional to the flux level of said phase shifter; and
said comparator output going from l to 0 when said integrator output corresponds to said control voltage and said predetermined flux level in said phase shifter and turning off said set pulse. 7. The system of claim 6, wherein said feedback loop includes a phase inverter for inverting the phase of said voltage across said phase shifter in order to produce a signal of proper phase to actuate said reset generator or gate and said set generator integrator.
8. The system of claim 7, including: a second or gate having first and second inputs; said first input being connected to the output of said set generator and gate and said second input being connected to the output of a differentiator;
said differentiator having an input connected to the output of said reset generator or gate;
said differentiator delivering a pulse in response to the trailing edge of said reset generator or gate signal;
said or gate responsive to said differentiator signal having an output connected to said reversing switch; and
said voltage amplifier output being a spike, responsive to said second or gate signal and being of opposite polarity relative to the reset driving signal.
9. The system of claim 8, wherein said reversing switch includes selector switches programmed in response to external signals corresponding to the trans mission and the receive mode of said antenna array; and
said system includes a dump circuit having its output connected to said integrator and causing said integrator output to go to 0 in response to a reset gate pulse at said dump circuit input.
10. The system of claim 9, wherein said voltage amplifier includes:
a first voltage amplifier having a negative polarity output and said second voltage amplifier having a positive polarity output;
said first voltage amplifier producing said output for driving said phase shifters to saturation for the transmission mode and to said predetermined flux level for the receive mode; and
said second voltage amplifier driving said phase shifters to said predetermined flux level subsequent to saturation, for the transmission mode and to saturation for said receive mode.
11. The system of claim 9, wherein said voltage amplifier includes: u
a first voltage amplifier having a positive polarity output and said second voltage amplifier having a negative polarity pulse;
said first voltage amplifier producing said output for driving said phase shifters to saturation for the receive mode and to said predetermined flux level for said transmission mode; and
said second voltage amplifier driving said phase shifters to said predetermined flux level subsequent to saturation, for said receive mode and to saturation for said transmission mode.
127 A method for producing a predetermined magnetic flux level in a magnetic analogue phase shifter in a phased array comprising the steps of:
driving the phase shifter to saturation; and
reversing the current to said phase shifter and driving said phase shifter to the predetermined flux level.
13. The method of claim 12, wherein said step of driving said phase shifters to saturation includes the step of sensing the flux level of said phase shifter and terminating said saturation driving current in response to said phase shifter reaching saturation; and
said step of driving said phase shifters to said predetermined flux level including the step of sensing the flux level of said phase shifters and terminating the current of said phase shifters when the predetermined flux level is reached.
14. The method of claim 13, wherein said phase shifters are driven in a first direction to saturation and said phase shifters are driven in a second direction opposite the said first direction to establish said predetermined flux level.
15. The method of claim 14, including the steps of reversing the polarity of the driving current for saturation and of the current for driving the phase shifters to a predetermined flux level, relative to the transmission and receiving modes.
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|US2822511 *||Jun 22, 1955||Feb 4, 1958||Crawford Jack A||Magnetic integrator|
|US3237088 *||Aug 17, 1961||Feb 22, 1966||Maxson Electronics Corp||Current regulator for inductive loads|
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|U.S. Classification||361/152, 342/372|
|International Classification||H01Q3/30, H03K3/00, H01Q3/34, H03K3/78|
|Cooperative Classification||H03K3/78, H01Q3/34|
|European Classification||H01Q3/34, H03K3/78|