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Publication numberUS3713885 A
Publication typeGrant
Publication dateJan 30, 1973
Filing dateMar 2, 1970
Priority dateMar 6, 1969
Also published asDE2010264A1
Publication numberUS 3713885 A, US 3713885A, US-A-3713885, US3713885 A, US3713885A
InventorsBetremieux P, Feissel H, Gallard J, Lagadec I
Original AssigneeHoneywell Bull Soc Ind
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory matrix and its process of fabrication
US 3713885 A
Abstract
A memory matrix and the process for fabricating said matrix, wherein a conductive array is formed of two mutually orthogonal and insulated sets of parallel conductive metallic bands, each band being formed of two superposed conductive strips, the lower strip of each band of the first set passing through an opening in the lower strip of each band of the second set and the upper strip of each band of the second set passing through an opening in the upper strip of each band of the first set, and wherein coupling elements selectively couple bands of one set to bands of the other set.
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United States Patent m1 Betremieux et al.

1111 3,713,885 [451 Jan. 30, 1973 [54] MEMORY MATRIX AND ITS PROCESS OF FABRICATION [75] Inventors: Pierre Arthur Betremieux; Henri Gerard Feissel; Jean Hilaire Gallard; Isidore Lagadec, all of Parris, France v [73] Assignees Societe lndustrielle Honeywell'Bull,

Paris, France [22] Filed: March 2, 1970 [2]] Appl. No.: 15,651

[30] Foreign Application Priority Data I March 6, 1969 France ..6906298 [52] U.S. Cl. ..';....ll7/2l2,- 29/625, ll7/2l7 [5]] Int, Cl. .LB44d l/00 [58.] Field of Search .....l56/3; l 17/212, 2l7; 29/604,

[56'] t References Cited UNITED STATES PATENTS 3,540,954 I i/I970 iiiiciiaiaj irfetaln ..l56/3 I 8/l970 Bingham ..l l7/2l2 X 3,525,617 3,366,519 H1968 Pritchard, .lr. et al ..l56/3 3,055,775 9/1952 Crittenden, Jr. et al ..1 17 217 x Primary ExaminerAlfred L. Leavitt Assistant Examiner David A. Simmons AltorneyLewis P. Elbinger, Fred Jacob and Ronald T. Reiling [57] ABSTRACT A memory matrix and the process for fabricating said matrix, wherein a conductive array is formed of two mutually orthogonal and insulated sets of parallel conductive metallic bands, each band being formed of two superposed conductive strips, the lower strip of each band of the first set passing through an opening in the lower strip of each band of the second set and the upper strip of each band of the second set passing 7 through an opening in the upper strip of'each band of the first set, and wherein coupling elements selectively couple bands of one set to bands of the other set.

8 Claims, 8 Drawing Figures PATENTEDJAH so 1915 3. 7 l 3; 8 85 sum 1 or 3 PATENTED JAN 3 0 I973 SHEET 3 OF 3 MEMORY MATRIX AND ITS PROCESS OF FABRICATION BACKGROUND OF THE INVENTION Memory matrices are known which comprise word lines and bit lines, wherein one part consists of metallic bands carried by an insulating support and crossing each other at right angles, and another part of coupling elements such as resistors, capacitors, diodes, etc., coupling certain bit lines to certain word lines, the two parts being disposed respectively in parallel planes separated by a layer of insulating material.

It isknown that a realization in thin films permits increasing the density of information capable of being contained in a memory (because it is possible to obtain a very large number of components on the same substrate) and reducing the time of response and the intensity of the control current, which is particularly advantageous for electronic computers.

Such matrices, realized in the form of thin films, present a great disadvantage. ln effect, in this instance, the metallic bands, of copper for example, have a thickness of only a few microns, whereby they have a high resistance which is prejudicial to transmission of electrical signals.

Therefore, the object of the present invention is to alleviate this disadvantage. Accordingly, the invention relates to a memory matrix realized of thin films, and its process of fabrication.

In accordance with the invention,jthe memory matrix comprises of one part having first andsecond sets of parallel lines formed of metallic conducting bands disposed on an insulating plane support in such a manner that each line of one of the sets crosses at right angles and is insulated from all of the lines ofv the other set, and of another part having coupling elements which couple certain lines of one of the sets to certain lines of the other. The invention is characterized in that each of the metallic bands comprises at least two superposed strips and wherein, at the crossing points of the bands, the lower strip of one line of the first set is provided with a firstopening through which passes the lower continuous strip of one line of the second set and the upper strip of said line of the second set is provided with a second opening through which passes the continuous upper strip of said line of the first set without being in electrical contact with the lower continuous strip of said line of the second set. I

Thus, at the crossing points the bit lines are insulated from the word lines, whereas between the crossings each line is formed of at least two layers. The transmission resistance of the lines is therefore reduced and, in the instance of the'band having two superposed layers, practicallydivided in half in relation to known matrices Obviously, the thickness of each strip once being chosen, the number of superposed strips'of a band is determined to provide the desired conductance value of aline.

Preferentially, in order to avoid all extraneous contact, the matrix comprises, at each crossing point, a small insulating plate disposed between a continuous strip of the line'of one set and a continuous strip of the line of the other set. Moreover, the portionsof the first opening formed between the lower strips of the two bands which cross are filled with an insulating material.

Advantageously, the matrix in accordance with the invention may be obtained by known techniques of deposition and of removing portions of thin films on an insulating support.

According to the invention the process for realizing on an insulating plane support a matrix such as specified above is characterized in that there is coated uniformly on such support a first conductive layer and then there is cut in this layer first notch couples, substantially parallel, distributed according to a pattern of 1 rectangular meshes. Next, each portion of the first layer which is between the two notches of a couple is covered, overlapping at its two edges, by an insulating plate, followed by coating everything with a second conductive layer. Next, in the two conductive layers are etched the bands of the two sets of lines in such a manner that, on one hand, the bands of the first set havefor their lower strips the portions of the first conductive layer included between aligned and adjacent notch couples and, on the other hand, the bands of the second set are orthogonal to the bands of the first set, the upperstrips' of the first set passing over the first notch couples and the insulating plates, after which there is cut in the upper strips of the bands of the second set, second notch couples disposed on each side of the upper strips of the bands ofthe first set.

Thus, the first and second notch couples form respectively the first andsecond openings mentioned above;

Advantageously, the coupling elements between the word lines and the bit lines are resistors. It is then possible to deposit on the insulating support, prior to'the deposit of the first conductive layer, a layer of electrically resistive material, after which there is cut inthe two layers the first notch couples. Then, after having put in place the insulating plates and covered everything with a second conductive layer, there is etched, simultaneously with said bands, in the two conductive layers and the resistive layer, a lamella having a pattern connecting, in each of the rectangular meshes, one band of one set toone band of the other, and passing substantially through the center of the mesh. Then there is formed the second notch couples and there is eliminated, at least partially, the portions of the two conductive layers covering the lamellae.

Thus, in each mesh there is a resistor which connects a word line to a bit line. It is then necessary, in order to write into ;the memory (encode) the desired information, to destroy certain of these resistors. To effect this, the matrix is then covered with a protective insulating layer having a window at the center of eachmesh, the area of the window being substantially less than that of the mesh.

Therefore, by covering the matrix with a layer of photosensitive lacquer and then an appropriate mask, and by exposing with a lamp those portions of the matrix not hidden by the mask, it is possible to seal certain of the windows. It is sufficient thento subject the matrix to e an etching bath for destroying resistors by eliminating what appears through the non-sealed windows and, therefore, writing information conveniently.

At the time of such writing, errors may be committed. Moreover, it may be desired to modify, afterward, the information written. To effect this, the matrix comprises supplementary word lines coupled to corresponding bit lines through resistors such as specified above, in series with a strip, for example of the same material as the resistor, easily fusible by a high intensity current.

Thus, by causing the passage through these fusible strips of an appropriate current, it .is possible to eliminate one by one in a convenient manner, the couplings between word lines and bit lines.

Advantageously, enlarged pads of the same material as these fusible strips are disposed at the extremities of the fusible strips, in order to facilitate the application of the high intensity current for the elimination of such strips.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the accompanying drawing, wherein:

FIG. 1 is a view, in perspective and to a large scale, of one embodiment of the memory matrix of the invention;

FIGS. 2 to 7 illustrate different stages in the process of fabrication of a memory matrix in accordance with the invention; and

FIG. 8' is a schematic view of a memory matrix providing supplementary lines in accordance with the invention. I

DESCRIPTION OF THE PREFERRED EMBODIMENT The portion of the memory matrix shown in FIG. 1 comprises, arranged on an insulating plane support 1, word lines 2 and bit lines 3. The word lines are mutually parallel, as are the bit lines which are orthogonal to the word lines, Thus, between two adjacent word lines and two adjacent bit lines is determined a rectangular mesh 4, in the interior of which is disposed a coupling element, constituted in this memory matrix of a resistor formed of resistive lamella 5 coupling a word line 2 to a bit line 3. These lamellae 5 have a sinuous pattern and pass substantially through the center of meshes 4.

Each word line 2 is a conductive metallic band formed of two superposed strips 6 and 7. Similarly each bit line 3 is a conductive metallic band formed of two superposed strips 8 and 9. The extremities of each lamella 5 are respectively affixed to the resistive strips 10 and 11 underlying bands 2 and bands 3 and in electrical contact therewith.

At each crossing of a band 2 and a band 3 the strip 11 and lower strip 8 of a band 3 comprise an opening 12 through which passes, without contact with the latter, the strip 10 and the lower strip 6 of a band 2. Similarly, at each of these crossings, the upper strip 7 of a band 2 comprises an opening 13 through which passes, without contact with such strip 7, the upper strip 9 of a band 3.

Thus, bands 2 and strips 10 are insulated from bands 3 and strips 11. In order to prevent any extraneous contact between strips 6 and 9, smallinsulating plates 14 are disposed between them.

One such matrix or a similar matrix can easily be obtained by employment of the process described hereinafter in regard to FIGS. 2 5. This process utilizes techniques well-known in photoengraving. Therefore, all the operations obvious to the specialist, the cleaning, the formation of the masks in photosensitive lacquer, the etching of the'deposited layers, etc., are not described.

There'is coated successively, for example by depositing under vacuum, the plane surface of an insulating support 1 with a uniform resistive layer 20 (for example, a layer of chromium of which the resistance can be of the order of ohms per square), and then with a first conductive layer 21 (for example, of copper).

In these two superposed layers 20 and 21, there is cut (see FIG. 2) notch couples 22 and 23, substantially parallel, leaving between them the portions 24 of layers 20 and 21. These couples are distributed in a manner to form'a pattern of rectangular meshes 4 (of which one is shown in FIG. 2). Next, each portion 24 is covered with a small insulating plate 14, which overlaps portion 24 at its two edges (FIG. 3). These insulating plates 14 are provided advantageously from an insulating layer, for

example a varnish, uniformly deposited on layers 20' and 21 and cut out by photoengraving. This mode of realization presents the advantage of permitting the filling in of notches 22 and 23 with an insulating mass,

which, as will be shown later, facilitates the isolation of the word lines and bit lines at each crossing.

After putting in place plates 14, support I is recovered (for example by deposition in a vacuum) with a second conductive layer, and then the three layers (the resistive layer and the two conductive layers) are etched to form the bands of the two sets of lines and the coupling resistors between the bit lines and word lines.

Bands 2 of the word lines are etched in a manner such that their lower strips 6 consist of the portions 24 of the first conductive layer 21 comprised between aligned notch couples 22 and 23 and the portions of layer 21 joining such portions 24. Bands 3 of the bit lines are etched'orthogonal to bands 2, in, a manner such that their upper strips 9 (etchedin the second conductive layer) pass over notch couples 22 and 23 and over insulating plates 24.

Thus, the lower strips of lines 2 and 3 are insulated at each crossing by a notch couple 22 and 23. In order to insulate the upper strips of these lines, notch couples 25 and 26, disposed on both sides of the upper strips of bands 3, are cut in the upper strips of bands 2.

At the time of etching of bands 2 and 3, there is also created under such bands, bands 10 and 11 of the resistive material of the layer 20. There is etched similarly, in the two conductive layers and the resistive layer, a band 50, having a pattern which connects in each mesh 4 a band 10 to a' band 11 (these bands 50 being in electrical contact with bands 2 and 3) and which passes substantially through the center of the mesh.

In order to prevent a short-circuit between lines 2 and 3, portions of the two conductive layers of band 50 which cover lamellae 5, are eliminated at least partially. To effect this, the plane support is covered again with a layer of photosensitive lacquer 27 (FIG. 5) comprising windows 28, which expose at least partially bands 50. The exposed portions of band 50 are subjected to the action of anetching bath which etches away the two conductive layers without attacking the resistive layer. Then layer 27 is removed.

As has been described above it is necessary, in order to encode the memory matrix in a desired manner, to destroy certain of resistors 5. To provide for the destruction of selected ones'of resistors 5, the matrix is now covered with a protective insulating layer 29 comprising a window 30 (FIG. 6) in each mesh 4, through which is exposed a portion of a resistor 5. The area of each window is substantially less than that of the mesh.

It is then possible for encoding the matrix to cut the selected resistors, either by punching or by etching portions of resistors 5 exposed by windows 30. For encoding the matrix, it suffices to cut the lines of connection of resistors 5, and therefore only the lines of connection appearing in windows 30.

Preferably, for destroying those resistors which must be cut to encode the matrix, the matrix is covered again with a layer 31 of photosensitive lacquer (FIG. 7) and then with an appropriate mask 32 hiding certain meshes 4. By exposing those portions of the matrix not hidden by mask 32 and then by eliminating the parts of layer 31 not polymerized, it is possible to seal certain windows 30 and to leave others open. Then the matrix is subjected to an etching bath for eliminating those resistors 5 not protected by the polymerized portions of layer 31.

Among the operations described above, those which precede the encoding operations serve for preparing matrices which do notdiffer; i.e., which in principle, are identical. Unique equipment may be utilized for these operations. The precision with which the essential characteristicsof these memory matrices will be obtained by means of such equipment depends on the precision with which such equipment is realized and utilized.

The encoding operations which permit the realization, starting from identical matrices, of matrices with different codes requires the creation of as many different masks 32 as the different .codes desired. It is advantageou's, consequently, i f masks 32 can be realized and utilized with the greatest possible tolerances, and it is for this purpose that, as has been indicated previously, the area of windows 30 should be substantially less than thatof the meshes. Thus, if the portion of the mask 32 intended to cover a mesh has approximately the same dimension as such mesh, the tolerance in dimension and position of this portion of mask 32 in a given direction is proportional to the difference between the dimension of the mesh and that of the corresponding window in the direction considered. It is therefore advantageous to reduce as much as possible the dimensions of windows 30 in order to increase the realizable tolerance and the'utilization of mask 32.

The encoding of the matrix may therefore be accomplished by eliminating at one time all of the resistors not desired. Nevertheless, in order to compensate for encoding errors or to modify the code, it is advantageous to provide supplementary word lines connected to bit lines through couplings able to be cut at will after the encoding.

To provide this capability, the supplementary word lines 2 are connected to .bit lines 3 by resistors 5 in series with a fusible strip 33 (for example of the same material as that of resistors 5), FIG. 8. Enlarged pads 34 and 35 are provided on each side of strip 33.-Therefore, therev can be applied to pads 34 and 35 the contacts of a generator delivering a current of sufficient intensity for volatizing the corresponding strip 33.

The description which has preceded relates a memory matrix in which the coupling elements are resistors. Memory matrices in accordance with this invention, in which the coupling elements are not resistors, do not permit the resistive strips 10 and 11 underneath the respective word lines 2 and bit lines 3. They can be, therefore, realized with the aid of a process similar to that which has been described above, but not involving the operation of depositing a uniform resistive layer 20 on insulating support 1 prior to the deposit of the first conductive layer.

It is apparent that modifications may be adduced from the embodiments which have been described, particularly through the substitution of equivalent techniques and means, without departing from the heart of the present invention.

We claim:

I. In a memory matrix comprising first and second sets of parallel lines, formed of conductive metallic bands disposed on an insulating plane support in a manner such that each line of one set crosses at right angles to and is insulated from all lines of the other set,

and means for coupling predetermined lines of one set to predetermined lines of the other set, wherein said means comprises lamallae of resistive material in series with a strip which is easily fusible by high intensity current applied to its extremities, the improvement wherein each of said bands comprises at least two superposed strips, and at the crossing points of said bands, the lower strip of one line of said first set is provided with a first opening through which passes the structurally continuous lower strip of one line of said second set, and the upperstrip of said line of said first set, and means for insulating said continuous lower and upper strips one from the other disposed between said continuous strips of the two sets at the crossing point.

2. The memory matrix of claim 1 wherein said lamallae of resistive material form resistors.

3. The memory matrix of claim 1, wherein said insulating means comprises a small insulating plate disposed between the continuous strips of the two sets, such that the portions of saidfirst opening disposed between the lower strips of the bands which cross are filled with an insulating material.

4. The memory matrix of claim 1, further comprising an enlarged pad disposed at the extremities of each of said fusible strips.

5. The memory matrix of claim 1, further comprising an insulating layer provided with windows through which appear at least partially said coupling means or the lines of connection of said coupling means.

6. A conductive matrix comprising: first and second sets of conductive metallic bands, each band of one of said sets crossing and being insulated from all bands of the other set, each band being formed of two superposed conductive strips, the lower strip of each band of said firstset being provided with first openings through which pass respective continuous lower strips of the bands of said second set, and the upper strip of each band of said second set being provided with second openings through 'which pass respective continuous upper strips of the bands of said first set, and means for coupling predetermined bands of one set to predetermined bands of the other set, said coupling means comprising lamallae of resistive material in series with a strip which is easily fusible by high intensity current ap-' plied to its extremities. l

' 3 ,7 l 3 ,8 8 5 7 r a 7. The memory matrix of claim 2, further comprising an enlarged pad disposed at the extremities of each of said fusible strips. l

8. The memory matrix of claim 2, further comprising. an insulating layer provided with windows through 5 v which appear at least partially said coupling means or the lines of connection of said coupling means.

Patent Citations
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US3055775 *Jun 10, 1960Sep 25, 1962Space Technology Lab IncSuperconductive switching component
US3366519 *Jan 20, 1964Jan 30, 1968Texas Instruments IncProcess for manufacturing multilayer film circuits
US3525617 *Jul 8, 1966Aug 25, 1970Int Computers & Tabulators LtdMethod of making electrical circuit structure for electrical connections between components
US3540954 *Dec 30, 1966Nov 17, 1970Texas Instruments IncMethod for manufacturing multi-layer film circuits
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4112496 *Feb 18, 1977Sep 5, 1978Sanders Associates, Inc.Capacitor matrix correlator for use in the correlation of periodic signals
US20050018495 *Jan 29, 2004Jan 27, 2005Netlist, Inc.Arrangement of integrated circuits in a memory module
WO2004093092A1 *Apr 16, 2004Oct 28, 2004Infineon Technologies AgMagnetic memory cell including a fuse element for disconnecting the defective magnetic element
Classifications
U.S. Classification361/679.31, 361/761
International ClassificationG11C17/00, G11C29/00
Cooperative ClassificationG11C29/78, G11C29/832, H05K999/99, G11C17/00
European ClassificationG11C29/78, G11C29/832, G11C17/00