US 3728681 A
The method of configuring communication units, all of which are connected in series on a loop such that some units may take priority and communicate out of the logical sequential order. This is accomplished using a master unit and first and second sets of slave units. The slave units respond to poll requests. These polls may come either from the master or the previously responding slave unit. The master unit always sends a prepoll before a poll. The first set of slave units will respond to a prepoll or a poll and thus can take priority in transmitting messages. The second set of slaves will respond only to a poll, internally set a flag, and then transmit a poll to further slave units upon receipt of the next prepoll.
Claims available in
Description (OCR text may contain errors)
Unite States Patent Fuller et al.
DATA LOOP COMMUNICATION PRIORITY ESTABLISHING APPARATUS Inventors: Ray C. Fuller, Cedar Rapids; Gary D. Phillips; Richard B. Simone, both of Marion, all of Iowa Collins Radio Company, Dallas,
Filed: Jan. 6, 1972 Appl. No.: 215,808
References Cited UNITED STATES PATENTS 3/1' Is'9"""1 'e'isii'..Y.LT.I..I.' "11540063 SEQUENCE CONTROL LPBSY LISTP 'POLDEL OPCNT BUFFER CONTROL RDTDEL ADDRESS STRAP 350 Primary Examinerl-larold l. Pitts Attorney-Bruce C. Lutz et al.
[5 7] ABSTRACT The method of configuring communication units, all of which are connected in series on a loop such that some units may take priority and communicate out of the logical sequential order. This is accomplished using a master unit and first and second sets of slave units. The slave units respond to poll requests. These polls may come either from the master or the previously responding slave unit. The master unit always sends a prepoll before a poll. The first set of slave units will respond to a prepoll or a poll and thus can take priority in transmitting messages. The second set of slaves will respond only to a poll, internally set a flag, and then transmit a poll to further slave units upon receipt of the next prepoll.
BIT COUNTER RESET PARCHK PARSCD PARITY CHECK CIRCUITS PATENTEUAFR 1 mm Cir um! T d3 3% mm mm mm H 8m Sm k: 1 Dow. IFQ\ lg 54 d3 1 Q03 v g $73196 w? 8 303 wow mi E 2 82 1 f l m m 3 55 Q Gm E w T E 092 .EJ Mi tlml .N mm vw ow :mm SJ 3w m 32 QM 7 W m mm o PATENTED mmms 3.72
sum 09 0F 13 POC TSI L POLDEL-RDYCAL- POLDEL-RDYCAL- POLDEL-L TT 3 DATO DEL D DAT RS LAST-RED D DATOUT=DAT|N L D DATOUT= l I) DA 1 DATIN OUT=RESP I) DATOUT DEL I) RS RSCNT+ I CNT'-O RESDEL 3 RSCNT"-O T84 POLDEL'RDYCAL-LACST CNTEN= I DATOUT= REGDAT REG I PARC = EGD PAR UT DATIN POLDEL3+RED-POLDEL RED-POLDEL D DATO POLDEL CNTEN= DATOUT REG DAT REGCKE=| POLDEL) PARCK RE DAT PA N=DATOUT ED 3 LA POLD STS= I POLD DATOUT= DATI N T824 DATOUT= DATl N POLDEL 4 E T85 DATOUT=RESP RSCNT-- RSCNT T825 0 O DATOUI:"=DATIN 4 F I G 5A LASTR l TT =-RESDEL-(POLDEL+ LAST- RDYCAU' G9 (SENPOL+ RDYCAL+POL| N) DATA LOOP COMMUNICATION PRIORITY ESTABLISHING APPARATUS The present invention is generally related to electronics and more specifically related to communication switching system.
A co-pending application in the name of L. D. Hungerford et al. Ser. No. 208,548, entitled Direct Switch System, filed Dec. 16, 1971, having the designation 4,064 and assigned to the same assignee as the present invention describes a communication system wherein a plurality of units connected serially on a loop respond to a poll signal originated at a control unit prior to sending messages. As will be realized, the devices closest to the control unit are most likely to receive the poll signal and thus may, in heavy traffic, prevent devices much further around the loop from ever receiving a poll so that they may transmit communications.
The communication problem of later units may be solved by requiring each unit to forward the poll to the next unit after completion of a single transmission. This is basically the way the problem is solved on the intermediate exchange loop of the above-referenced Collins application. However, the local exchange loop is designed such that a'master or control unit is allowed to regain control of the loop between each message or communication for the purpose of interjecting messages into the loop for reception by units on the loop. This is necessary to prevent tie-up or clogging of the main or high speed loop.
This is solved, according to the present invention, by having the slave units on the local exchange loop respond only to a poll signal. The control unit will initially send a prepoll which, if unanswered, will result in the sending of a poll signal. The first unit to respond with a communication will set an internal flag so that the reception of the next prepoll signal by the control unit will result in an output of a poll signal from that slave unit. Thus, the poll will be forwarded to the next unit on the loop desiring to communicate. The control unit may at any time delay sending further prepoll signals and instead supply messages to units on the loop. When no further messages are forthcoming from the control unit, it can then send further prepolls which will be changed to polls by the last unit to transmit a message and this poll will continue around the loop to the originating control or master unit.
One or more of the slave units may be given priority whereby they will respond to either a prepoll or a poll in the transmission of messages. It will be realized, however, that too many of these priority units will cause the same clogging conditions in the local exchange loop as occasionally happened previously and which the present invention was designed to eliminate or substantially reduce.
It is therefore an object of the present invention to provide a priority and non-priority situation in polled loop connected units.
Other objects and advantages of the invention will be apparent from a reading of the specification and claims in conjunction with the drawings wherein:
FIG. 1 is a block diagram of an overall direct switching communication system as more completely described in the above referenced co-pending application and which may advantageously embody the present invention;
FIG. 2 is a block schematic diagram of a receive module portion of a SCU or other unit connected to the local exchange loop of FIG. 1;
FIGS. 3A-3E illustrate the flow diagram applicable to the apparatus of FIG. 2;
FIG. 4 is a block diagram of the transmit module portion of a SCU or other device connected to the local exchange loop of FIG. 1; and
FIGS. 5A-5E are flow diagrams applicable to the transmit module of FIG. 4.
DIRECT SWITCHING APPARATUS OF FIG. 1
A more detailed description and understanding of FIG. 1 may be obtained from the above-referenced patent application. However, in general the apparatus of FIG. 1 provides communication between any units on a specific loop such as the local exchange loop 86 and communication between SCUs and 108. This is accomplished by having the master control unit 78 transmit a poll which is received by one of the SCUs which wishes to transmit a message. This unit then transmits the message in response to the received poll. The transmitted message contains an address which is decoded by the appropriate receiving SCU who changes an acknowledge portion as appropriate before forwarding the message back to the original sender. If communications are desired between SCU's on different loops such as between loops 86 and 114, the SCU such as 100 will transmit a message in response to a receive poll and this message is stored in a buffer in MGU 78. MGU 78 changes the acknowledge section of the message to indicate to SCU 100 that a successful reception has occurred. MGU 78 then awaits a turn on intermediate exchange loop 68 so that it may transmit the recently received message to MGC 64. After MGC 64 receives and acknowledges its message, it calls an appropriate station such as on local exchange loop 114 and provides station 120 with the message. After station 120 acknowledges receipt of the message, it returns a reply message to SCU 100, buffer by buffer, back through intermediate exchange loop IXL to local exchange loop 86. Then, SCU 100 transmits the next portion of the message.
As explained above and as will be apparent, the polls sent out by MGU will be received first by the closest SCUs such as 100 as illustrated. If SCU 100 has a large quantity of messages to transmit, it is conceivable that a poll will never reach SCU 108 and it could not provide communications. Thus, as explained in the succeeding flow diagrams, MGU 78 supplies a prepoll on line 86 which comprises a logic 1 followed by a predetermined number of Os. This prepoll is not recognized by SCU 100 unless an internal flag is set due to it being the last SCU unit to send a message. In this instance the prepoll is changed to a poll which comprises two logic 1 bits. The following SCUs such as 108 may now receive this poll signal sent by 100 and respond thereto. This poll signal will continue around the loop until received by a SCU having a message to transmit or by MGU 78. Any following unit having a message to transmit will likewise later change the next prepoll from the control unit to a poll and forward this poll around the loop for use by any later units. When the poll is finally forwarded to MGU 78, it realizes that all SCUs on the loop have had the opportunity to transmit a message and it thus sends a new poll so that the sequential transmission by all SCUs containing messages can continue.
RECEIVE CONTROL MODULE FIG. 2
FIG. 2 illustrates the receive control module found in the LRT sections of the various units of FIG. 1. As will be noted in the referenced patent application, there are two receive control modules in the master group control block and one in each of several other blocks.
As indicated on the left-hand side of FIG. 2, there are leads coming from and going to the RGT interface as well as leads coming from and going to the buffer sections of the appropriate devices and leads going to and coming from the transmit control section. Within the FIG. a J-K flip-flop 350 is illustrated as well as a sequence control unit 352, and operator register 354, an address register 356 and a response register 358. Cables are utilized to connect the last three referenced registers to operator decode 360, address compare 362, and response decode 364, respectively. In addition a parity check circuit 366 is illustrated along with an operator counter 368, a bit counter 370, and a bit count decode 372. It should be realized that other polynomial check codes may be used other than parity and that further references to parity are by way of example only. A receive data (RXDAT) supplies input data from the RGT to a .I input of the J-K flip-flop 350 and through an inverting circuit to the K input of .l-K flip-flop 350. A loop clock input supplies data through an inverter to the C or clock input of flip-flop 350 as well as to blocks 352-358 and 366-370. The bit sync and initialization sequence inputs are supplied to the sequence control block 352 and a transmit enable is supplied from control block 352 to the RGT. The leads to and from the buffer portion of the particular unit in which the receive control module is utilized are, respectively, BUFS (bufferfull set), RDTDEL (receive data delimit), and CD (control/data) each of which is obtained from sequence control 352. Another line to the buffer unit is a data lead which is obtained from the output of J-K flip-flop 350. The J-K flip-flop 350 provides the one-half bit delay, which was previously mentioned, by having the loop clock 180 out of phase with the received data. A further J-K flip-flop in FIG. 4 provides a further half bit delay in the same manner in the transmit control module to produce the one full bit delay for each module connected to a loop. The data lead from f/f 350 is also supplied to blocks 352358 and 366 and is output to the transmit control block. Two leads labeled RBSCD and RBSCC (receive busy select call data and receive busy select call control, respectively) supply signals from the buffer portion to the sequence control unit 352.
From the transmit control block a single input is received labeled XMTAC (transmit active). This transmit active lead is supplied to the sequence control unit which returns five signals to the transmit control block of FIG. 4 via leads POLDEL, SENPPOL, DATA, RESDEL, and AKCON. These last referenced leads refer to poll delimit, send prepol, data, response delimit, and acknowledge/connect, respectively. A further lead from the sequence control is the LPBSY (loop busy) lead when the receive control module is being used in certain units.
The operator register 354 receives an additional input QPSC (opcode register shift control). The address register 356 also has an additional input ADRSC (address shift control). The operator decode has six outputs supplied to the sequence control 352. The first two are call control and call data (CLCTRL and CL- DATA, respectively). The next is a signal which indicates that it is neither a call control or a call data (CLCTRL'CLDATA). Two further inputs from the operator decode supply a signal for connect control or connect data (CNCTRL and CNDATA, respectively). Finally, a signal is supplied indicating that the input decoded is neither a connect control or a connect (CNCTRL-CNDATA).
The address compare 362 supplies a single input labeled ADRCOMP to the sequence control 352. The response decode 364 supplies three inputs to sequence control 352 of acknowledge/connect (AKCON), negative acknowledgement/busy (NAKBSY), and neither of the above (AKCONNAKBSY). The parity check circuit 366 was previously indicated as receiving the loop clock and the data signal, and it also receives a reset input and a parity shift delimit (PARSCD) from the sequence control block. In addition a parity check output (PARCHK) is supplied from 366 to the sequence control 352. The operator counter 368 receives two control signals OPZO and OPCNE (operator zero and operator count enable, respectively). The sequence control unit 352 also supplies the operator the bit counter 370 with an input CNINC (bit counter clock line). The operator counter 368 returns an input to sequence control labeled OPCNT7 (operator count 7).
The bit counter 370 also receives an input CNZO which is the bit counter reset line. This input accomplishes the same result as the OPZO input to counter 368. The bit counter 370 supplies a multiple lead output to the bit counter decode 372 which provides outputs, upon the decoding of counts of 21, 22, 44, 53, 62, 93,103, 256, 1,046, 1,077, and 1,085, back to the sequence control 352.
In view of the extensive use in mnemonics in FIGS. 2 and 3, a mnemonic list is providedbelow as a simple reference to the mnemonics used in these two figures.
RECEIVE MODULE MNEMONIC LIST ACK (Acknowledge) Positive response field in a connect message. ADRCKE (Address Clock Enable) Enables called address transfer from receive module to transmit BUSY (Busy) Response field in a SELECT call message which indicates to the receive module that the called party is busy.
CD (Control/Data) Line from receive module which indicates the type of CONNECT block received. Logic 1 implies data; logic implies control.
CLCTRL (Call Control) SELECT call control field which indicates a control message will follow. (Operator code plus start bit l l 101 100) CLDATA (Call Data) SELECT call data field which indicates a data message will follow. (Operator code plus start bit l 1 10001 1) CNCTRL (Connect Control) CONNECT message supervisory opcode. (Operator code plus start bit 11110000) CNDATA (Connect Data) CONNECT message data opcode. (Operator code plus start bit 1 l l l l l l l CN0021 A bit counter decode of count 21.
CN0022 A bit counter decode of count 22.
CN0044 A bit counter decode of count 44.
CN0052 A bit counter decode of count 52.
CN0062 A bit counter decode of count 62.
CN0093 A bit counter decode of count 93.
CN0103 A bit counter decode of count 103.
CN0128 A bit counter decode of count 128.
CN1046 A bit counter decode of count 1046.
CN1077 A bit counter decode of count 1077.
CN 1085 A bit counter decode of count 1085.
CNlNC Bit counter clock line.
CNZO Bit counter reset line.
CONN (Connect) Positive response field in a SELECT call message.
CNT (Counter) Modulo 2048 counter to count message bits.
1N TSO (Initialization Sequence) Normally a logic 0." Generates a one shot logic 1 after 1537 zeros have been counted on the line.
LPCLK (Loop Clock) Clock line from Regenerative Tap (RGT).
LISTP (Local-Intermediate Loop Strap) Logic 1" enables MGC poll generator for local loop polling.
LPBSY (Loop Busy) Indicates receive module may be in the process of receiving a call.
NAK (Negative Acknowledgement) response field in a CONNECT message.
NAKBSY Indicates negative response to reception of any message.
OPCNE (Opcode Counter Enable) Enables the modulo 8 counter 368 to incrementj OPCNT (Opcode Counter) Modulo 8 counter 368.
OPCNT7 Decoded count '7 of operator counter.
OPSC (Opcode Register Shift Control) Enables the loading of an 8-bit opcode register.
PARCHK (Parity Check) Signals good message pari- PARSCD (Parity Shift Delimit) Delimits parity check field.
PLA (Poll Active) Enables poll delimit to be sent to the transmit module when a poll is detected.
POC (Power On Clear) Establishes all initial conditions for receive module during system connection.
POLL (Poll) Signal for activating non-priority loop devices (Operator code 1000000) Negative POLDEL (Poll Delimit) Signal to delimit loop poll condition to the transmit module.
PREPOLL (Prepoll) Start bit signal for activating priority (Red) units and for alerting non-priority (White) units that they may be activated on the next message if they are in the next position on the loop after the last white unit to transmit. (Operator code plus start bit 10000000) RBSCC (Receive Busy Select Call Control) Busy to a SELECT call control message.
RBSCD (Receive Busy Select Call Data) Busy to a SELECT call data message.
RDTDEL (Receive Data Delimit) Signal which delimits the control parameters or data portion of a CONNECT message.
RESDEL (Response Delimit) Signal which delimits response field to the transmit module.
RXDAT (Receive Data) Data line from RGT.
SENPPOL (Send Prepoll) Requests the transmit module to send a prepoll signal or start bit.
TE (Tap Enable) synchronously routes data from regenerative tap unit (RGT) to receive module after POC.
XMTAC (Transmit Active) Signal which delimits the condition which implies that the transmit module has sent a SELECT call message.
The purpose of the receive module is to take the incoming message and check its operator, address and response portions to determine the type of message being received along with checking its parity to make sure there are no mistakes in the message before transferring the message into the data buffer and/or indicating to the transmit control section of the LRT to send a return response of ACK, NAK, etc. The message used in one embodiment of the invention comprised first a start bit of one digit, an operand or operator code of seven digits, a called address vector of 24 bits, a data portion of either 40 or 1,024 bits depending upon the operator portion, a check field of 24 bits, and a response field of 8 bits. The 40-bit data field is utilized for control messages while the 1,024-bit data field is used for data messages. The operator register 354 is enabled from the OPSC input and the output is decoded via decode block 360 which provides an input to sequence control 352. The address register 356 is enabled by the output ADRSC for comparing the received address with the address supplied from the address strap input to address compare circuit 362 to determine whether or not the address is the same as the present station. The address strap is used so that the address of a station can be changed to any given call code.
The response register 358 continuously receives input data and the output is merely ignored until the proper time. This proper time is obtained by checking the operator to determine whether a call word is a data or control message and then using the bit count decode 372 and the operator counter 368 to determine the proper time to start checking the response decode and the ending of this check 8 bits later. Since the time at which parity check occurs depends upon the type of word, this circuit is also dependent upon the response obtained from operator decode 360. Thus, an input labeled parity shift delimit is utilized to enable the parity check circuit only during the proper time.
Returning to the address compare section it will be realized that if the station incorporating the receive control module is awaiting a call, the address should compare. However, if the station has just transmitted a call and is awaiting a return of that call to determine the response, the address will not compare.
The response register and its decode 364 are utilized to determine whether the call which is returned contains a busy or connect signal or an acknowledge or not acknowledge response. There will on occasion he a faulty return word wherein the response section is such that none of these responses is decoded. This bit of information is also provided to the sequence control unit. As will be ascertained from a study of the discussion in connection with FIG. 3, the sequence control utilizes this information also.
RECEIVE CONTROL MODULE FLOW DIAGRAM FIG. 3
Since the block diagram of FIG. 2 can be imple mented utilizing a plurality of logic circuits and registers and since these circuits can be implemented in such a variety of ways, it is believed that a flow diagram of the operation of FIG. 2 will provide more information to one skilled in the art. In this manner the apparatus can be easily programmed into a computer in practicing the invention. However, since the flow diagram is quite detailed, the physical circuit design will also be apparent from an understanding of the flow chart.
The flow charts of FIG. 3 are divided into five pages labeled 3A to 3E. Normally, a receive module is a passive unit although it is responsible for initiating a prepoll if it was the last device to react to a poll in its order of placement on the loop. A local-intermediate loop strap is utilized in a MGC to force a return to state 2 (RST2) whenever the device reaches a state indicated as AG as shown in FIGS. 38, 3D, and 3E. This strapping operation is performed upon installation of the device and is included to illustrate a universal embodiment even though not required as part of the explanation of the SCU unit operation which has the inventive subject matter of this application.
Referring now to FIG. 33, a POC or power on clear signal is supplied to state 44 after actuation of the device. The device will then set the tap enable to zero and pass to state 45.
In the present flow diagram and the remaining flow diagrams, it should be noted that the blocks for each state have upper and lower portions. The upper portion defines an immediate action upon state entry. The lower portion of the block defines a clocked action on exit from the state. The symbol denotes an action which occurs upon entering a state, or immediately thereafter, and exists only during the existence of that state. Thus, such an action cannot, by definition, occur during the bottom portion of a flow chart block. The symbol denotes a setting, which is often a flag or flip-flop setting, external to the flow diagram actions. This symbol is a permanent setting, which remains until set otherwise and can occur either upon entering (top part) a state or upon leaving (bottom part) a state. Thus, the receive module remains in state 44 as long as power on clear (POC) is present. The first clock occurring after POC is removed causes a change from state 44 to state 45. While the receive module remains in state 44, tap enable (TE) is set at logic 1. Upon completion of FCC during state 44, the device is ready to enter state 45 upon receipt of the next clock at which time TE is set to logic 0.
As will be noted, state 45 receives three other inputs besides the one from state 44. The device remains in state 45 until the initialization sequence (logic 1") is obtained from the RGT. Prior to this time the device remains in an idle or recirculating condition since the output of the initializAtion sequence quadrangle continually indicates that the inltialization sequence line is zero. On the simultaneous occurrence of a l and a clock signal to the sequence control, the device proceeds'to state 1. As the device passes through state 1 the poll active signal is set to one to enable a poll delimit signal to be sent to the transmit module when a poll is detected. The opcode counter 368 is set to zero and the loop busy output is set to zero. The device then passes to state 2 and idles there until a start bit is received indicating the possible commencement of data.
The character which looks like a backward C in both the upper and lower portions of the state 2 block should be interpreted in this specification to mean means the same as, or implies. Thus, upon each passage of the idling status through the data decision block the error check circuits are reset. Upon the occurrence of the start bit or first data bit the loop busy lead is set to a one, and the opcode register shift control and opcode counter enable are momentarily set to one.
In state 46 the second bit is examined at which time the count is set to zero. If the second bit is a zero it will proceed as a prepoll indication to state 47. If the second bit is a logic I, the device will know this is not a prepoll and is either a poll or a call. Thus, it will proceed to state 3. During the existence of state 46 the poll delimit line will be set to a one if the poll active flag is a one and the opcode register shift control and the opcode counter enable are momentarily set to a one.
Assuming the second bit is a logic zero, the device in state 47 will return the opcode counter 368 to zero and the loop busy output to zero. Further, the poll active slgnal is set to one if not previously set there.
If the second bit is a logic 1 thereby indicating that the received message is not a prepoll, the device in state 3 will examine the third bIt. If the third bit is a logic 1, the apparatus will realize that the received message is not a poll and will proceed to state 5. How ever, if the third bit is a zero, a poll is indicated and the device will go to state 4. In state 3, the opcode register shift control and opcode counter enable are again temporarily set to one. Further, if poll active is still a one from state 1 or is a one for some other reason, the poll delimit is set to a one.
Assuming the condition of the third data bit is a zero, the apparatus enters state 4 where the op count, and loop busy are again set to a zero while the poll active is set to 1" if zero or if already a l causes-the poll delimit to be set to a one. The device then returns to state 2 and again waits for a start bit. However, if the third bit is a one, the device knows that this is not a poll and proceeds to state 5. It remains circulating in state 5 until the operator counter 368 provides a count of 7.
On each clock bit through state the OPSC and OPCNE are et to a one temporarily. When the counter 368 reaches a count of 7, the device proceeds to state 6. This count of 7 is 7 plus the bit which allowed the apparatus to pass through the states 2 and 46. Thus, as the device reaches state 6, there are actually 8 bits or clock pulses since the first data bit was received.
It should be noted at this point that the operator counter must have already triggered the enabling mechanism to a count of 7 before it can detect such a count. Thus, it returns to state 7 after the count indication is 7 and upon leaving for state 6 it adds one more pulse thereby resetting the modulo 8 counter 368 to a logic 0 for later counts such as the count of 7 following state 29 in FIG. 3D and other portions in the flow diagram.
In state 6 the decoded output from operator decode 360 is checked by the decision boxes. if the operator decode provides anything other than a connect-control, a connect-data, or a call-control and call-data, the device will proceed to state 45. The passage through state 6 will activate the address register shift control lead to a temporary one even though the opcode indicates improper operation.
If the output from the operator decode 360 indicates a connect-control, the device will proceed to state 7. The bit counter 370 was started counting at the same time that operator counter 368. The device will stay in state 7 until bit counter 370 reaches a count of 104. At
this time the decode 372 provides an output which enables the device to change from state 7 to the decision block LISTP in FIG. 3D. If the unit is in a MGU, the device will proceed to state 43; and as it passes therethrough, will send a prepoll and return to state 1. However, in most installations the device will be strapped to a zero and the device will return to state 2 directly and await the reception of another data or start bit.
If the operator decode provided an indication of connect-data in the decision block of state 6, the device would proceed to state 8 where the device would remain in an idling or recycling state until the decode counter 372 reached a count of 1,086. The count of 1,086 is the length of a complete data message including the header, parity check, and response sections. Upon a count of 1,086 the device again proceeds to the decision block in FIG. 3D where it sends a prepoll or returns directly to state 2.
The reason for the MGU initiating a prepoll on the local exchange loop is to give it priority on sending messages. When the operator decode indicates that there is a CONNECT message on the loop, the MGU merely waits until the message has passed and sends a new prepoll so that further devices on the loop can respond with calls. If the MGU has a message from the intermediate exchange loop which it wishes to place on the local exchange loop, it merely withholds the prepoll bit and instead sends the message out to the appropriate device on the local exchange loop.
Later in the flow diagram the receive control module will react differently to a CONNECT message.
it will now be assumed, after returning to state 2, that a further message is decoded which is either a call-control or a call-data message. In this event the flow sequence leaves state 6 through the decision control block and proceeds to state 9 in FIG. 3B. The apparatus reaches state 9 at the time of the first bit of the called address portion of the data word. Thus, the address register shift control lead is set to a one and the bit counter is incremented for 22 bits until the bit count decode 372 supplies an output indicating that count 22 is reached. Upon receipt of this signal, the device moves to state 17. The address register is no longer activated since it is only activated long enough to admit 24 data bits into the address register. The 24 bits are obtained by one bit being entered from state 6 and 22 bits being entered from state 9 before the apparatus makes its final loop through state 9 and finds that the 22nd count occurred as it left the decision block with a no indication on the previous recycle. In other words, the count is incremented after the decision is made whether or not the count equals the desired amount. Thus, 23 counts are obtained from state 9 and one count is obtained from state 6 to make a total of the 24 counts for the called address vector.
It should be noted at this point that while both the operator counter 368 and the bit counter 370 were set to zero in state 46, the operator counter is already in cremented by the setting to one of the OPCNE lead in the upper portion of the various state blocks. The bit counter is already incremented by the CNT CNT l in the lower portion of the blocks. Thus, the count of 22 during state 9 had not been previously affected by the count indicated in state 5.
From the decision block indicating a count of 22 has been reached, the device now enters state 17 where it awaits an output from address compare 362. If the address compares, the device proceeds to state 26 on FIG. 3D. As it leaves state 17 the parity shift control delimit is temporarily set to one and since the address did compare the loop busy is set to a zero. If the address did not compare then, of course, the loop busy would be left alone. In state 26 the device idles or recycles for a number of bits while advancing the count register until on the 46th counted bit the device proceeds to state 27. As may be noted from FIG. 26 of the referenced application, a SELECT mode call may contain a parity check section for the 24 bits after the called address vector. Thus, an output is obtained from parity check circuit 366 and the sequence control determines whether the parity checked or did not check. If parity did not check the device proceeds directly to state 29. As may be ascertained from the lower portion of state 27 the occurrence of a parity not checking will reset the loop busy line to a logic 0." in state 29 the opcode counter enable circuit is temporarily set to one on each circle of the recycling device until a count of 7 is reached and then upon the next cycle the device proceeds to FIG. 3B and enters the strap decision block prior to state 42. If the device is anything other than a MGU, the apparatus will return to state 2 and again await an incoming data bit. However, if it is a MGU, the device will proceed to state 42 and wait for a count of 256. The error check circuits are reset on each cycle. If prior to count of 256 a data bit is detected, the device will proceed to state 3 of FIG. 2A. However, if no data bit is detected prior to count 256, upon reaching count 256 the device will proceed to state 43 on FIG. 3D where a prepoll will be sent and the device will return to state 2 to await the return of the prepoll, a poll, or a further data message.
Returning to state 27 it may be assumed that, instead of not obtaining a parity check, a parity check is obtained. If either RBSCC or RBSCD is a logic l along with an indication of parity check, the device will proceed to state 28. The raising of either of these lines indicates that the station is busy to any calls whether control or data.
In state 28 the response delimit is raised to a l as well as raising the operational counter enable to a l The device then proceeds to state 29 and continues as previously described to state 42 to send a prepoll if its a MGU or returns to await further data bits if the device is not a MGU.
If the parity checks and neither of the receive busy SELECT call lines are raised to a l, the device proceeds to state 30. It cycles through state 30 for seven counts until on the 8th count it passes to state 31. As before the 8th count returns the operator counter to a logic zero condition so that it may be operational for future counts. During each cycle the response delimit, the opcode counter enable, and the acknowledge/connect lines are placed in a logic 1" state.
The device then proceeds to state 31 where it awaits the receipt of additional logic bits. The raising of the acknowledge connect line in state 30 to a logic 1 supplied a signal to the transmit control block enabling it to supply the proper response in the final 8 bits of the SELECT mode call word to be returned to the calling de ice. The receive control block is now awaiting a CONNECT message from the calling device. When the device receives its first data bit the opcode counter enable and the opcode register shift control leads are placed at a logic 1" temporarily while the count is shifted to a 0. In state 32 the device recycles for seven counts during each of which the opcode register shift control and opcode counter enable leads are temporarily placed in a logic 1 condition. On the next clock after the 7th count the device proceeds to state 33 of FIG. 3D. As the device passes through state 33 the address clock enable is set to 1." Since 8 bits have passed since the first data bit was received, the operator decode 360 provides an output signal. If the output is a connect-control and the control-data line is a logic or the output is a connect-data and the controldata line is a logic l the device will proceed to state 34. If neither of these conditions exist, the device will proceed to state 45 and await another initialization sequence. This procedure is taken because the arrival of the wrong CONNECT words at this time would indicate that either the calling or the called device is inoperative.
However, assuming that the control data lines in the operator section of the CONNECT word correspond, the device will proceed to state 34. lt will stay in state 34 for 22 counts until on the 23rd count the device proceeds to state 35. As will be ascertained, during each of the recycles in state 34, the address clock enable is set to a l while the count is incremented. Upon reaching state 35 the 24 address bits will have been entered into the register 356 of FIG. 2 and decoded in comparator 362. The device stays in state 35 and continuously increments the counter until the count reaches 62 or 1,046. During each of these cycles the received data delimit signal is placed in a logic l If the control-data line is a logic 1, the apparatus counts to 1,046 to allow the passage of the full data message. However, if the control data line is a logic 0," this indicates a control word and only a count of 62 is required. Upon the attainment of the required count, the device proceeds to state 36 where, upon passing to state 37, the parity shift control delimit is set to a I temporarily while the loop busy and count leads are placed in a logic O." The device stays in state 37 for 22 counts while incrementing the counter until on the 23rd count the device proceeds to state 38. The 23 counts necessary to go through state 37 plus the one count for state 36 allows a parity check after the passage of the message. Thus, a parity check is made in state 38. If parity does not check, the device proceeds to state 40 where a count of 7 is completed during which time the response delimit and opcode counter enable are each set to a one. On the 8th count the device proceeds to state 41 on FIG. 3E. If the parity does check, the device proceeds from state 38 to state 39 whereby the acknowledge connect line is raised to a 1 in addition to the response delimit and the opcode counter enable being set to 1. Again, this state idles for a count of 7 and the device proceeds to the strap prior to state 41.
As will be ascertained, if the parity did not check, no acknowledgement would be sent to the calling party. Howevensince the parity did cheek, an acknowledgement was sent so that a further message portion could be transmitted. If the device is anything other than a MGU on the local loop side, the device proceeds to state 2 and awaits a data input signal. If, however, the device is a MGU, the device proceeds to state 41 where the opcode counter enable is set to a 1" and the apparatus waits 7 more counts before proceeding to state 43 where a prepoll is sent and it now returns to state 2.
Previously, the apparatus was followed through to state 17, in FIG. 3B, where it was assumed that the address compared. However, if the address does not compare, the device proceeds to state 10. It stays in state 10 for 53 counts. If after the 53rd count the transmit active signal is a logic 0," the device proceeds to a strap decision block above state 42 on the same sheet. Again, depending upon whether the device is a MGU or not, the device may or may not supply a prepoll output before returning to state 2.
If, upon a count of 53, the transmit active signal is a logic I," thereby indicating that the reason the address did not compare was that a call had just been sent out and it was now being received, the device proceeds to state 11. The response field is examined by decode network 364 and if a busy signal is supplied the device will proceed to state 12 where the response delimit is set to a one temporarily and the poll active is set to a zero. The device then proceeds to state 2 to await a new data bit. If the decode indicates that the response is not busy and if further there is no connect signal, the device will proceed through state 13 to state 2. Again, the response delimit is set to a one.
If the response decode indicates that a connect was received, the device proceeds to state 14 and as it passes therethrough sets the response delimit to a 1" and the acknowledge-connect lead to a logic l. The device then proceeds to state 15 where it awaits the reception of further data. When further data is received, the opcode register shift control is set to a 1" as well as the opcode counter enable lead. The