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Publication numberUS3742484 A
Publication typeGrant
Publication dateJun 26, 1973
Filing dateDec 28, 1971
Priority dateDec 28, 1971
Publication numberUS 3742484 A, US 3742484A, US-A-3742484, US3742484 A, US3742484A
InventorsRosenthal J
Original AssigneeXerox Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Character generating apparatus employing bit stream length correction
US 3742484 A
Abstract
Apparatus for displaying generated characters or symbols on the screen of a cathode ray tube by deflecting the electron beam in a predetermined path in accordance with signals derived from a read only character memory. Binary rate multipliers, under the control of counter logic process the signals from the memory to provide bit streams for transmission to digital to analog converters. The bit streams are integrated in the digital to analog converters to generate strokes which are applied to the X and Y deflection amplifiers of the cathode ray tube.
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United States Patent mi Rosenthal [4 June 26, 1973 [22] Filed:

[ CHARACTER GENERATING APPARATUS EMPLOYING BIT STEAM LENGTH CORRECTION [75] Inventor: Jerome A. Rosenthal, Brighton, N.Y.

[73] Assignee: Xerox Corporation, Stamford, Conn.

Dec. 28, 1971 [21] App]. No.: 212,923

Primary Examiner-John W. Caldwell Assistant Examinere-Marshall M. Curtis Attorney-James J. Ralabate, John E. Beck and David L. Davis 5 7] ABSTRACT Apparatus for displaying generated characters or symbols on the screen of a cathode ray tube by deflecting the electron beam in a predetermined path in accordance with signals derived from a read only character 340/324 memory. Binary rate multipliers, under the control of d 235 counter logic process the signals from the memory to 1 e 0 l l provide bit streams for transmission to digital to analog I 9 converters. The bit streams are integrated in the digital to analog converters to generate strokes which are ap- [56] References cued plied to the X and Y deflection amplifiers of the cath- UNITED STATES PATENTS d ray tube 3,510,865 5/1970 Callahan et al 340/324 A 3,587,083 6/1971 Tubinis 340/324 A 3 Chm, 4 Drawing Figures" I l 1 N X r v END OF STROKE INPUT AD SOURCE SEE. A rr X 9 /3 AY{ I F COUNTER CLOCK Log gi j f r i EM ggg miaasaum. I 12 I l II M I l CLOCK I l ENQSFS'TRBRETMTES x BRM GATES 43 XI Yl T0 BLANKlNG use T0 can. DEFL A K 4 AMP x2 4 47 AM): 0|??? 2 7 J X3 46 Lse' END OF CHI Patented June 26, 1973 4 Sheets-Sheet 2 FFBO FIG. 1A

Patented June 26, 1973 4 Sheets-Sheet '5 STARTING POINT X Y X SY a EXAMPLE OF CHARACTER CODING 9BIT WORD FIG. 2

EOCOOOOO Patented June 26, 1973 I 3,742,484

4 SheetsSheet 4 STARTING POINT X Y X Y 3 0 l l 0 5 II I I l 4 II I l I 4 H I o llx8=8BBlTS 5 II I O I 3 7 O l 0 EXAMPLE OF CHARACTER CODING 2 Q Q Q H BITWORD EOC O O O 0 0 FIG. 3

This invention relates to a character generating apparatus. More particularly, this invention relates to an electronic character generator in which the electron beam of a cathode ray tube is deflected along a prede termined path in order to form characters or symbols on the tube screen.

BACKGROUND OF THE INVENTION display systems a number of electronic devices have been proposed. Among these is the character generator apparatus employing a cathode ray tube. Character generation by means of a cathode ray tube has the objective of displaying line traces on the face of the tube or screen. The line traces may represent vectors, alphanumeric characters or symbols. To provide such a dis- -play, the electron beam of the cathode ray tube is deflected from point to point along a predetermined path.

To deflect the electron beam along the predetermined path, it is necessary at each point of direction change in the path to apply the proper deflection signals to the horizontal (X-axis) and vertical (Y-axis) deflection circuits of the cathode ray tube to move the electron beam to the next point of direction change. In digitally operated display systems, these deflection signals are stored in the character memory and applied to the input circuits of the cathode ray tube at timed intervals. Digitally operated display systems of the past required a great deal of programming and calculations of values of deflection signals in order to drive the electron beam across the tube screen. Inaddition, depending on the number and type of symbols to be generated, digital storage and logic circuits were generally quite numerous. Also the deflection control circuits of these prior art display systems had the disadvantages of requiring precision components as well as being difficult to control.

In these prior art systems a multiplicity of current sources such as transistors and balancing resistors were utilized in order to generate line segments of characters or symbols. Since individual transistors inherently have different operating characteristics, compensating circuitry is required to offset their'differ ing characteristics. The effects of drift and the difficulty of maintaining equal character stroke intensity are also disadvantages frequently encountered in these systems. These deficiencies of prior art systems served not only to .increase the complexity but also the expense of the display apparatus.

Accordingly it is an object of this invent-ion to provide an improved and inexpensive character generating apparatus.

It is another object of this invention to provide a character generating apparatus requiring less current sources for generating character strokes.

It is still another object of this invention to provide a character generating apparatus wherein all the character strokes are confined to a grid simplifying the coding'of stroke signals.

It is further object of this invention to provide a character generating apparatus wherein the electron beam of the cathode ray tube is automatically deflected to trace a character by ,a data bit stream input to circuits which control tube deflection.

SUMMARY OF THE INVENTION In accordance with principles illustrative of this invention, a cathode ray tube is advantageously provided for character generation. Stroke generators activate the deflection circuits of the cathode ray tube by delivering fixed voltage pulses to current sources which in turn charge or discharge capacitors. The strokes are coded as binary bit streams for-the X and Y axes. A binary I bit causes a fixed amount of charge to be deposited or removed from the capacitor associated with appropriate coordinates of X and Y. A binary 0 bit causes no change in the quantity of charge.

The increments in X and Y emanating from character memory are fed to counter logic circuitry including a binary rate multiplier, wherein bit streams are generated. The bit streams are then loaded into X and Y digital to analog converters where they are integrated and strokes generated. The strokes generated in the digital .to analog converters are applied to the X and Y deflection amplifiers of the cathode ray tube to move the electron beam in order to generate the desired character on a grid. In addition, the invention provides means for minimizing digitization error and means for maintaining nearly constant tube contrast.

DESCRIPTION OF THE DRAWING The foregoing will be more readily understood upon DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, there is depicted a block schematic diagram of an illustrative embodiment incorporating the principles of this invention. All of the circuitry to implement this embodiment is well known to one of ordinary skill in the art and no detailed description thereof will be given. Six binary bits of information from an input source I, such as a computer, data keyboard, magnetic tape, etc., are fed into address selector 11. The six binary bits are character selection bits and may be in,ASCII, EBCDIC or other standardized code. In address selector 11 the six bit binary code is translated into a nine bit binary code designating the starting address for each character in character memory 13. This translation may be done by any of various well known prior art techniques. Memory control 12 controls the transmission of the translated address to char acter memory 13. It is to be noted that any codes SPCCIEIE':

ing, since it will occur to those skilled in the art that other codes could be used depending upon the number of characters or symbols desired and the amount of storage available. Information for controlling the generation of a character is stored in memory 13 as a block of contiguous words, the aforementioned translated address defining the first word of the block.

Upon receipt of the address code from memory 12, character memory 13 provides a nine bit binary character code which consists of three bits each for the X and Y increments, one bit each for sign X, sign Y and blanking. The three X increment bits from character memory 12 are routed to input conductors of OR gates 14, 16 and 17 in counter clock logic 15 and also to X binary rate multiplier AND gates 43, 44, and 46. The three Y increment bits from character memory 13 are routed to different input conductors of OR gates l4, l6, and 17 in counter clock logic 15 and to Y binary rate multiplier AND gates 48, 49, and 50. The sign X bit is routed to the X digital to analog converter 52 and the sign Y bit is routed to the Y digital analog converter 53 from character memory 13. The blanking bit from character memory 13 is routed to an input conductor of AND gate 42.

determine the number of counter stages in the binary rate multipliers that will be used to generate the current strokes. Physically, the binary rate multiplier consists of the counter comprising flip-flops 23, 27 and 30, and the binary rate multiplier gates.

The operation of the character generator is described hereinafter. The binary rate multiplier is automatically adjusted to stroke length so that the time taken for drawing shorter strokes is minimized. The number of bits in the binary rate multiplier depends upon the magnitude of the larger ofthe X and Y increments. If the larger increment is or I, the binary rate multiplier has 2 bits; if the larger increment is 2 or 3, the binary rate multiplier has 2 bits; if the larger increment is 4, 5, 6 or 7, the binary rate multiplier has 3 bits. Usual binary rate multipliers construction does not have this feature and the time to draw a stroke is the same for all strokes regardless of length. In the example, all stages of the binary rate multiplier are used. In the event where X 3 and Y 7, the input conductors of OR gates 14, 16 and 17 in counter clock logic 15 will have the following bit configuration:

OR gate 14 will have on its input conductors 0,], OR gate 16 will have on its input conductors [,1 and OR gate 17 will have on its input conductors 1,1. From OR gate 14, a l is fed to inverter 18, AND gate 32 in the end of stroke gate block 35 and AND gate 22 of the counter. OR gate 16 has a l output but AND gates 19 and 21 do not conduct because of inverter 18. Thus, only AND gate 22 is enabled to pass a clock pulse from clock and the counter is configured as a 3 bit counter.

Flip-flops 23, 27 and 30 are set to zero by an initializing pulse from memory control 12. The increments of X and Y are sent to counter logic block and to binary rate multiplier gates 43, 44, 4'6, 48, 49 and 50 4. fromcharacter memory 13. Clock 10 applies a pulse to AND gates 22, 24 and 28, but only AND gate 22 is enabled to pass the clock pulse. Flip-flops 23, 27 and 30 are now toggled in the manner of a conventional three stage counter as indicated in FIG. 1a. Flip-flap 23 is in the one state during times t t t and t Flip-flop 27-is in the one state during times t t t and t, and flip-flop 30 is in the one state during times 1 t t and t Gates 25, 38, 39 and 40 act in a conventional fashion so that line 55 is in the one state during times t,, 1 t and t Line 57 is in the one state during times t and t and line 56 is in the one state during time In this example, the X binary rate multiplier gates 43, 44, 46 and 47 steer three pulsesat times t t and t,, to the X digital to analog converter 52 while the Y binary rate multiplier gates 48, 49, 50 and 51 steer seven pulses at times t, t-, to the Y digital to analog converter 53.

After the stroke has been completed, an end of stroke signal is generated by circuit 35. The end, of stroke gates produce an end of stroke signal when either the output of AND gate 21 is a one and flip-flop 30 is set, or when the output from AND gate 19 is a one and flip-flops 27 and 30 are set, or when the output of OR gate 14 is a one and flip-flops 23, 27 and 30 are set. On receipt of the end of stroke signal, memory control 12 accesses the next word from character memory 13.

In the X and Y digital to analog converters 52, and 53 respectively, the bit streams are integrated by current sources which in turn charge or discharge capacitors and are converted into strokes having direction and amplitude. The strokes are coded as binary bit streams for the X and Y axes. A binary 1 bit causes a fixed amount of charge to be deposited on or removed from the capacitor associated with the appropriate X and Y coordinates. A binary 0 bit causes no change in the quantity of charge on the capacitor. The stroke outputs from X and Y digital to analog converters 52 and 53 are applied directly to the X and Y deflection amplifier of the cathode ray tube (not shown).

The cathode ray tube is unblanked by OR gate 41 and AND gate 42 only when a -one is being loaded into one of the digital to analog converters 52 and 53 and the stroke is coded as an unblanked stroke. Thus, for the bit stream X lOlOlOI Y 0000000,'(X 4, Y 0) the tube is unblanked four sevenths of the stroke generation time. For the bit stream X 111, Y 001 X 3, Y l) the tube is unblanked per cent of the time. In the latter example, there are only three pulses in the digital to analog bit stream because the counter clock logic has suppressed trailing zeros. This is accomplished by steering the clock into flip-flop 27 by way of AND gate 24 and OR gate 26, thereby eliminating flip-flop 23 from the counter and reducing the counter to two stages. When the character has been completed, memory control 12 sends an end of character signal to reset circuit 54. Reset circuit 54 resets the digital to analog converters in preparation for the receipt of the next bit stream.

FIG. 2 shows an example of character coding using a nine bit word. In order to code this character using a character height of 24 units, 1 17 bits of memory is required. Referring to table, in frame I X 3, Y 0, sign X I, sign Y I and B 0. Thus, the signs of X and Y are positive and the tube is blanked. Three pulses along the X axis move the CRT electron beam to the starting'position. In frame 2, X 3, Y 7, sign X I, sign Y.= l and B l. The tube is now unblanked and the strokes are generated to move the beam seven units i 1 l l along the X axis. In Frame 3, t e eam is move seve sar units along the Y axis and two units along the X axis, both sign X and sign Y are positive and the beam is unblanked. By the end of frame 4 the first leg of the letter A is written and the stroke has moved the beam 24 units along the Y axis in a positive direction and nine units along the X axis in a positive direction. Frame 6 starts the beam downward. Therefore sign Y is 0 signifying negative direction, sign X 1 because the beam is moving in the positive X direction and B 1 since the tube is unblanked. in frames 79 the other leg of the letter A is completed. lt now remains to complete the crossbar of the letter A. This is accomplished beginning in frame 10 wherein the beam is blanked, sign X 0, sign Y 1, X =3 and Y 7. Thus, the beam is blanked along the dotted line. In frames 1 l and 12 the crossbar is written and frame 13 sends the system the end of character signal.

FIG. 3 is an example of a character employing an 11 bit word (4 bits each for X and Y and three control bits sign X, sign Y and blank). This character is achieved with a moderate expansion of the logic and 88 bits are required to code the same character.

As can be seen from FIGS 2 and3, the resultant character is generated in continuous line segments on the grid. This permits characters having substantially constant .intensity. Moreover, the characters are formed at high speed and have good character definition independent of character size and location.

lt will be apparent to those skilled in the art that the present invention may be used generally in display systems and is not limited to the embodiment described. Numerous other variations, modifications and adaptations of the present invention will be apparent to those skilled in the art, and such as come within the spirit and scope of the appended claims are considered to be cmbraced by the present invention.

What is claimed is:

I v 1-. Character generating apparatus for controlling the deflection circuits of a cathode ray tube to move an electron beam across the screen of said cathode ray tube to display a character thereon, said character being formed by a plurality of straight line segments,

llllllllllllllllll means for receiving a character code and transforming said character code into an address code,

memory means responsive to said address code for providing a word for a line segment of said character, said word containing horizontal and vertical components of the deflection increment and beam control signals for said line segment,

counter means including a plurality of selectively enabled stages for providing signals defining a selectable number of bitstream positions,

counter enabling means responsive to the magnitudes of the horizontal and vertical component increments of said line segment for selectively enabling 4 said stages of said counter means so as to select the number of bit stream positions defined by said counter means,

means responsive to said increment signals and said bit stream position defining signals for generating a horizontal bit stream and a vertical bit stream, each of said bit streams having as many ls as the magnitude of the respective coordinate component of said line segment, and

means converting said bit streams into stroke signals and applying said stroke signals to the respective deflection circuits of said cathode ray tube.

2. The apparatus of claim 1 further comprising means responsive to said counter means and said counter enabling means for generating an end of stroke signal for application to said memory means at the end of said bit streams, said memory means being responsive to said end of stroke signal for providing another word containing signals for another line segment of said character.

3. The apparatus of claim 2 further comprising means responsive to an end of character indication in said beam control signals for resetting said deflection circuits so as to position said electron beam for the display of another character.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3510865 *Jan 21, 1969May 5, 1970Sylvania Electric ProdDigital vector generator
US3587083 *Sep 28, 1967Jun 22, 1971Xerox CorpCharacter generation and display system
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3869085 *Dec 17, 1973Mar 4, 1975Sperry Rand CorpControlled current vector generator for cathode ray tube displays
US3930250 *May 6, 1974Dec 30, 1975Vydec IncSynchronizing system for refresh memory
US3952297 *Aug 1, 1974Apr 20, 1976Raytheon CompanyConstant writing rate digital stroke character generator having minimal data storage requirements
US4331955 *Aug 7, 1980May 25, 1982Eltra CorporationMethod and apparatus for smoothing outlines
US4524353 *Mar 29, 1982Jun 18, 1985Sperry CorporationLine pattern template generator
Classifications
U.S. Classification345/18
International ClassificationG06F7/60, G09G1/06, G06F7/68, G09G1/10
Cooperative ClassificationG06F7/68, G09G1/10
European ClassificationG06F7/68, G09G1/10