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Publication numberUS3743923 A
Publication typeGrant
Publication dateJul 3, 1973
Filing dateDec 2, 1971
Priority dateDec 2, 1971
Also published asCA984906A1, DE2254618A1, DE2254618B2
Publication numberUS 3743923 A, US 3743923A, US-A-3743923, US3743923 A, US3743923A
InventorsSteudel G
Original AssigneeRca Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Reference voltage generator and regulator
US 3743923 A
Abstract
A circuit which is utilized to produce a reference voltage that is substantially independent of changes in the supply line voltage and in temperature and which produces a regulated output voltage as a function of the reference voltage.
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United States Patent 1191 Steudel REFERENCE VOLTAGE GENERATOR AND REGULATOR [75] lnventor: Goetz Wolfgang Steudel,

I Flemington, NJ.

[73] 'Assignee: RCA Corporation, New York, [22] Filed: Dec. 2, 1971 21 Appl. No.: 204,224

[52]. us. c1...- 323/22 R, 307/304, 323/1,

[51] Int. Cl. G05! 1/56 [58] Field of Search 307/297, 304; 323/ 1,

323/4, 16, 19, 22 R, 22 T; 330/30 D, 69

[56] I References Cited UNITED STATES PATENTS 3,681,623 8/1972 Hoffman, Jr et a1 323/4 X 2,963,637

l2/l960 Osborn 323/22'r' 1451 July 3, 1973 3,317,850 5/1967 Hilbiber 307/304 X 3,303,413 2/1967 Warner, Jr. et al 323/4 3,386,030 5/1968 Kann 323/4 3,508,084 4/1970 Warner. Jr 307/304 OTHER PUBL1CAT1ONS Markus, Sourcebook of Electronic Circuits,

McGraw-Hill Book Co., 1968, page 171, TK7867M3.

Primary Examiner-A D. Pellinen Attorney-H. Christoffersen s7 I ABSTRACT A circuit which is utilized to produce a reference voltage that is substantially independent of changes in the supply line voltage and in temperature and which produces a regulated output voltage as a function of the reference voltage.

11 Claims, 1 Drawing Figure REFERENCE VOLTAGE GENERATOR AND REGULATOR BACKGROUND In the present technology, the integrated circuit is being utilized in more and more applications. There are several types of integrated circuitry known. One popular type of integrated circuit technology uses the so called COS/MOS (i.e., Complementary-Metal-Oxide- Semiconductor) integration process. This type of process or technology permits many circuits to be produced utilizing the standard MOS type advantages as well as the advantages which are provided by using the COS/MOS techniques. These advantages,. such as low power requirements, high packing density and low power-delay product, are well known in the art.

When producing circuits or systems utilizing COS/- MOS techniques, it frequently becomes necessary to include a means for providing regulation of one or more of the voltages which are utilized or generated by the circuit. As one approach to providing the regulation, it is frequently desirable to provide a reference voltage to which the circuit may be referenced. Moreover, it is desirable that the reference voltage be substantially independent of any fluctuations in the supply voltage or, alternatively, due to temperature changes or the like. Furthermore, it is important that the regulator circuit should not be a power drain on the overall system. Another desirability is to be albe to produce the voltage generator and regulator using standard COS/- MOS processing techniques whereby the circuit can be integrated along with the associated COS/MOS circuitry. The use of a COS/MOS regulator, on the same chip as the associated COS/MOS circuitry, permits the full utilization of the low power requirement advantage of COS/MOS circuitry.

SUMMARY OF THE INVENTION A voltage generator and regulator circuit is provided wherein a first portion of the circuit operates uponstandard supply voltages to produce or generate a reference voltage which is substantially independent of variations in supply voltage or temperature. The output voltage from the voltage generator is supplied to a regulator circuit which produces an output voltage which is regulated as a function of the reference voltage. Thus, the output from the regulator circuit is a regulated voltage which is controlled by a relatively accurate reference voltage.

BRIEF DESCRIPTION OF THE DRAWING The single FIG. is a schematic diagram of one embodiment of the instant invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT is negative relative to the'source electrode. Conversely, N-type MOS devices are rendered conductive when the gate electrode is positive relative to the source electrode.

In the reference voltage generator, the input voltages are suppied at terminals 10 and 11, respectively. Input terminal 10 may represent ground potential or any suitable reference source (V while terminal 11 is connected to source V the voltage to be regulated by circuit 51. The voltage V is positive relative to V A P-type semiconductor device P1 has the source electrode (S) and the substrate thereof connected to' terminal 10. The drain electrode (D) of device P1 is con-' nected to the cathode of Zener diode Z2. The anode of Zener diode Z2 is connected to terminal 11 along with the gate electrode (G) of P-type semiconductor device P2. The drain electrode (D) of device P2 is connected to the cathode of Zener diode Z2. The source electrode (S) and substrate of device P2 are connected to terminal 10. The cathode of Zener diode Z2 is also connected to the gate electrode (G) of N-type semiconductor device N1. The source electrode (S) and substrate of device N1 are connected to terminal 11. The drain electrode (D) of device N1 is connected to the anode of Zener diode Z1. The cathode of Zener diode Z1 is connected to terminal 10. The anode of Zener diode Z1 is also connected to the gate electrode of device P1 and to the regulator circuit portion along line 13. The cathode of Zener diode Z2 is connected to the regulator circuit portion along line 12.

In the series voltage regulator circuit portion 51, the source electrode (S) and the substrate of semiconductor device P3 are connected to source V,,,, at terminal 10. The gate electrode (G) of device P3 and the gate electrode (G) of device P4- are connected to the reference input source supplied at line 13 from voltage generator 50. The drain electrode (D) of device P3 is connected to the source electrodes of devices P4 and P5. The drain electrode (D) of device P5 is connected to terminal 11 and source V The drain electrode (D) of device P4 is connected to the drain electrode (D) of device N2. The source electrode (S) and the substrate of device N2 are each connected to terminal 11. The gate electrode (G) of device N2 is connected to line 12 which, in this embodiment, is a source of a constant voltage, relative to source V supplied by voltage generator 50. In an alternative embodiment, line 12 may be connected to source V at terminal 10. In the alternative embodiment, some control over the impedance of device N2 and, thus over the circuit, may be lost in the case of widely fluctuating V,,,,.

The drain electrode of device P5 is also connected to terminal 1 1 along with the source electrode (S) and the substrate of device N3. The drain electrode (D) of device N3 and the gate electrode (G) of device P5 are connected to output terminal 14 at which a voltage V is regulated by the circuit 51. The gate electrode (G) of device N3 is connected to the common junction of the drain electrodes of devices P4 and N2. The sub strates of devices P4 and P5 are also connected to V Typically, device P3 is of medium impedance (i.e., higher than P4, P5 and N3 but lower than N2) and is normally turned on whereby there is a substantially constant source-drain current therethrough. Also, device N3 is the regulating device in the circuit and is of relatively low impedance (i.e., of approximately the same impedance as devices P4 and P5). With the circuit configuration shown, the drain-source voltage of device N2 is the gate-source voltage of device N3.

In operation, an essentially constant voltage is supplied to the gate electrode of device N1 by Zener diode Z2. Consequently, when saturation of N1 is reached, device N1 operates as a constant current source and supplies current to Zener diode Z1. Conversely, the current through Zener diode Z2 is supplied by device P1 which also operates as a constant current source after saturation is achieved. That is, an essentially constant voltage is applied to the gate of device P1 by Zener diode Z1, which voltage biases device P1 in saturation. Thus, the current through Zener diode Z2 is supplied by device P1 while the current through Zener diode Z1 is supplied by device N1. The circuit comprising devices N1 and P1 and Zener diodes Z1and Z2 tends to operate as a flip-flop. That is, once the circuit achieves the steady state condition, it latches in this condition and substantially constant voltages relative to V and V are applied at lines 12 and 13. These voltages are defined as a function of the Zener voltage drop across Zener diodes Z1 and Z2. This type of operation results when the currents supplied to Zener diodes Z1 and Z2 by devices N1 and P1, respectively, are of sufficient magnitude to bias the diodes Z1 and Z2 at points in the constant or Zener voltage portions of their I-V operating characteristics. It is possible for the circuit to latch in the inoperative condition if insufficient current is supplied to the Zener diodes by the devices P1 and N1. This condition will produce insufficient voltage drops across the Zener diodes whereby devices P1 and N1 will remain nonconductive.

Therefore, semiconductor device P2, which is a high impedance device, is provided. Whenever a supply voltage greater than the threshold voltage of device P2 is connected between nodes and 11, semiconductor device P2 is conductive and is designed to supply sufficient current through Zener diode Z2 to poduce a voltage of at least the N-threshold across Zener diode Z2 thereby causing device N1 to be rendered conductive. Of course, when device N1 is conductive, device P1 is rendered conductive becuase the current through N1 produces a voltage drop across Z1 which is greater than the P-threshold for device P1. In fact, in some applications where regulation is not so critical, device P1 may be eliminated whreby device P2 maintains the turn-on current for Zener diode Z2, as suggested supra. In this alternative configuration the control of the voltage on line 12 is somewhat reduced. However, the performance of both circuits is satisfactory and very similar.

The reference voltages produced by voltage generator 50 are supplied to regulator 51 along lines 12 and 13. In particular, the voltage on line 12 is a constant control voltage which controls the impedance of device N2 which is a high impedance device relative to devices P3, P4, P5 and N3. Becuase the gate electrode is at one fixed value of potential V and the source electrode at another fixed value of potential V device N2 operates as a constant current means. The voltage on line 13 is the reference voltage upon which the regulator operates to produce the regulated voltage V The transistors P4, P5 receiving the current supplied by-sourcc P3 of the regulator circuit operate as a differential amplifier. They compare the voltage V on line 13 with the output voltage V at terminal 14 in the manner discussed in detail below.

In typical operation, if the output voltage V measured between terminals 10 and 14 is larger (i.e., less positive or more negative) than the reference voltage measured between terminals 10 and 13, low impedance device P5 is relatively more conductive than low impedance device P4 whereby substantially all of the current from device P3 is passed through device P5. Conversely, device P 5 is relatively nonconductive whereby its impedance is much higher than that of N2. Consequently, the voltage drop across device N2 drops to near zero wherein device N3 is rendered nonconductive. When device N3 is nonconductive, the output voltage at terminal 1 1 is reduced (becomes less negative or more positive) inasmuch as current is not supplied to terminal 14- from the source represented by terminal 13.

Conversely, if the voltage V at terminal 14 is smaller (i.e., less negative) than the reference voltage on line 13, device P4 is rendered conductive and device P5 is rendered nonconductive. Consequently, current flows through the series connected conduction paths of devices P4 and N2 to source 11. As a result of the current through devices P4 and N2, the voltage drop across device N2 increases because device N2 is of much higher impedance than P4 whereby the voltage applied to the gate electrode of device N3 becomes more positive (relative to V In response to the voltage condition at the gate electrode thereof, device N3 is rendered conductive and connects terminal 11 to terminal 14. Consequently, the output voltage at terminal 14 increases (becomes more negative or less positive) as a result of the current supplied via device N3.

When the output voltage at terminal 14 is equal to the reference voltage on line 13, devices P4 and P5 are both conductive wherein the current from source P3 is split between devices P4 and P5. The current split is effective to'stabilize the operation of the circuit. In this condition, device N3 is just barely conductive.

Furthermore, the circuit loop includes only one inversion, i.e., if the output voltage at terminal 14 becomes more positive, the voltage at the gate electrode of device N3 becomes more positive and this causes the voltage at terminal 14 to become more negative. This is the only inversion in circuit 51. With only one inversion, oscillation (or hunting) of the output voltage V is possible only for the case of extremely high impedance loads. That is, with high impedance loads, even small load currents produce large voltage swings across the load and, thus, at terminal 14. These large voltage swings can cause oscillation inasmuch as the circuit cannot follow precisely enough and limit the swing. However, the loads for this circuit typically will not be of the magnitude to permit this type of operation. Conversely, small loads (e.g., load currents in the low microampere range) cause the circuit to be extremely stable. Of course, in typical applications of the circuit in integrated circuit form, the load currents will be quite small. However, some type of load, even though small, should preferably be provided in order to assure that the voltage at terminal 14 can be returned towards the V level. That is, zero load produces an operation wherein the voltage level at terminal 14 can be reduced to below the reference voltage level (V at line 13 but cannot be increased from a voltage level below the reference level.

The circuit shown is especially adapted to integrated circuit fabrication especially of the COS/MOS variety.

For example, referring to voltage generator 50, it is known that in the normal COS/MOS fabrication process, P- and N-channel MOS enhancement field effect transistors on a monolithic substrate include a P+ and an N+ diffusion for the drain and source electrodes of the P and N units, respectively. If the N+ diffusion is diffused into a P+ diffusion, a PP N+ junction is obtained. This type of junction as a Zener characteristic. Moreover, the Zener voltage produced by this junction has a positive temperature coefficient. Inasmuch as semiconductor devices N1, P1 and P2 of voltage generator 50 have negative temperature coefficients, the circuit can be designed to produce a substantially temperature independent voltage source. This circuit together with regulator circuit 51 can be fabricated using the normal COS/MOS techniques whereby a sophisticated power regulator source for a logic system can be integrated on the same monolithic chip of an integrated circuit.

The combined circuits, thus, produce a circuit which regulates a variable load at the output so that a relatively constant voltage substantially equal to a reference voltage is produced. This circuit also has a very small power consumption in comparison to the maximum load.

Thus, there has been described one embodiment of a voltage generator and regulator circuit which has the described advantages. The circuit is described in terms of MOS type integrated circuitry. The specific circuitry shown is illustrative of the invention; however, the scope of the invention is defined by the appended claims.

What is claimed is:

1. In combination,

source means having first and second terminals,

a plurality of semiconductor devices each having a conduction path and a control electrode for controlling the conduction through said conduction path,

first and second semiconductor devices of a first conductivity type having one end of the conduction paths thereof connected together in a common junction,

a third semiconductor device of said first conductivity type having the conduction path thereof connected between the common junction at said first and second semiconductor devices and said first terminal of said source means,

a fourth semiconductor device of a second conductivity type having the conduction path connected between the conduction path of said first semiconductor device and said second terminal of said source means,

an output terminal,

a fifth semiconductor device of said second conductivity type having the conduction path thereof connected between said second terminal of said source means and said output terminal,

reference source means connected to the control electrodes of said first and third semiconductor devices to establish a conduction level in saif first and third semiconductor devices, and

control source means connected to the control electrode of said fourth semiconductor device to establish a conduction level therein,

the control electrode of said fifth semiconductor device connected to the common connection of said first and fourth semiconductor device conduction paths to control the conduction of said fifth semiconductor device as a function of the voltage level at said common connection thereby to control the voltage at said output terminal,

the control electrode of said second semiconductor device connected to said output terminal to control the relative conduction of said first and second semiconductor devices as a function of the voltage level at said output terminal relative to the voltage supplied by said reference source.

2. The combination recited in claim 1 wherein said semiconductor devices are MOS field effect transistors formed on a common substrate.

3. The combination recited in claim 1 wherein said first, second and fifth semiconductor devices normally exhibit substantially similar impedance values, said fourth semiconductor device exhibits an impedance value which is substantially greater than the impedance value of said first, second and fifth semiconductor devices, and said third semiconductor device exhibits an impedance value between the impedance values of said fourth semiconductor device and said first, second and fifth semiconductor devices.

4. The combination recited in claim 1 including load means connected between said output terminal and said first terminal of said source means.

5. In combination,

source means having first and second terminals,

a plurality of semiconductor means, each of said semiconductor means having a conduction path with a terminal at each end thereof and a control electrode for controlling the conduction through said conduction path, said semiconductor'means being of first or second conductivity type,

first semiconductor means of said first conductivity type,

second semiconductor means of said second conductivity type, 1

first Zener diode means connected in series with the conduction path of said first semiconductor means,

second Zener diode means connected in series with the conduction path of said second semiconductor means,

means connecting said control electrode of said first semiconductor means to a common connecton between said second semiconductor means and said second Zener diode means,

means connecting said control electrode of said second semiconductor means to a common connection between said first semiconductor means and to said first Zener diode means,

said first Zener diode means and one terminal of said conduction path of said second semiconductor means connected to said second terminal of said source means, 1

said second Zener diode means and one terminal of said conduction path of said first semiconductor means connected, to said first terminal of said source means,

third and fourth semiconductor means of said first conductivity type having one terminal of the conductioh paths thereof connected together in a common junction,

the other terminal of the conduction path of said fourth semiconductor means connected to said second terminal of said source means,

fifth semiconductor means of said first conductivity type having the conduction path thereof connected between the common junction at said third and fourth semiconductor means and said first terminal of said source means,

sixth semiconductor means of said second conductivity type having the conduction path connected between the conduction path of said third semiconductor means and said second termnal of said source means,

an output terminal,

seventh semiconductor means of said second conductivity type having the conduction path thereof connected between said second terminal of said source means and said output terminal,

the control electrodes of said third and fifth semiconductor means connected to said common connection between said second semiconductor means and said second Zener diode means to establish a conduction level in said third and fifth semiconductor means, and the control electrode of sixth semiconductor means connected to said common connection between said first semiconductor means and said first Zener diode means to establish a conduction level therein, the control electrode of said seventh semiconductor means connected to the common juncton at said third and sixth semiconductor means conduction paths to control the conduction of said seventh conductor means as a function of the voltage level at said common junction thereby to control the voltage at said output terminal, the control electrode of said fourth semiconductor means connected to said output terminal to control the relative conduction of said third and fourth semiconductor means as a function of the voltage level at said output terminal relative to the voltage supplied to the control electrodes of said third semiconductor means; 6. In a voltage regulating circuit of the type comprising first and second transistors connected in differential amplifier configuration; current source means connected to said differential pair to supply current thereto; means for providing a reference potential to the control electrode of said first transistor; means for connecting the control electrode of said second transistor in circuit with an output terminal the voltage at which is to be regulated; and a series pass transistor connected in series with said output terminal and adapted to regulate the supply of line current to said output terminal as a function of the signal applied to the control electrode of said series pass transistor, the improvement comprising:

a further transistor having its conduction path con nected in series circuit with the conduction path of said first transistor and connected to operate as a constant current source, the conduction path of said further transistor exhibiting a relatively high impedance to said first transistor whereby the output signal from said first transistor is applied as a control signal to the control electrode of said series pass transistor.

7. A voltage regulating circuit comprising:

first and second transistors having one end of each of the conduction paths thereof connected together at a common junction;

means for providing a relatively constant current to said common junction;

means for providing a relatively fixed reference potential to the control electrode of said first transistor to bias said first transistor into conduction;

means for connecting a load to the control electrode of said second transistor, the voltage drop across said load being the voltage to be regulated;

feedback means including a third transistor having its control electrode connected in circuit with the other end of the conduction path of said first transistor and further having one end of its conduction pathconnected in circuit with the control electrode of said second transistor, the conduction path of said third transistor being connected in series with with the load for controlling the current level therethrough;

a fourth transistor having its conduction path connected in series with the conduction path of said first transistor; and

means for providing a constant reference potential to the control electrode of said fourth transistor to bias said fourth transistor into conduction, the conduction path of said fourth transistor exhibiting a relatively high impedance to the output signal produced by said first transistor whereby said output signal is directly applied as a control signal to the control electrode of said third transistor.

8. A voltage regulating circuit as recited in claim 7 wherein the impedance of the conduction'path of said fourth transistor is substantially greater than the impedance of the conduction paths of said first, second and third transistors for the same value of bias condition, and wherein said first and second transistors are of one conductivity type and said third and fourth transistors are of a second conductivity type.

9. A voltage regulating circuit as recited in claim 8 further comprising:

first and second terminals adapted for connection to a source of potential, said common junction being connected in circuit with said first terminal through said relatively constant current means;

means for connecting the conduction paths of said third and fourth transistors in circuit with said second terminal; and

circuit loading means connected between said first terminal and the control electrode of said second transistor.

10. in combination:

first and second field effect transistors each having a conduction path and a control electrode for controlling the current flow therethrough, and a current source coupled to said paths for supplying current in parallel to said paths;

a circuit point at a reference'potential connected to the control electrode of the first transistor;

a second circuit point at which a voltage to be regulated appears, connected to the control electrode of the second transistor, said voltage being a function of the current supplied to said second circuit point;

current sensing means comprising a constant current element connected in series with the conduction path of the first transistor;

a second current source; and

a signal responsive conduction path located between said second current source and said second circuit feet transistor having a conduction path connected in series with that of the first transistor, and having a control electrode connected to a point of fixed reference potential for maintaining the impedance of said path at a given value.

Disclaimer 3,743,923.Goet2 Wolfgang Steudel, Flemingbon, NJ. REFERENCE VOLT- AGE GENERATOR AND REGULATOR. Patent dated July 3,

1973. Disclaimer filed May 5, 1980, by the assignee, BOA Gov-1201mm.

Hereby enters this disclaimer to claims 6, 7 8, 9, 10 and 11 of said patent.

[Oficz'al Gazette Jwne 24, 1980.]

Disclaimer 3,743,923.-G0etz Wolfgang Steudel, Flemingbon, NJ. REFERENCE VOLT- AGE GENERATOR AND REGULATOR. Patent dated July 3, 1973. Disclaimer filed May 5, 1980, by the assignee, BOA Omamtion.

Hereby enters this disclaimer '00 claims 6, 7, 8, 9, 10 and. 11 of said patent.

[Ofiicz'al Gazette Jwne 24, 1.980.]

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Reference
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3926198 *May 2, 1975Dec 16, 1975Arco Med Prod CoCardiac pacer
US4061962 *Jun 11, 1976Dec 6, 1977Rca CorporationCurrent mirror amplifier augumentation of regulator transistor current flow
US4096430 *Apr 4, 1977Jun 20, 1978General Electric CompanyMetal-oxide-semiconductor voltage reference
US4158804 *Aug 10, 1977Jun 19, 1979General Electric CompanyMOSFET Reference voltage circuit
US4165478 *Sep 21, 1977Aug 21, 1979General Electric CompanyReference voltage source with temperature-stable MOSFET amplifier
US4217535 *Dec 23, 1977Aug 12, 1980Tokyo Shibaura Electric Co., Ltd.Constant-voltage circuit with a diode and MOS transistors operating in the saturation region
US4232261 *Jan 30, 1978Nov 4, 1980Eurosil GmbhMOS Control circuit for integrated circuits
US4266178 *Oct 5, 1977May 5, 1981Kabushiki Kaisha Suwa SeikoshaCharge control circuit
US4267501 *Jun 21, 1979May 12, 1981Motorola, Inc.NMOS Voltage reference generator
US4397563 *May 1, 1980Aug 9, 1983Kabushiki Kaisha Suwa SeikoshaPower circuit for electronic wristwatch
US4423369 *Apr 11, 1979Dec 27, 1983Motorola, Inc.Integrated voltage supply
US5079497 *Aug 14, 1990Jan 7, 1992U.S. Philips CorporationCircuit intended to supply a reference voltage
US5159260 *Jan 7, 1987Oct 27, 1992Hitachi, Ltd.Reference voltage generator device
US6630903 *Sep 28, 2001Oct 7, 2003Itt Manufacturing Enterprises, Inc.Programmable power regulator for medium to high power RF amplifiers with variable frequency applications
Classifications
U.S. Classification323/281, 327/581, 330/69
International ClassificationG01D5/12, G05F3/18, G05F1/10, H01L21/70, H01L21/822, H01L27/04, G05F3/08, G01D5/24, G05F1/56
Cooperative ClassificationG05F3/185
European ClassificationG05F3/18F