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Publication numberUS3754392 A
Publication typeGrant
Publication dateAug 28, 1973
Filing dateMay 17, 1971
Priority dateMay 17, 1971
Publication numberUS 3754392 A, US 3754392A, US-A-3754392, US3754392 A, US3754392A
InventorsDaniels R
Original AssigneeMotorola Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus for driving a light emitting diode of horologic display
US 3754392 A
Abstract
There is disclosed a logic and driving circuit for a light emitting diode type horologic display in which three diodes are read out at any given time to represent the time of day. Power consumption is kept to a minimum by the use of a two voltage level system with the lower voltage supplying those portions of the circuit working at a high frequency while the higher voltage supplies the display and those portions of the driving circuit operating at a considerably lower frequency. In addition to a crystal frequency standard and a "divide-by-two" flip-flop countdown circuit which provides a 1 Hz signal to a series of toggle flip-flop counting circuits which function as the seconds, minutes and hours storage elements, there is provided a multiplexer coupled to the outputs of these counting circuits which is strobed with pulses having a combined duration of only a fraction of the sampling cycle. This results in a low duty cycle for the output of the multiplexer and thus for the display itself which conserves on the power necessary to drive the display. Since hour, minute and second information is sequentially sampled by the multiplexing circuit, multiplexing eliminates decoder and driver redundancy. Provision is made in the multiplexing logic for dividing the horological display into quadrants or sectors so as to further reduce the number of driver and decoder elements. As a result there is also provided a quadrant selecting circuit. The sampling pulses for the multiplexing circuit are conveniently derived from the frequency standard countdown circuit. The driving system utilizes complementary metal oxide semiconductor (CMOS) components in which power drain is minimized because these elements draw appreciable power only when switching. A further power consumption advantage is obtained by utilizing NAND gate logic to permit the use of these low power CMOS components. Toggle flip-flops are chosen for the counters because they are available in metal oxide semiconductor form and because the total number of transistors utilized is reduced. The logic described herein is used with a horologic display in which the minutes and seconds are displayed in the single ring of elements with the hours being displayed in another single ring of elements.
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United States Patent Daniels [111 3,754,392 1451 Aug. 28, 1973 3/1971 Walton 58/23 X Primary Examiner-Richard B. Wilkinson Assistant Examiner-Edith C. Jackmon Attorney-Mueller and Aichele ABSTRACT There is disclosed a logic and driving circuit for a light emitting diode type horologic display in which three diodes are read out at any given time to represent the time of day. Power consumption is kept to a minimum by the use of a two voltage level system with the lower voltage supplying those portions of the circuit working at a high frequency while the higher voltage supplies the display and those portions of the driving circuit opl.5 VOLT SUPPLY (HIGH FREQUENCY CIRCUITS) crating at a considerably lower frequency. In addition to a crystal frequency standard and a "divide-by-two flip-flop countdown circuit which provides a 1 Hz signal to a series of toggle flip-flop counting circuits which function as the seconds, minutes and hours storage elements, there is provided a multiplexer coupled to the outputs of these counting circuits which is strobed with pulses having a combined duration of only a fraction of the sampling cycle. This results in a low duty cycle for the output of the multiplexer and thus for the display itself which conserves on the power necessary to drive the display. Since hour, minute and second information is sequentially sampled by the multiplexing circuit, multiplexing eliminates decoder and driver redundancy. Provision is made in the multiplexing logic for dividing the horological display into quadrants or seetors so as to further reduce the number of driver and decoder elements. As a result there is also provided a quadrant selecting circuit. The sampling pulses for the multiplexing circuit are conveniently derived from the frequency standard countdown circuit. The driving systemutilizes complementary metal oxide semiconductor (CMOS) components in which power drain is minimized because these elements draw appreciable power only when switching. A further power consumption advantage is obtained by utilizing NAND gate logic to permit theuse of these low power CMOS components. Toggle flip-flops are chosen for the counters because they are available in metal oxide semiconductor form and because the total number of transistors utilized is reduced. The logic described herein is used with a horologic display in which the minutes and seconds are displayed in the single ring of elements with the hours being displayed in another single ring of elements.

19 Claims, 13 Drawing Figures 1 i 1 I I 110 11s 1 n C I 1 F 4 F 1 i 1 I 1 Hz ll I F/F F/F---F/F I I I 1 l 1 1 1 1 1 1 I16 116 11s I 1 1 El i 256 111V lza Hz 1 l i l -64 Hz 1 i i 1 1 1 1 l 9- J L PPE BQ'Q 1 I l 1 l l 1 160 1 n 1 i 130 12,1 132 TIME SET f g 1 sec MIN. HR, 1 COUNTER COUNTER COUNTER DECODER 1 136 I z Y /?133 771a4 /?135 l I SEC. m,"- 1

I5 1 QUADRANT l LEVEL m 1 TRANSLATOR MULTJPLEXER I I -14o HR i I I I 1 |2o SECTOR I F g i SELECTOR m l 1 1 3 VOLT SUPPLY (LOW FREQUENCY cmcun's) .11 J

FROM DRIVER Patented Aug. 28, 1973 3,754,392

11 Sheets-Sheet 2 HR FROM ISZ SECTOR m SELECTOR MlNUTE-SECOND RING ONLY 5 I Hi2 (QUADRANTS Lm, AND N) I4 |3 H|| HOUR SECTOR H 11 I I0 m" MINUTE SECOND SECTORS n a H HOUR SECTOR 5 0- I 4 mu E- EC ND SECTOR 3 o M T S O S INVENTOR 2 m0 1?. Gary Dan/Eels BY O WM 1744M ATTY'S w l I I I I I I I I I I mwhzDoo m:

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Patented Aug. 28, 1973 1 1 SheetsSheet 7 lI orA I Or I! =5 w M m M a M A N k M v MINJSECJHR. MULTIPLEXERJI Illlulllllllllll INVENTOR. R. Gary Danie/s WM M Arrrst Patented Aug 28, 1973 1 1 Sheets-Sheet 8 ISO DECODER I I l i l l l I l Arrrs.

Patented Aug. 28, 1973' 11 Sheets-Sheet 9 Arrris.

Patented Aug. 28,1973 I 3,754,392

11 Sheets-Sheet ll 7 SEC.

AND

- MIN.

I E E 5* J INVENTOR BY 1?. Gary Danie/s i 2/ 2 4 ATTYS APPARATUS FOR DRIVING A LIGHT EMITTING DIODE OF I-IOROLOGIC DISPLAY BACKGROUND OF THE INVENTION This invention relates to horologic displays and more particularly to a system for providing a digital readout for a horologic display in which the minutes and seconds are displayed in a first ring of elements with the hours being displayed in a second ring of elements.

There has in the past been a great deal of interest shown in the provision of a digital readout for wrist watches. Wrist watches utilizing digital readouts have recently been provided with readouts in alpha-numeric form utilizing an XY addressable matrix of individual light emitting diodes. The circuits necessary for driving XY addressable light emitting diode arrays are well known. However, alpha-numeric light emitting diode displays suffer from one major problem when they are utilized to portray the time of day in a wrist watch. This problem is primarily power consumption. Power consumption is so great in wrist watches utilizing alphanumeric displays that the battery for the wrist watch mustbe replaced within a matter of weeks if the'display is to run continuously. The reason for the amount .of power drawn by alpha-numeric display type wrist watches is the number of :light emitting elements necessary toportray the time of day. In an effort to increase thelifetime of the wrist watch there is provision for intermittent readout which is-activated by the user of the wrist watch. This is both inconvenient and annoying to the user.

Thesubject system is employed in a time readout of adifi'erent character altogether. The time of day is read out by a maximum of three light emittingdiodes. In one configuration, 60 light emitting diodes are arranged in a ring and represent both minutes and seconds. An inner concentric ring of 12 light emitting diodes represents the 'hour of day. The time is read out in this display by providing that the hour diode be substantially continuously lit for the "hour it represents. In the outer ring the minute diode remains litsubstantially continuously for the minute that it represents. While :the minute diode is lit the remaining diodes in the outer ring are lit sequentially so as to represent seconds. Thus,for any given minute-all 60 diodes representing seconds are lit sequentially in a clockwise stepping type .display. After the seconds have stepped around a full 60 seconds, the next minute diode is activated. it will be appreciatd that in this type display the 60 diodes in the outer ring serve both to represent minutes and seconds. It will be further appreciated thatthe time of day can be read out with a maximum of 3 diodes during any given second. This compares to a maximum of 87 diodes to represent the time of day in alpha-numeric form.

The subject system isone which providesthelogic and driving circuits necessary to actuate the above mentioned light emitting diodes in the proper sequence. In the concentric ring display, it is possible to reduce the current drawn by such a display to 5 milliamps or less by reducing what is known as the duty cycle-of the display. This refers .to the'practice of lighting each light emitting diode, not continuously, but in alpulsed manner'such that the diode is lit only for a certain percentage of time. The logic portion of the circuit to be described herein in combination with the driving portion not only actuates the display in proper sequence, but also provides the low duty cycle. The logic and driver portions utilize only an insignificant additional amount of current therefore enabling a light emitting diode horologic display which can be read out in a substantially continuous manner for a period of time exceeding one year without the necessity of providing for intermittent readouts to extend battery lifetime.

Power consumption in the logic and driving circuits are kept to a minimum by the use of several individual concepts. The first of these concepts involves the use of two voltage levels in the operation of the display. For those circuits having a high frequency of operation (i.e., almost continuous operation), a lower voltage such as 1.5 volts is used to minimize power consumption. These type of circuits are the crystal oscillator circuit and the countdown circuit which are utilized in reducing the frequency of the crystal oscillator to l .Hz. The remainder of the circuit, that is to say the minute, second and hour counting circuits, the multiplexer circuits, the decoding circuits, and the driving circuits, as well as the light emitting diodes themselves, are ,provided with a 3 volt supply. It will be appreciated that these latter circuits are operated at a considerably lower frequency than the countdown circuitry. Although the higher voltage is desirable in order to drive the light emitting diode elements, power is conserved because both the duty cycle of the light emitting diode :elements and the duty cycle of the drive circuitry isreduced to as low as 12.5 percent total on time perelement. Thus, while it is necessary to increase the voltage to these circuits in order to provide driving power for the light emitting display, this power is utilized over a low duty cycle which corresponds to alower frequency of operation.

Another power saving portion of the invention involves the useof complementary metaloxide semiconductors (CMOS) as switching elements and in the counters. It will be appreciated that the metal oxide semiconductor devices draw current only when they are switching (i.e., changing state).

In addition to power consumption advantages'of the subject circuit, the multiplexing circuit utilized herein eliminates redundancy in the decoder and driver elements necessary for driving the hours, minutes andseconds portions of the display. The numbers of elements are also decreased by provision of .a quadrant or sector system of addressing the light emitting diode elements. An additional and a most important function of the multiplexing circuit is to reduce the aforementioned duty cycle. What the multiplexing circuit does is to sample the seconds, minutes, and "hour counters at a high repetition rate with a low duty cycle as dictated'by sampling pulses of short duration. If the information in the counters is sampled once every onesixty-fourth of a second, the information is actually flowing out of the multiplexer for only a small portion of this one sixtyfourth second time period clue to the short sampling pulses. At all othertimes, the output of the multiplexer is inhibited. Thus'the multiplexer II'I'BddIIIOII to sequentially reading out the information stored in the counters also serves the purpose of reducing-the duty cycle ultimately for the light emitting diode in the display. A further advantage occurs with the multiplexing circuit when used in conjunction with a display in .which time is displayed by three diodes. Although it looks as if three diodes are continuously lit during one sampling cycle, this is not so. In any given sampling period only one diode is lit at a time. This is because the seconds, minutes and hours information is not simultaneously read out but rather is read out over mutually exclusive time intervals. This means that peak battery current drain is minimized so that high impedance batteries may be used.

The sampling is accomplished in the subject circuit by coincident gating within the multiplexer circuit. The timing pulses for the sampling are derived from the aforementioned divide-by-two countdown circuit which provides the I Hz signal for driving the counters.

In addition, the counters consist of toggle-type flipflops which are so arranged to have a binary output. These toggle-type flip-flops are utilized rather than JK- type flip-flops because of the aforementioned decrease in number of transistors necessary. While toggle-type flip-flops are usually utilized only in countdown circuits, they are utilized in this application as binary encoders. In the configurations to be described herein the toggle-type counters are easily matched to a NAND- type decoder circuit which is also available in MOS form.

It will be appreciated that the choice of the two level voltage in a strobed multiplexer circuit, MOS type components and the logic to be described are important primarily because of power consumption savings. They are further chosen because of the saving of individual component parts. 11

SUMMARY OF THE INVENTION It is therefore an object of this invention to provide an improved logic and driving system for use in light emitting diode horologic display.

It is a further object of this invention to provide in combination an oscillator circuit; a divide-by-two countdown circuit for providing a I Hz signal; seconds, minutes and hours counters cascaded to form storage elements having an output in binary form; a multiplexer circuit which provides for sequential readout of the seconds, minutes and hours counters as well as providing for a low duty cycle driving signal; a binary-to-pulse decoder, and a driving circuit which responds to the pulsed output of the decoding circuit for actuating individual light emitting diode elements in the horologic display.

It is a still further object of this invention to provide a horologic display in which the time is represented by an outer ring of elements representing seconds and minutes, and an inner ring of elements representing hours in which the outer ring of elements is dividedinto sectors such that all the elements are driven by a single driver connected in parallel with the corresponding elements in each sector and is further provided with a sector selector such that only one sector and therefore only one element in each sector is driven at any one given time.

It is a still further object of this invention to provide a driving circuit for a light emitting diode horologic display in which the high frequency circuits are powered by a first voltage while the lower frequency circuits are powered by a second voltage higher than the first voltage such that power consumption is minimized.

It is a still further object of this invention to provide a binary logic system utilizing toggle flip-flops and NAND gate reset logic to provide information which when decoded and supplied to a driving circuit actuates the light emitting diode display.

It is a still further object of this invention to provide a multiplexed logic and driving circuit for light emitting diode display in which the multiplexing circuit samples seconds, minutes and hour information available in binary form from counters in a sequence and for a sampling duration which minimizes the duty cycle of the light emitting diodes in the display while at the same time conserving on the number of driving elements, thereby conserving greatly on the power dissipated both by the driving circuit and by the light emitting diode display elements.

It is yet another object of this invention to provide logic and drive circuitry for a horologic display utilizing a logic permitting the use of metal oxide semiconductor logic parts.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the logic and driving circuits for a light emitting diode display;

FIG. 2 is a diagrammatic view indicating the manner in which the time of day is read out from the aforementioned light emitting diode display, also indicating an asymmetrical sector arrangement indicating in addition the method of actuation from the output of the driver shown in FIG. 1;

FIG. 3 is a block diagram showing generically the circuit configurations of the multiplexer, the decoder, the sector selector, and the driver circuit, referred to in FIG. I;

FIG. 4 is a pulse train diagram showing the sampling times and the sampling period of the pulses delivered to the multiplexer which in turn result in the aforementioned low duty cycle;

FIG. 5 is a block and schematic diagram of the frequency dividing circuit utilized to count down the frequency available from a crystal oscillator to 1 Hz also showing a pulse shaper and level translator utilizing in matching the high frequency section of the device to the low frequency section of the device;

FIG. 6 is a pulse train diagram showing the derivation of 41 (b and d) from intermediate outputs of the frequency dividing circuit shown in FIG. 5;

FIG. 7 is a block diagram of a binary seconds or minutes counter utilizing toggle-type flip-flops to indicate a binary number corresponding to integers between 0 and 59;

FIG. 8 is a block diagram of a counter circuit for indicating hours in binary form in which toggle-type flipflops are utilized to represent in binary form integers between 0 and II;

FIG. 9 is an expanded diagram of the multiplexer circuit shown in connection with FIG. 3;

FIG. 10 is an expanded diagram of the decoder circuit shown in connection with FIG. 3;

FIG. I] is an expanded diagram of the driver circuit shown in connection with FIG. 3;

FIG. 12 is an expanded diagram of the sector selector circuit shown in connection with FIG. 3; and

FIG. 13 is a diagram showing the arrangement of the light emitting diodes to be driven by the output of the driver and sector selector circuits shown in connection with FIGS. 11 and I2.

BRIEF DESCRIPTION OF THE INVENTION There is disclosed a logic and driving circuit for a light emitting diode type horologic display in which three diodes are read out at any given time torepresent the time of day. Power consumption is kept to a minimum by the use of a two voltage level system with the lower voltage supplying those portions of the circuit working at a high frequency while the higher voltage supplies the display and those portions of the driving circuit operating at a considerably lower frequency. In addition to a crystal frequency standard and a divideby-two flip-flop countdown circuit which provides a 1 Hz signal to a series of toggle flip-flop counting circuits which function as the seconds, minutes and hours storage elements, there is provided a multiplexer coupled to the outputs of these counting circuits which is strobed with pulses having a combined duration of only a fraction of the sampling cycle. This results in a low duty cycle for the output of the multiplexer and thus for the display itself which conserves on the power necessary to drive the display. Since hour, minute and second information is sequentially sampled by the multiplexing circuit, multiplexing eliminates decoder and driver redundancy. Provision is made in the multiplexing logic for dividing the horologi'c display into quadrants or sectors so as to further reduce the number of driver and decoder elements. As a result there is also provided a quadrant selecting circuit. The sampling pulses for the multiplexing circuit are conveniently derived from the frequency standard countdown circuit. The driving system utilizes complementary metal oxide semiconductor (CMOS) components in which power drain is minimized because these elements draw appreciable power only when switching. A further power consumption advantage is obtained by utilizing NAND gate logic to permit the use of these low power CMOS components. Toggle flip-flops are chosen for the counters because they are available in metal oxide semiconductor form and because the total number of transistors utilized is reduced. The logic described herein is used with a horologic display in which the minutes and seconds are displayed in the single ring of elements with the hours being displayed in another single ring of elements.

DETAILED DESCRIPTION OF THE INVENTION As mentioned hereinbefore the subject logic and driving circuit is tailored to a type of horologic display in which the time of day is read out by three light emitting diode elements. It will be appreciated, however, that many of the concepts utilized in power conservation in the driving of this display can be equally well utili'zed in the driving of any XY addressable display in which power consumption is a major factor. Thus, al-

though the subject logic and driving circuits are described in connection with the horologic display in which the time of day is represented by two rings of light emitting elements, any system in which pulses are provided on output lines of a driving circuit is within the scope of this invention.

Referring now to FIG. 1, a horologic display 100 is shown with an outer ring 101 of 60 light emitting diodes, and an inner ring 102 of 12 diodes. The time of day in this display is indicated by the sequential activation of the individual light emitting elements. In this display, minutes and seconds are represented by utilizing the same set of light emitting elements. TI-Ie importance of representing time by using the same light emitting elements for seconds and minutes is the saving of as many as 60' light emitting elements. The display to which the subject logic is tailored therefore minimizes the number of light emitting elements by portraying minutes and seconds on the same ring by the same set of elements. There are of course other ways of representing time utilizing concentric rings of time indicating elements in which multiplexed readout of counters having binary outputs drives these elements. In addition, for instance additional elements may be added to indicate half hour of 20 minute intervals. In the configuration shown involving a set of 60 elements arranged so as to define a closed geometric curve or ring 101, minutes are portrayed by sequentially actuating successive light emitting elements clockwise around the ring 101 within on durations of 1 minuteQSimultaneously, each of the elements in this ring are lit sequentially in a clockwise direction for one second such that at any given minute the seconds indications have been stepped around the ring until they reach the 12 oclock position. At this time the minute indication is stepped ahead so as to indicate the start of a new minute with the second indicator corresponding to the first second of this new minute. The hours are represented by the concentric ring 102 which are actuated sequentially having a 1 hour duration. The time indicated by the display as shown by the darkened light emitting diodes 103, 104 and 105 is 1:12 and 39 seconds.

The driving circuit for display 100 generally consists of a frequency standard indicated by oscillator and countdown circuit 115, which produces a precise 1 Hz signal. This signal is coupled through a level translator to a second series of countdown circuits involving counters 130, 131 and 132 which serve as storage elements for seconds, minutes and hours information. The output of these counters is in binary form such that the information contained in each one of these counters is sequentially read out or sampled by a multiplexing cir' cuit 140. The binary information sampled by the multiplexing circuit is coupled to a decoding circuit which provides a pulse of one of 16 output lines depending on the binary number stored in the particular counter read out by the multiplexing circuit 140. This pulse activates a driver circuit which in turn drives simultaneously all five of the sectors into which the display 100 has been divided. In addition, a portion of the output of the multiplexer circuit drives a sector selector which selects which of the aforementioned five sectors is to be enabled. The enabling of only one of the five sectors results in the activation of only one diode for each sampling pulse to the multiplexer circuit 140. The inner ring 102 of 12 diodes representing hours is in essence one sector which is activated in the timed sequence determined by the multiplexer circuit such that when the hour counter is read out by the multiplexer circuit, the sector selector is directed to enable the hour sector. The minutes-seconds ring 101 is divided into four sectors so that both the sector and the particular element in the sector must be driven to light a particular element.

Referring to the oscillator 110, it is a crystal oscilla tor with the crystal 111 having a frequency of 65, 636 Hz. This corresponds to 2 Hz. The output of the oscillator is coupled to a divide-by-two countdown circuit shown diagrammatically in the dotted box 115. This is composed of a series of flip-flops shown diagrammatically at 116 which basically divide the output of the preceding flip-flop by two. Thus, by the use of 16.individual flip-flops, the 2 Hz oscillator output is reduced to 1 Hz. There are however intermediate outputs from the countdown circuit which are utilized for forming the sampling pulses for the multiplexer. These readouts are tapped from the outputs of various of the flip-flops and represent respectively a 256 Hz signal, a 128 Hz signal, and a 64 Hz signal. These intermediate signals are coupled to the pulse shaper and level translator I20 and thence to the multiplexer circuit 140 where they serve to cycle the multiplexer such that a sampling period takes one sixty-fourth of a second with the individual sampling times occupying in one embodiment only 12.5 percent of this one sixty-fourth sampling period. As mentioned hereinbefore, the high frequency circuits are supplied with a lower voltage, thus conserving power. The high frequency circuits are the oscillator circuit 110 and the countdown circuit 115. In order to enable the use of the pulsed signals generated by the countdown and oscillator circuits, there is of necessity a level translator which makes the signals at the output of the countdown circuit compatible with those of the multiplexer and the counter circuits 130, 131 and 132. The 256 Hz signal has a dual purpose insofar as it is utilized in forming the sampling pulses for the multiplexer circuit 140 and as speeds time setting signal. As can be seen, the output of the level translator 120, at least in one configuration, is a 1 Hz signal designated Y, and a 256 Hz signal designated by the letter Z. In ordinary operation the switch 136 is in the position shown coupling the counters 130, 131 and 132 to the 1 Hz signal. If, however, it is desired to change the time displayed by the subject horologic display, switch 136 is coupled to a higher frequency signal, in this case the 256 Hz signal, which peeds up the counting operation until the appropriate time is reached at which point switch 136 is returned to the position shown in FIG. 1. This 1 Hz output signal is coupled directly to the seconds counter 130 which operates in such a manner as to count the number of bits of information delivered thereto between and 59 (i.e., 60 bits). The state of the counter is indicated by a binary output of 6 bits as shown by the output lines 133. In the configuration shown, the state of the counter is changed on the negative going edge of an incoming pulse. What this means is that the flip-flops used in the counters are set by the leading edge of an incoming pulse and are toggled by the trailing edge. After 59 bits have been counted; seconds counter 130 resets and also simultaneously delivers a first pulse to the minutes counter 13]. Minutes counter is identical to the seconds counter in that it has 6 flip-flops. Thus its state is also represented by a binary number of 6 bits. The output in binary form of the minutes counter 131 is shown by the output lines 134. Thus, the seconds counter 130 must cycle through all of its 60 bits before the minute counter receives its first pulse. Likewise, the minute counter must cycle through its 60 bits before the hour counter 132 receives its first pulse. The hour counter is provided with four flip-flops and thus its state is represented by the four output lines 135. At the end of 12 bits this counter is reset. It will be appreciated that counters 130 and 131 have six flipflops each. It is therefore possible for these counters to count up to 63 in binary form. However, these counters are reset after they reach a count of 59 by a logic to be described hereinafter. Likewise, counter 132 can count up to 15. However, this counter is reset after it reaches a count of I], thus representing 12 bits. These counters, as mentioned hereinbefore, are constructed of toggle-type flip-flops with attendant NAND gate logic circuitry to make the counters operate in the above fashion. They are toggle-type flip-flops rather than J K-type flip-flops because toggle-type flip-flops use less transistors in the form shown than do .IK flip-flops. As has been mentioned hereinbefore that the available of these devices in MOS form contribute significantly to power consumption reduction. It will be appreciated that there is an analog in the JK flip-flop counter art to the toggle flip-flop once the NAND gate-inverter logic shown in connection with FIGS. 7 and 8 is known. Also, any binary encoderswhich count pulses and generate a binary output can be used with the multiplexer.

In the configuration shown, the information in binary form is available at outputs 133, 134 and 135 which are coupled to the multiplexer circuit 140. The multiplexer circuit is basically a coincident gate-type circuit such that when enablingpulses 5 or (1 appear, either the seconds counter or the minutes counter or the hours counter is read out to both the decoder unit 150 and the sector selector 170. (1) and 4),, are generated from outputs of the countdown circuit by the pulse shaping portion of the level translator 120. After tb d) and :11 are generated, they are level translated by level translator so as to be compatible with the multiplexer circuit which generally operates at 3 volt level as opposed to the 1.5 volts supplied to the high frequency circuits mentioned hereinbefore. and d) are not however coextensive with the outputs of the various flip-flops from which they are derived. As will be discussed in FIG. 5, the outputs of the three selected flip-flops from which (it 11),, and 15 are derived are coupled to NAND gate circuitry such that a series of three sequential pulses are produced spaced apart by considerable dead air time. (b 4),, and (b are coupled to the multiplexer 140 to cause the multiplexer to sample the outputs of the counters in mutually exclusive and separated time intervals within the sampling cycle. The sampling takes place only over the time at which (1) 41 and 4),, appear. This results in the seconds counter being read out during the duration of the pulses da the minutes counter being read out during the duration of the pulse 4) and the hour counter being read out during the duration of the pulse (1) At all other times the output of the multiplexing circuit is a binary coded set of words which are incapable of actuating any light emitting diodes in the display. Thus when the term low duty cycle is used it refers to the fact that the light emitting diodes have a low duty cycle. In actuality none of the other components in the system are inhibited during dead air time." It is sufficient that only the display has the low duty cycle since it draws the majority of the power. In one embodiment the sampling time for one pulse is only 12.5 percent of the entire sampling cycle. If three samples (i.e. (1: and (1) are made during the sampling cycle the sampling pulses take up only 37.5 percent of the sampling period.

As mentioned hereinbefore the output of the multiplexer in addition to being coupled to the decoder which decodes either the seconds, minutes or hours numbers, is also coupled to the sector selector 170. It will be appreciated that the aforementioned ring of 60 elements is divided into four parts or sectors. These parts are, however, not equal for reasons which will be described hereinafter. At this point it is only necessary to note that the sector selector is activated by the last two bits of information from either the seconds counter or the minutes counter. The hours sector is activated merely by a pulse appearing on the line 41,, since it is completely separate from the other four sectors utilized to activate the outer ring of elements. However, the outer ring of elements being divided into four parts must be actuated in some orderly manner depending on the numbers in the seconds and minutes counters. The sector which these numbers occupy is conveyed to the sector selector as the last two bits of information in each one of these counters. These last two bits of information in conjunction with d) and dz instruct the sector selector in which sector the information being read out by the multiplexer 140 is to be placed. Thus, although there are 60 elements in the outer ring 101, the driver need only have 16 outputs as shown in FIG. 1. These 16 outputs are connected in parallel to corresponding elements in each one of the first three sectors. The fourth and hour sectors however have only 12 elements and therefore only the first 12 of the output lines of the driver are connected in parallel to corresponding elements both in sectors I-III and the fourth and hour sectors. Actually, the fourth sector is designated sector No. II in keeping with quadrant" designation commonly used in analytic geometry.

' Neglecting for the moment the hours activation, the minutes and second activation is accomplished by the use of only 16 driving lines and four quadrants making this akin to an XY addressable array. If, for instance, 10 minutes past the hour is to be represented,

during the minutes segment of the multiplexing, quadrant I is enabled by grounding it, while the binary number corresponding to 10 is decided by the decoder 150. The decoding circuit enables a section of the driver 160 which then connects to V one electrode of corresponding elements No. 10 in each of the sectors. Thus V is fed in parallel to the element No. 10 in quadrant" I, the element No. 10 in quadrant II, the element No. 10 in quadrant III, and the element No. 10 in quadrant IV. However, since only quadrant" I is grounded, diode No. 10 in quadrant I is the only diode which is connected between V and ground.

Outputs zero through 11 of the driver 160 are also coupled to the inner ring of elements 102 such that the No. l element is also connected to V via output line 10. However, since only quadrant l is activated, the delivery of this pulse to this element has no effect. However, if o'clock is to be represented, then the hour sector is grounded in conjunction with the connection of V to the No. l0 element via output line 10. This causes the 10th diode in the inner ring 102 to become lit during that portion of the multiplexer sequence which reads out the number l0 contained in binary form in hour counter I32. Thus, it can be seen that the sector selector 170 is only necessary to distinguish between seconds readouts and minutes readouts with the hours readouts being directly actuated by is shown to pass directly through the sector selector 170. As mentioned hereinbefore the minutes and seconds readout is a bit more complicated. During the time when the seconds are read out, the last two bits in the seconds counter instruct the sector selector 170 to actuate the appropriate quadrant." When it becomes time for the minutes counter to be read out, the multiplexer also instructs sector selector 170 which quadrant is to be actuated. However, since the hours are not segmented in any form there is no necessity to instruct a sector selector which quadrant to actuate because there is only one sector as far as the hour light emitting diodes are concerned. It will be appreciated that there are five sectors, with the first four sectors designated as quadrants so as to distinguish outer ring actuation from that of the inner ring.

The matter of actuation of this subject display is described in connection with FIG. 2. In this diagram, the minute-second portion of the display is divided up into four quadrants as shown. The first quadrant has 16 light emitting diode elements associated with it. These run from positions zero through 15. Going clockwise the fourth quadrant also has 16 elements going indicated from positions zero through 15 as does the third quadrant. The fourth quadrant however has only I2 elements which run from positions zero through 11. This asymmetric division of the of the elements is indicated by the particular seconds, minutes and hours counters employed. It is of course possible to use other types of counters such that the quadrant" representation is made symmetrical. However, if symmetrical quadrants are used more complicated decoders and more complicated counters are necessary. It will be appreciated that the asymmetrical division of quadrants described is chosen because it greatly simplifies the logic circuitry required. For example, if four equal quadrants" of 15 elements each are employed with a 6 bit 0-59 counter, counter outputs 16, 31 and 47 would not be decoded although they are states of the counter which exist during each cycle. Thus, an error of 3 units per cycle would be introduced. To circumvent this problem four 0-l4 counters could be used instead of one 0-59 counter for seconds and minutes. This would require 16 flip-flops instead of 6 flipflops as described herein. The outputs from driver of FIG. 1 are shown to the bottom left-hand side of diagram shown in FIG. 2.It will be appreciated that the outputs from the driver 160 are connected in parallel not only to those corresponding elements in each one of the quadrants," but also to the corresponding element in the hour ring (hour sector). Thus, the zero output line is connected to the quadrant I zero, the quadrant II zero, the quadrant III zero, and the quadrant IV zero as well as to the hour sector zero which in this case represents the hour of 12 oclock. Likewise, for instance, the llth output is coupled simultaneously to the llth element in the first quadrant, the l lth element in the second quadrant," the l lth element in the third quadrant, and the l lth element in the fourth quadrant. It is also connected to the l lth element in the hour ring (hour sector). Output lines 12 through 15 are however only connected to those corresponding elements in quadrants" I, III and IV. It will be obvious that there is no element for them to be connected to in quadrant" II or in the hour ring sector. As mentioned hereinbefore, the hourring is represented by a single sector which is driven oractuated during the hour readout portion, dz of the multiplexing cycle. However, for the seconds and minutes readout the quadrants" I, II, III and IV are read out in accordance with the binary number in the seconds or minutes counter which is activated or read out by the multiplexer 140. Thus, there are only three light emitting diodes read out in a given sampling cycle. In the embodiment shown in the Figures, the minute, second and hour are read out once every one sixty-fourth of a second or 64 times a second. This provides for a seemingly continuous readout of the light emitting diode display. It is however not continuous since the sampling cycle takes place over one sixty-fourth of a second and the actual readout takes place over only 12.5 percent of the cycle. Thus the diodes in the display are lit for only 12.5 percent of the time. This 12.5 percent figure in conjunction with the one sixty-fourth of a second sampling rate provides the user with what appears to be a continuous readout of a time period in excess of one year. It will be appreciated that other acceptable duty cycles are feasible going as low as 1.56 percent and as high as 25 percent.

The logic involved in the subject system is now described in general. As mentioned hereinbefore, each of the aforementioned counters 130 through 132 have an output in binary form. The output for the seconds counter 130 is in the form of 6 bits designated A through F The binary output of the minutes counter 131 is designated A through F and the output of the hours counter is designated A through D For reference the corresponding binary number table of through 63 is now presented.

TABLE I No. FEDCBA No. FEDCBA 0 O 0 0 0 0 0 32 l 0 O 0 0 0 1 0 0 0 0 0 1 33 l 0 0 0 0 1 2 0 0 O 0 l 0 34 l O 0 0 1 0 3 0 0 0 0 1 l 35 1 0 0 0 l l 4 0 0 0 l O O 36 l 0 0 l O 0 0 O 0 l 0 l 37 l 0 0 l O l 6 0 0 0 1 1 0 38 1 0 0 1 1 0 7 0 0 0 l l l 39 l 0 0 l 1 1 8 0 0 1 0 0 0 40 l 0 l 0 0 0 9 0 0 l 0 0 1 41 l 0 l 0 0 1 l0 0 0 1 0 l 0 42 l 0 l 0 1 0 11 O 0 1 0 l l 43 1 O l 0 l 1 12 0 0 l l 0 0 44 l 0 1 l 0 0 l3 0 0 1 1 0 1 45 l 0 l l O l 14 0 0 1 l l 0 46 1 0 l 1 1 0 l5 0 0 1 l 1 l 47 l 0 l l 1 1 l6 0 1 0 0 0 O 48 l l 0 O 0 0 l7 0 l 0 0 0 l 49 1 l l 0 0 1 l8 0 l 0 0 l 0 50 1 l O 0 1 0 l9 0 l 0 0 l 1 51 l l 0 0 l l 0 l 0 l 0 0 52 l l 0 1 0 0 2| 0 l 0 1 0 l 53 1 l 0 1 0 l 22 0 l 0 l l 0 54 1 l 0 l l 0 23 0 l 0 l l l 55 1 l 0 l l l 24 0 l l 0 0 0 56 l l l 0 0 0 0 1 l 0 O l 57 1 l l 0 O l 26 O l l 0 l 0 58 l l 1 0 l 0 27 O l l 0 l l 59 1 l l 0 l l 28 0 l l l 0 0 6O 1 l 1 l 0 0 29 0 l l l 0 l 61 l 1 l l 0 1 Not 0 l l l l 0 62 l l l l l 0 Used 3| 0 l l 1 1 l 63 l l 1 l l 1 As shown at the bottom on FIG. 3, the outputs of counters 130 and 131 and 132 are coupled to the multiplexer circuit 140. In general, each of the corresponding outputs of each of the counters is connected as shown in the multiplexer circuit to three corresponding NAND gates 141, 142 and 143. The outputs of these NAND gates form the inputs for a further NAND gate 144. Positive true" logic is used in this system (i.e., a logic 1" is represented by a positive voltage potential approximately equal to the supply voltage whereas a logic 0" is represented by an approximately zero voltage potential). The NAND gate produces a logic high or 1" output if one or more of its inputs are low. A logic low is generated if, and only if, all of the inputs are high. Taking, for instance, the A output from each of the counters (A A A each of these form one of the inputs for the aforementioned NAND gates 14] through 143. The other input for each of the NAND gates 141 through 143 is the sampling signal which permits readout of the particular counter. For instance, if it is desired that the seconds be read out a logic 1 signal 4),,- is applied simlutaneously with the A, signal to NAND gate 141. If A is a logic 1 signal, the coincidence of the 42 and the A signal results in a logic 0 signal A This signal is coupled to NAND gate 144 such that a logic 1 output of gate 144 indicates the simultaneous presence of an A logic 1 signal and the tb signal. NAND gate 144 produces this logic 1 signal because the other signals to this NAND gate will be logic 1" during the presence of a sampling pulse. Thus during sampling only one signal from gates 141-143 will be low. This is the condition ofa logic l output from NAND gate 144. The same is true for the minutes sampling signal 1b,, and the hours sampling signal (b It can be seen therefore that the multiplexer utilizes coincident-gate sampling. The multiplexer section shown in FIG. 3 is but one of many such sections corresponding to the six outputs from the seconds and minutes counters and the four outputs of the hours counter. The output of gate 144 is a logic level signal which indicates the simultaneous presence of either A S and (1, or AM and rim, or A and (b signals. There is also provided in the multiplexer an inverter circuit 145 which produces the complement of that which is produced at the output gate 144. The analysis of the multiplexer circuit is a direct consequence of demorgans laws.

The output of the multiplexer circuit is coupled to the decoding circuit which in general is a simple circuit involving 16 NAND gates. One of these gates is represented by the reference character 151 to be that corresponding to the A, B, C', D outputs of the multiplexer corresponding to the A, B, C and D outputs from a counter. The prime after these letters indicates that these are in fact sampled. In other words, there is either a 45 a 4) or 4a,, which enables the information A, B, C, and D to be read out. Referring to Table l, the presence of logic 1s" in A, B, C, and D represent the number 15, the number 31, and the number 47. the selection of which of these numbers is represented by the display is accomplished by the sector selector 170. lgnoring for the moment the hours indications since this number does not exist on the hours ring, the input to the sector selector is two fold. The first inputs are the enable inputs, and 4) These are coupled to inverters 171 and 172 such that the output thereof is HT and a; (i.e., logic 0s). Utilizing a further NAND gate 173 its output is a logic 1 when 41 or 4a,, are present at inverters 171 and 172. Thus whenever or 4; is present the "quadrant" portion of the sector selector is enabled. This means that there is a logic 1 signal at one of the inputs to NAND gate 174. The output of gate 173 is thus an input to gate 174 which is also a NAND gate. The other two inputs to this gate are the E and F outputs from the multiplexer circuit and thus correspond to the sampled E or F outputs from the minutes and seconds counter. In this case the F output of the counter is a logic 0. This is recognized by the multiplexer which generates a logic 1" signal on its 1 output line. The multiplexer generates logic 1 signals indicating a logic 0 signal from a counter. Thus all Y signals referred to herein are available as logic 1 signals from the multiplexer. E and F indicate that a logic 1 exists a t NAND gate 174. With three logic "1 signals (E', F, (b) the output of gate 174 is low.

This is converted to a high signal by inverter 175. This logic high signal then renders NPN tran sistor 161 conductive. From Table I the presence EF indicates that the number 31 is to be selected over the number 15 and the number 47. To reiterate, the output of the NAND gate 174 in combination with the inverter circuit 175 indicates that there is a sampling of either the seconds or the minutes counter, and that the quadrant indi eating the number 31 should be activated. This quadrant," referring to FIG. 2, is quadrantTlV. A logic 1 signal therefore from the output of inverter 175 is delivered to the base of the NPN transistor 161 in the driver circuit 160. This particular NPN transistor is coupled between one electrode of each of the light emitting diode devices 162 of quadrant" IV and ground. The other electrode of these light emitting diodes is connected to the collectors of PNP transistors 163 whose emitters are connected to V 3 volts. The output of the decoder gate 151 is coupled simultaneously to the base of those transistors coupled to corresponding light emitting diodes in each quadrant. Thus a logic generated by the presense of A", B, C, D at NAND gate 151 is coupled to the base of transistor 163' at the same moment that a logic l is delivered to the base of transistor 161. Thus the LED 162' is connected to both V and ground.

For any given state of the decoder 150 and the sector selector 170, only one diode is actuated or lit. The results in the aforementioned low peak current drain and the feasibility of using low cost high impedance batter- Referring now to the hours actuation, the presence of 4),, at the base of transistor 165 enables all of the light emitting diodes 166 in the hour ring. If, for instance, the decoder gate corresponding to F, 1?, G and I? were actuated, corresponding to a count in the hours counter of 0000, then at sampling time the diode representing 12 oclock would be lit. This is because the particular decoder gate produces a logic 0 signal when logic I signals A, E 3 and occur at the NAND gate in the decoder. All of the other gates have logic 1 outputs. The gating in the driver circuit simply renders conducting the transistors on either side of the light emitting diode which is to be actuated. The diode is therefore connected between a 3 volt power supply and ground through the NPN and PNP transistor across which it is connected in series. Various biasing resistors 167 are provided to complete the partial schematic diagram of the driver circuit 160 shown in FIG. 3.

Referring now to FIG. 4, it will be apparent that the entire multiplexer circuit operates on the principle of coincident gating. However, the sampling period is dietated by the length of the sampling pulses, tb tit and d) The length of the sampling pulses is considerably reduced by narrowing these pulses. Since the output of the multiplexer circuit 140 actuates the display, only during the presence of a sampling pulse, by narrowing the sampling pulses the output of the multiplexer can be maintained at a zero level for a considerable portion of time. As shown in FIG. 4, in one embodiment the samepling cycle is one sixty-fourth of a second as shown by the distance between the leading edges of consecutive pulses 180 and 181 of the s sampling pulse train. However, the combined? widths of pulses 180, 182 and 183 only occupy about 12.5 percent of the one sixty-fourth second time period. The duty cycle for this logic and driving system is therefore defined to be the combined pulse widths of the seconds, minutes and hours sampling signals as compared with the length of time between the leading edges of two consecutive tps sampling pulses. Since the ouput of the multiplexer does not actuate the display for approximately 87.5 percent of the time, the decoder circuit, sector selector circuit and the driver circuit are actuated for only 12.5 percent of the time that the display is running. Thus, the light emitting diodes are actuated for only 12.5 percent of the time that the display is running. Since NAND gate circuitry is utilized, and since complementary metal oxide semiconductor devices are utilized, the power saving with the circuit thus described in general, is considerable.

A more detailed description of the operation of the preferred embodiment of this invention is now described in detail in connection with FIGS. 5 through 13.

Referring now to FIG. 5, an expanded diagram is shown in which the signals 42 41 4) Y and Z are derived. Included in dotted box are the last nine of the flip-flops in the countdown circuit 115. As can be seen, these are labeled F/F through FIF Each flipflop has two outputs. The first being a 6 output, and the second being the Q output. As mentioned hereinbefore, the output of F/F, is a 1 Hz signal. Since the countdown circuit 115 is supplied with a 1.5 volt potential, the output Q, must be converted to be compatible with the 3 volt follow-on systems. In order to accomplish this, the 0, output is coupled to the base of an NPN transistor 121 in the pulse shaping and level translating circuit 120. When transistor 121 is ofi, the voltage at point 122 is high since no current is being pulled through this transistor. This voltage then corresponds to the 3 volt potential at point 123. When, however, Q, is applied to the base of transistor 121 as a logic high, transistor 121 goes into conduction pulling the point 122 low by the IR drop across the resistor 124. Thus the output Y is an inverse replica of the output 0,. This same procedure is used for the time set output Z enclosed in dotted box 125. Here the transistor 121' is coupled to the Q output of F/F When the Q output of FIF is high, 122' is low because of the voltage drop across the resistive element 124'. The time set signal is equal to 256 Hz which in the worse case can reset the clock in about 6 minutes. It will however be appreciated that the tap for the base of transistor 121' can be taken off a higher numbered flip-flop such that the frequency of the signal at Z is increased proportionately thereto. The signals tb d) and d) are derived from the Q Q 2 Q and 1 outputs of flipflops 116 as follows. As shown, the Q, output of HE, is coupled to one of the inputs of each of NAND gates 126, 127 and 128. The 6,, outputof F/F is coupled to another of the inputs to NAND gate 127. The 0,, output of F/F is coupled to another of the inputs of NAND gates 126 and 128. The 6, output of F/F, is coupled to the last of the inputs to NAND gate 128 while the Q, output of F/F is coupled to the last of the inputs to NAND gates I26 and 1 27. The outputs of these NAND gates drive the basesof transistors 121", 121", and 121"" respectively. The boolean algebraic expressions for the outputs of NAND gates 126 through 128 are as shown. By going through demorgans theorem recognizing the properties of the level shifting transistors 121, da dz and'qm are generated as shown in FIG. 6 having been derived from the outputs of FlF F/F and F/F,. The remaining resistors 119 are for biasing purposes. It will be appreciated that the pulse widths of tb 4) and d) are equal to that of Q but the repetition rate is equal to that of 0,. Thus the combined pulse widths of tb d) and d) are only 37.5 percent of the period of 0,.

Referring now to FIG. 7, the seconds/minutes counter is shown in dotted outline. The toggle flip-flops described herein require two trigger (or clock) pulses which are out of phase T andT The flip-flops trigger (i.e., change state) upon the transistion of the T input pulse from a high to a low state. The toggle flipflops employed require only 17 MOS transistors per flip-flop which is about one-half the transistors required for a JK flip-flop. Thus, while more NAND gates and inverters are necessary to make a counter (0-59) or (0-l) with toggle flip-flops than JK flip-flops, the total numbers of transistors required for a counter may be less with toggle flip-flops. It should be noted through-out the following discussion of the operation of the counters that the first pulse is the 0th pulse and the 59th pulse therefore represents a count of 60. Likewise, in the hours counter the llth pulse represents a count of 12. This agrees with the boolean Table I. Taking, for instance, this counter as the seconds counter 130, it is composed of six toggle flip-flops 138 labeled A, B, C, D, E, and F respectively. It is the purpose of this counter to store the number of pulses received of from zero through 59. If it were the purpose of this counter to recognize zero through 63 incoming pulses, the toggle flip-flops would be cascaded in the normal manner, and no additional logic elements (NAND gates and inverters) would be required. How ever, in order to stop the toggle flip-flop count at a point corresponding to the 59th incoming pulse and to reset it after this 59th incoming pulse requires the use of NAND gate logic coupled with the inverters as shown. This NAND gate logic assures that the outputs of the six flip-flops are all reset to zero on the trailing edge of the 59th pulse. The system for limiting the count of this counter centers around the use of four NAND gates and four inverter circuits. The input to the counter is the 1 Hz Y signal across the switch 136 which goes directly to the T input of flip-flop 138A. The Y signal is inverted by the inverter 137 and is then coupled to the T input of this first toggle flip-flop. The outputs of the first toggle flip-flop (138A) are coupled directly to the inputs of the 13813 toggle flip-flop. Thereafter the switching theory becomes indeed complicated. Referring to Table l, and remembering that the flip-flops toggle on the negative going edge of a pulse it will be appreciated that in the seconds/minutes counter, if the counter is allowed to run up past 59 counts, nothing needs to be done about inhibiting the input to flip-flops 138A and 1388 because the change from 59 to 60 is the same as a change from 59 to zero (i.e., the outputs of flip-flops 138A and 1388 will be the required zero" after the 59th pulse has passed). The 138C counter after the 59th pulse would ordinarily go to a logic l." Some type of circuitry is therefore needed to maintain the output of flip-flop 138C at its zero level (no toggle). The inputs to flip-flop 138C are therefore inhibited during the passage of the 59th pulse so that the trailing edge of the 59th pulse does not toggle flip-flop 138C. The passage of the 59th pulse is indicated when D, E and F are all logic ls" and B goes from a high to a low. D, E, and F are thence the inputs to a NAND gate as shown by 139. An output low from gate 139' indicates the presence of D, E and F at its inputs as logic ls. This output low (i.e., logic 0 is coupled to one of the inputs of a NAND gate 139". The input to flip-flop 138C is ordinarily the B output of flip-flop 1388. What is done in effect is to inhibit this B output of flip-flop 1388 from reaching the input to flip-flop 138C when D, E, and F are present at the output of their respective flip-flops and when B goes from a logic 1 to a logic 0." From the first table, D, E, and F are logic ls from 56 through 59. However, during this interval B only goes from a high to a low after the 59th pulse. The fact that B goes from a low to a high does not trigger the 138C flip flop. The toggle flip-flop only changes state when its input goes from a logic high to a logic low (the negative going edge of a pulse). Therefore, the only time at which the input to 138C is inhibited is after the 59th pulse input. The T input to flip-flop 138C is therefore the output of inverter 146' (i.e., B DEF). The output of gate 139' (BDEF) is thence coupled to the T input of flip-flop 138C to complete the toggling.

At the passage of the 59th pulse flip-flops D, E, and F would not normally change state and would be logic 1. it is therefore necessary in order to return the counter to the 000000 first state to cause flip-flops D, E, and F to toggle. Since these flip-flops are cascaded, it is only necessary to toggle the D flip-flop in order to toggle E and F flip-flops back to the original D=0, E=0, and F=0 state. This is accomplished as follows: Normally flip-flop 138D toggles in response to the output of flip-flop 138C changing from a logic 1" to a logic 0". This is because the output of 139"" goes low on the appearance of a logic l pulse at the 6 output of the 138 flip-flop. However, flip-flop 138D is made to toggle either on the E input to gate 139"" or on an ABDEF condition since the ABDEF condition occurs only on the 59th pulse on the 60th pulse. A and B change to a zero which causes the output of 139"to go high. This causes the output of 139"" to go low, thus toggling the flip-flop 138D. Therefore, flip-flop 138D while not ordinarily being toggled after the 59th pulse is in fact toggled so as to return the counters 138D, 138E, and 138F to a zero state. The ABDEF signal is derived as follows: The output of NAND gate 139' is is? This is inverted to DEF by inverter 146". The output of the inverter 146" is an input to NAND gate 139". A and B signals from flip-flops 138A and 1388 form the other two inputs to NAND gate 139". The output of NAND gate 139" is low when ABDEF signals are present at their respective flip-flops. The output of NAND gate 139" is thus m. This is coupled as one of the inputs to NAND gate 139"" along with a 6 input. The 6 input normally toggles flip-flop 138D. The presence of the ABDEF condition indicates the passage of the 59th pulse. Since the 59th pulse is indicated by ABDEF, going from ABDEF to ABDEF indicates passage of the 59th pulsev The occurrence of ABDEF is sensed by an output from gate 139" which toggles flip-flop 138D. The output of gate 139" is inverted by inverter 146' to form the T input to flipflop 138D, and is inverted again by inverter 146"" to form the T input for this flip-flop.

The output of the seconds counter (output F from flip-flop 138F) is connected to the input of the minutes counter. The minutes counter operates in precisely the same way as the seconds counter in that both counters

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Classifications
U.S. Classification368/87, 368/83, 968/947, 968/902
International ClassificationG04G3/02, G04G3/00, G04G9/04, G04G9/00, H03K21/00
Cooperative ClassificationH03K21/00, G04G3/02, G04G9/042
European ClassificationG04G3/02, G04G9/04B, H03K21/00